JPH0646776B2 - Decompression device for compression code - Google Patents

Description

The present invention relates to a decoding device for a compressed code by band compression encoding used for facsimiles, image electronic files and the like.

In an image transmission device such as a conventional facsimile or an image file device using an optical disk or a magnetic disk in recent years, by compressing and handling image data, the amount of data is reduced and transmission or storage operation is speeded up and efficiency is improved. I am trying to make it.

The image compression is a kind of so-called code conversion operation, and in the case of the modified Hoffman (MH) encoding which is a typical compression method, a continuous bit block of white or black pixels in an image is separately compressed. It is expressed in correspondence with the code. At this time, a compressed code having a short code length is made to correspond to a pixel bit block having a high occurrence frequency, while a compressed code having a long code length is made to correspond to a pixel bit block having a low occurrence frequency. The entire image is represented by another code string having a smaller number of bits by utilizing the bias in the occurrence frequency of the combination of.

Further, in the above-mentioned MH encoding, in addition to the compression code obtained by compressing the image information, the end-of-line signal (EOL code) indicating the delimiter for each line is transmitted.
This EOL code is used for line control of the print operation based on the decoding information, detection of the beginning of the compressed code to be decoded, etc., but it does not indicate actual image information.

In recent years, for example, a high-speed printer capable of forming a high-quality image such as a laser beam printer using an electrophotographic process has been developed, and a real-time reproduction (recording) of a compressed image is performed by such a printer. Is becoming desired. In order to perform this real-time decoding and reproduction, it is necessary to accurately obtain some synchronization relationship between the line-by-line recording of the printer and the decoding operation of the compressed code.

The present invention has been made in view of the above points, and an object of the present invention is to provide a decoding apparatus for a compressed code, which is sufficiently high quality and can sufficiently cope with image processing capable of high-speed image reproduction.

Another object of the present invention is to provide a compressed code decoding apparatus capable of performing a compressed code decoding operation in real time and supplying an uninterrupted image signal to a subsequent apparatus.

A further object of the present invention is to provide a compressed code decoding device capable of effectively synchronizing the decoding operation of the compressed code and the printer operation based on the decoded image information.

That is, according to the present invention, in a compression code decoding device for sequentially decoding compression codes of indefinite length including an EOL code indicating the end of each line of an image, storage means for successively storing a plurality of compression codes to be input. By shifting a plurality of compressed codes stored in the storage means,
By shifting the decoded compressed code from the storage means and setting the compressed code to be decoded next at a predetermined position of the storage means, and by decoding the compressed code set at the predetermined position of the storage means Decoding means for outputting the run length data and code length data of the compressed code, detecting means for detecting whether or not the EOL code exists in the storage means, and according to the code length data output from the decoding means Shift control means for controlling the shift amount of a plurality of compressed codes executed by the shift means, and recording means for recording an image at a constant speed line by line according to the run length data output from the decoding means,
When the detection means detects the EOL code in the storage means, the shift means discharges the EOL code from the storage means before the recording means records an image of each line, and a compression code following the EOL code is generated. Decoding of compressed code having a predetermined position in the storage means, and decoding control means for causing the decoding means to start decoding of the compressed code following the EOL code in synchronization with the start of image recording of each line by the recording means. A device is provided.

A detailed description of the invention is provided below.

First, an outline of an embodiment of the present invention will be described with reference to the circuit block diagram shown in FIG.

In FIG. 1, reference numeral 101 denotes a memory circuit, which has been input from a reader that photoelectrically reads an image, an electronic file that fails an image, or a receiver that receives image information through a transmission line such as a telephone line. A 16-bit (1 word) 16-bit (1 word) so-called MH (modifeyed Hoffman) code obtained by compression-encoding an image signal using a separate means
It is a circuit that stores data in a sequentially readable form in units, and can be realized by, for example, a RAM (random access memory) or a latch circuit. The storage format of the MH code in the storage circuit 101 is as shown in FIG. 2 (a). In other words, the MH code is inherently unequal in the code length (minimum 2 bits to maximum 13 bits), but regardless of the code length, there is no 1 bit vacancy,
As in (b), the serially linked bit string is converted into parallel every 16 bits and arranged. In FIG. 2 (b), WB and BB are MH codes indicating white and black pixels, respectively.
The number after BB and BB indicates the run length indicated by the code, for example, WB8 indicates white of run length 8.
This is the MH code. In this format, the MH code delimiter and the word (16 bit) delimiter do not necessarily match. Further, the memory circuit 101 has a function of sequentially outputting the subsequent words in parallel in accordance with external control.

In FIG. 1, 102 is a so-called multiplexer (data selector). Further, 103 is a register having 28-bit parallel input and output, which is given to the input side of the register 103 from the memory circuit 101 through the multiplexer 102.
The function of temporarily storing the MH code and the role of giving the MH code already stored in the register 103 as an output to the MH code decoding logic 104 and the MH code decoding table ROM (read only memory) 105 described later. Have a

The multiplexer 102 and the register 103 form a so-called bit shifter capable of serial shifting of data and jump shifting of n bits. This bit shifter is controlled by the outputs of the MH code decoding logic 104 and the MH code decoding RM105 which will be described later, and is stored in the register 103 from the memory circuit 101 regardless of the boundary of the MH code by the above method. It functions to store the MH code by shifting it by the required number of bits. FIG. 3 (details will be described later) is a diagram showing a detailed configuration of this bit shifter, and M shown in the register 103 as an example.
The H code string shows the state in which the MH code illustrated in the first memory circuit 101 in the first diagram has come to a position where the MH code WB ₁ (10011) indicating the white run length 8 can be decoded through appropriate control. There is. That is, the output C of the register 103 shown in FIG.
0, that is, the state in which the leading bit of the MH code is output to the LSB output is the position at which decoding is possible, and is hereinafter referred to as "completion of cueing". Therefore, the arrangement of the codes in the register 103 in FIG. 3 indicates that the MH code WB8 indicating the white run length 8 is in the “cue completed” state.

In FIG. 1, reference numeral 104 is an MH code decoding logic (hereinafter referred to as logic 104), and the following four types of codes, that is, the run length indicated by the MH code is shorter than the code length of the MH code, that is, the white run length. 1 (00 with MH code
0111, code length = 6> run length = 1), white run length 2 (MH code 0111, code length = 4> run length = 2), white run length 3 (MH code 100)
0, code length = 4> run length = 3) and black run length 1 (MH code 010, code length = 3> run length = 1).

In the following description, the above four types of MH codes indicating the white run length 1, the white run length 2, the white run length 3 and the black run length 1 will be collectively referred to as an HSC code. .

In FIG. 1, reference numeral 105 denotes an MH code decoding RM (hereinafter referred to as RM105), which is a circuit which mainly decodes all MH codes including four kinds of MH codes which the above-mentioned logic 104 takes charge of decoding.

The logic 104 and the ROM 105 divide the MH code responsible for decoding according to the difference in the processing speed and method of the MH code. These two decoders each time the MH code in the register 103 is "cue completed". ,
The run length of the MH code, the code length and the color of the black or white image, the make-up code or the terminate code, and the presence / absence of the code are detected.

Reference numeral 112 denotes an EOL detection circuit, which detects whether or not a code for line synchronization, that is, an end of line (EOL) code exists in the MH code stored in the register 103 in bit serial, and the storage position thereof. To do.

In FIG. 1, reference numeral 108 denotes a run length counter, which is a binary length capable of counting from the count number "0" to the maximum make up code run length, that is, "2650" or more.
It is a counter. The run length counter 108 outputs a count end signal (ripple / carry CR of the counter in this example) each time the run length of the MH code output from the logic 104 or the ROM 105 is counted.

109 is a flip-flop, which receives a count end signal (ripple-carry CR) from the run-length counter 108 and inverts the output each time. However, as will be described later, the output is controlled so as not to be inverted by the count-up signal of the make-up code. The output of this flip-flop 109 was read from the memory circuit 101.
It is an image signal obtained by decoding the MH code.

107 is a code length counter that can count the maximum code length of MH code of "13" or more. It is a binary counter that serializes or jump-shifts the MH code that was "completed" in register 103. As a result, the decoded code is swept out from the 103 register, and when the succeeding MH code is shifted to the "cue completed" position, the shift amount is counted and controlled.

106 is a 4-bit accumulator. As described above, the MH code fetched from the memory circuit 101 into the register 103 is sequentially swept out from the register 103 when it has been decoded, whereby an empty bit can be formed in the register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and each time 16 empty bits are generated, a new MH code is read from the memory circuit 101 by one word (16 bits).
The empty bit in the register 103 is complemented in parallel. Thus, the sequence of the MH code given from the register 103 to the logic 104 or the RM 105 is controlled so as not to be interrupted, thereby enabling a high-speed decoding operation.

Reference numeral 110 shows a control circuit for controlling input / output signals between the blocks 101 to 109 shown in FIG.

As described above, the MH code is converted into the image signal, that is, the MH code is decoded. The decoded image signal is a printer
The image is recorded on the recording material by being supplied to 111.
The printer 111 outputs a horizontal synchronizing signal HSYNC which is a synchronizing signal for each scanning, and this HSYNC is used for the timing of the decoding operation.

Next, examples of the present invention will be described more specifically. In the present embodiment, the image signal which is the result of decoding the MH code which is the image compression code is obtained by laser
It provides a so-called "high-speed, real-time MH decoder" used for direct output to a high-speed printer such as a beam printer. Therefore, the processing speed of the MH decoder and the image output of the MH decoder (in this example, the image frequency =
The problem of synchronization between high-speed printers such as laser beam printers should be solved. Therefore, in order to solve these problems, a desired "high-speed real-time MH decoder" is realized based on the processing method described below.

(1) MH decoder EL is synchronized with MH decoder for printer
And a horizontal synchronizing signal which is a synchronizing signal for each line of the printer.

(2) As shown in Fig. 1 register 103, the MH code that has been "cue completed" and decoded has been swept, and the subsequent MH code is shifted to the "cue completed" position by the code to be swept. Therefore, use one of two methods, jump shift and serial shift.

A specific configuration for achieving these two points will be described with reference to the drawings.

FIG. 8 is a perspective view showing the configuration of an embodiment of the laser beam printer shown as an example of the output section in FIG.

This printer is of an electrophotographic type using a laser beam, and 201 is a photosensitive drum rotatably supported in a housing Ha. Reference numeral 202 denotes a semiconductor laser that emits laser light La, and the emitted laser light La is made incident on the beam expander 203 and becomes a laser light having a predetermined beam diameter. Further, the laser light is incident on the polyhedral mirror 204 having a plurality of mirror surfaces. The polyhedral mirror 204 is rotated at a predetermined speed by a constant speed rotation motor 205. The laser light emitted from the beam expander 203 is scanned substantially horizontally by the polyhedral mirror 204. Then, an image is formed as spot light on the photosensitive drum 201 charged by the charger 213 to a predetermined polarity by the image forming lens 206 having the f-θ characteristic.

A beam detector 207 detects the laser light reflected by the reflection mirror 208, and the photosensitive drum 20 is detected by this detection signal.
The timing of the modulation operation of the semiconductor laser 202 is determined in order to give desired optical information on 1.

A high-resolution electrostatic latent image is formed on the photosensitive drum 201 by the laser light image-formed and scanned on the photosensitive drum 201. This latent image is visualized by the developing device 209, and then the cassette 210, 211
The image is transferred to a recording material stored in any one of the above, and the recording material is further passed through the fixing device 212, so that the image is fixed on the recording material and discharged as a hard copy to a discharge portion (not shown).

FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser of FIG. 8 with a predetermined image signal.

Image signal VI decoded and input from input terminal IN
DEO is a first line buffer 301 and a second line buffer 3 which are shift registers having a number of bits equal to the number of pixels for at least one scan for each image signal group for one scan.
02 is alternately input under the control of the buffer switch control circuit 303.

Further, the image signals input to the first line buffer 301 and the second line buffer 302 are alternately read for each scanning by using the beam detection signal from the beam detector 304 as a trigger signal and added to the laser driver 305.

The laser driver 305 modulates and controls the semiconductor laser 306 based on the input image signal to control the emission of laser light.

By having two line buffers, the image signals already stored in the other line buffer are output to the laser driver 305 while the image signals input one after the other are input to the laser driver 305. It can handle input.

The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as the horizontal synchronization signal HSYNC, and is used for synchronization between the decoding processing and the printer operation as described later.

The image signal decoded by the printer is input through two line buffers, that is, a buffer having a double buffer structure including a first line buffer 301 and a second line buffer 302. This double buffer structure is used to perform the correction operation when there is an error in the decoding operation. That is, if an error occurs in the decoding operation while the image signal decoded by the decoding circuit is being stored in one of the line buffers, the printing operation by the image signal of the current line in which the error has occurred is prohibited and the other line buffer is already in operation. The printing operation is performed by the stored image signal of the previous line.

As a result, printing is not performed due to the image signal that has been erroneously decoded, so that it is possible to remove the influence on the reproduced image.
It should be noted that the correction operation causes images of the same image signal to overlap at least two lines, but in the high-resolution (for example, 16 pel / mm) recording operation used in this example, the reproduced image is greatly affected. is not.

In FIG. 4, 105 is the MH code table ROM shown in FIG.
In reality, it is composed of a plurality of RMs (read only memory). Below is RM105
Explaining the contents of the above, AD0 to AD13 are RM105
0 to O11 are output terminals of the RM105. The format of the contents stored in ROM 105 is
L of MH code to be decoded supplied from register 103
Align SB bit with RM105 address terminal ADO
Each bit of the MH code is sequentially applied to the address terminals AD1 to AD11 of the RM105 in the MSB direction. Address pin AD13
Is a signal B / -ROM (black =
1, white = 0). If the MH code is shorter than 12 bits, the insufficient bits are ignored (DON'T
CARE). The EL code is treated as a make-up code. In addition, makeup of run length 1972 or more
Ignore the color code bit (AD13) of the up code (DON'TC
ARE).

The contents of the MH code to which each address is given are written in the ROM 105 as the storage data of the address determined as described above, and outputs corresponding to each MH code are output terminals O _{0 to} O ₁₁
Output to. That is, the output terminal 0 outputs the signal M / which becomes "1" when the decoded MH code is the make-up code and "0" when the decoded MH code is the terminate code.
MH code decoded at output terminal 1 is run length O
Of the white code (00110101) or the black code of run length O (0000110111), "0" is output, and at other times, a signal ▲ ▼ that is "1" is output.

The output terminals 2 to 5 output 4-bit outputs CLO to CL3 in a form in which each MH code length (bit number) is expressed in 2's complement.
However, the output terminal 5 is the LSB of the code length. The output terminals 6 to 11 output 6-bit outputs RL _{0 to} RL ₅ in the form in which the run length of each MH code is expressed in 2's complement. However, the output terminal 11 is the LSB of the run length. still,
For the make-up code, only the upper 6 bits of the binary representation of run length are assigned to the output terminals 6-11. This is because the make-up code in the MH code can express the run length with only the upper 6 bits. M in FIG. 4 shows the run length 8 white at 402.
The outputs 0 to O11 of the ROM 105 when the H code WB8 (10011) is decoded are illustrated. (The MH code table used in this embodiment is CCITT YELLOW BK Fascicle VII.2 Rec. T.4 TA.
According to BLE 1 / T.4 and TABLE2 / T.4).

In FIG. 4, reference numeral 104 denotes the MH code decoding logic shown in FIG. 1, and in this embodiment is a detection logic constituted by an AND gate and an OR gate. A signal output from the logic 104 is "0" when the HSC code, that is, the MH code indicating the white of the run lengths 1, 2 and 3 and the MH code indicating the black of the run length 1 is detected. The outputs ▲ ▼ to ▲ ▼ are the four types of M mentioned above.
Each code length of the H code (HSC code) is expressed by a binary number, inverted and output. Fig. 4 404
MH code white 1 WB1 (00
The output when 0111) is decoded is illustrated.

The reason why the logic circuit is used for decoding the HSC code is that the current ROM address method cannot sufficiently cope with time because of high-speed processing.

The operation of the bit shifter shown in FIG. 3 will be described with reference to Tables 1 and 2.

FIG. 3 shows the multiplexer shown in FIG. 1 and comprises two tri-state multiplexers 1021 and 1022. When the control line from the accumulator 106 to the multiplexer 102 is "0", the outputs A7 to A27 from the multiplexer 1022 side to the register 103 are all invalidated due to the tri-state floating.
The outputs A0 to A27 from the multiplexer 1021 side are valid for 103 and become the outputs C0 to C27 of the register 103. At that time, the multiplexer 1021 selects the input signals C0 to C27 from the register 103 by the input lines S0 to S2. Table 1 shows the selection method. For example, in the case of S ₀ = S ₁ = 1 and S ₂ = 0, the outputs C _{3 to} C ₂₇ of the register 103 are fetched and the outputs A _{0 to} A _{24, respectively.}
And output as.

Next, when the control line to the multiplexer 102 is "1",
The outputs A0 to A6 of the multiplexer 102 are selectively given from the multiplexer 1021 by the input lines S0 to S2 in the same manner as when the control line is "0". Output A7 from multiplexer 102
~ A27 multiplexers other than those indicated by Y in Table 2
Side becomes valid, and outputs A7 to A27 from the multiplexer 1021 side
Of those, those other than those indicated by Y in Table 2 become floating and are invalid. The outputs A7 to A27 given from the multiplexer 1022 to the register 103 are selected by the input lines Σ0 to Σ2 to the multiplexer 1022 as shown in Table 2, provided that the bit indicated by Y in Table 2 is the multiplexer 1021.
Selected from the side. The number of Y is the number of input lines ST7 to ST1 output corresponding to the input lines Σ0 to Σ2 to the multiplexer 1022.
It is set by controlling the tri-state state of the multiplexer 1021 by 1. The circuits of the multiplexers 1021 and 1022 in FIG. 3 can be easily realized by a commercially available multiplexer (for example, IC, F215, etc. manufactured by Fairchild, USA) and a gate circuit. Further, the outputs selected by A0 to A27 as the outputs to the register 103 in the multiplexer 102 are latched in the register 103 by the clock CK.

The bit shifter is configured as described above, and the memory circuit 101 enables shifting by an arbitrary number of bits for the MH code signal input in 16 bits parallel. As a result, the MH code of which the code lengths are not uniform can be brought into the above-mentioned "cue completion" state.

As described above, what is the MH code is determined by monitoring the code string moving in the register 103. The moving method is 1 by the bit shifter 102 or the like.
When a serial shift that moves bit by bit and an MH code that is treated as an HSC code are detected, a jump shift of up to 6 bits occurs. That is, the code string in the 103 register is controlled so that the maximum movement is 6 bits or less in one clock time.

Therefore, when the EOL code (000000000001) moves in the register 103, even if the movement amount is incorrect due to the progress from the previous time, the LS
The B bit always appears in C0 to C5 of the register 103.

Now, generally, when decoding an MH code, detection of the EL code is extremely important due to its code system. Hereinafter, the EOL detection circuit 112 shown in FIG. 1 will be described in detail.

That is, the EOL code is a code that separates each line of the image, and at the same time, it has a role of indicating the position of the MH code that follows it. Therefore, if the EOL code is missed during decoding, it immediately follows the MH code. The code delimiter becomes unknown and the image for one line cannot be decoded.
Also, the EOL of each subsequent image line cannot be detected depending on the detection method, and eventually the printed image is disturbed and spreads to the extent that it cannot be used.

Therefore, in the MH code string, even if there is a transmission / reception error, etc.
It is important to have an EOL detection method that does not cause an error in the detection of the EOL code even if the MH code is slightly wrong.

If the EOL code is reliably detected, the code error can be recovered within one image line.

FIG. 10 is a diagram showing a detailed configuration of the EOL detection circuit 112. As shown in FIG. 10, the LSB of the 12-bit EL code (000000000001) can be anywhere in C _{0 to} C ₅ of the register 103 so that at least one shift amount of the register, that is, 6 corresponds to 6 Seed detection gates 1001 are provided in parallel. As a result, the EL code detection failure is prevented by monitoring the data stored in the register 103. And the detection gate 1001 that detected the EOL code
From each of them, a detection signal indicating the position of the EOL code in the register 103 is output, as in ▲ ▼ to ▲ ▼.

This method prevents the EL detection from being mistaken unless the EOL code itself contains an error bit.

Therefore, the image code error can be recovered within one line without fail. Also, the probability that an error bit is included in the EOL code is extremely low compared to the probability that an error bit is included in the image code, and is extremely low in practical use and can be ignored.

FIG. 11 shows the details of the detection gate for detecting the EOL code. As shown in the figure, the configuration is such that 12-bit data is fetched in parallel, and 11-bit data excluding the MSB is applied to the 12-input NAND gate 1002 together with the above-mentioned MSB via the inversion gate INV. As a result, the EOL code is decoded, and when the EOL code is decoded, the output of the NAND gate 1002 becomes low level.

Outputs 0EOL to 5EOL of the EOL detection circuit 112 of FIG. 10 are transmitted to the code length counter 107 and the accumulator 106. Based on this signal, the accumulator 106 causes the register 103 to shift by the EOL code length.

That is, the EL detection circuit 112 shown in FIG. 10 indicates that the MH code or the FiLL code before the EOL code is stored in the register 103 from the detection position.
EOL may already be detected while the bit is still left. Therefore, among the EOL codes detected by the EOL detection circuit 112, an EOL code detection signal other than the signal ▲ ▼, that is, ▲
When ▼ to ▲ ▼ are detected, the accumulator 106 causes the remaining code before the EL code in the register 103 to be swept from the register 103 by the above-mentioned shift operation, and then the code length of the EL code, that is, 12 bits. Causes the register 103 to further perform the shift.

As a result, the EOL code has been swept out, and the state of the "image heading completed" of the image MH code at the beginning of the next line to be decoded is set. Further, by doing so, it is possible to eliminate the waste of time due to the decoding operation of the EOL code which is not the image information similarly to other compressed codes.

Next, a detailed description of the entire block diagram shown in FIG.
Use figures and the like. Since the operation of the circuit shown in FIG. 5 is complicated, some conditions are set to facilitate the explanation, and the decoding operation of the MH code which seems to be more general is taken as an example. The basic operation will be described, and then the establishment of the setting condition will be described.

FIG. 2 (b) is used as an example of the MH code string to be decoded. As the operating principle of this circuit, before the horizontal synchronizing signal HSYNC of the printer arrives, the EL code appearing at the end of FIG. 2 (b) is swept from the register 103 shown in FIG. 3 by the bit shift operation described above, The MH code WB ₈ indicating the white run length 8 which is the MH code next to the EL (that is, the MH code of the first image signal of the line to be decoded from now) is stored in the register 103 as “cue completed” as described above. It is assumed that the printer is waiting for HSYNC from the printer.

FIG. 6 is a time chart of the main part of the circuit shown in FIG. In FIG. 6, HSYNC 601 is a synchronizing signal in the main scanning direction of the printer described above, which is generated for each main scanning line. Using this as the reference for time chart, this time t ₀
And The CK 600 is the basic clock and its frequency is the same as the image frequency. VEN 602 is a section signal that defines an effective image section within the main scanning line. In addition, the iNi 603 has a pulse E one clock (one bit) before the start of the section signal VEN.
The OS 604 is a pulse of the last clock (bit) of the section signal VEN.

As described above, when the recording operation based on the image signal obtained by decoding the compressed code (MH code) is performed by the laser beam printer, the horizontal synchronizing signal HSYNC is set at the predetermined position of the scan line of the raster scan line by the laser beam. , Is based on a beam detection signal that detects the arrival of the laser light, and the section signal VEN is scanned by the laser light and the laser light scans the photoconductor (drum) on which a latent image is formed. Based on the section.

As is clear from these, the signals 600 to 6 in FIG.
The time relationship of 04 should generally be fixed to a fixed value. In this example, a fixed length of 64 clocks is set between HSYNC 601 and iNi 603. Further, the VEN 602 section has the number of pixels of one line, but in this example, it is set to 4096 bits (pixels).

In FIG. 6, at time t ₀ , the circuit of FIG. 5 is set to the initial state for each main scan of image output. That is, as described above, the MH code of the leading image of each line (WB ₈ (10011) indicating the white run length 8 in this example) is “cue completed” in the register 103, and the output of the register 103
C _{0 to} C ₁₂ ((10011.0010.000 in this example
1) is given to the logic 104, ROM 105, etc.

Similarly, the value of the code length counter 107 is (-1) = (1
111B). At this time, (-1) is defined to mean "cue completion". Also, each flip-flop 510,
109 and 515 are in the reset state, and flip-flop 509 is in the reset state.

Flip Flop 509 is set (Q = 1) means M
Indicates that the EOL code has been swept from the register 103 after detecting the HOL code EOL. As described later, the run length latch 513 is busy (B = 1) when the flip / flop 510 is set (Q = 1).
usy). Flip Flop 515 is B /
Output the ROM signal as output Q. The output of this flip-flop 515 is MH to be copied when it is 1.
It is a B / -ROM signal indicating that the color of the code is black. Similarly, when the output Q is 0, it indicates white.

Also, assume that the run length counter 108 is stopped,
Its value is O. The SFTEN 605 is a control line, and when it is 1, it means that the register 103 may shift data (MH code). Further, for simplicity, it is assumed that the output signals Σ0 to Σ2 and the signal of the accumulator 106 are O. That is, according to this assumption, 28 of register 103
All of the bits are valid MH code strings, indicating that there is no space.

The above is the state at time t _o . At time t ₁ , the flip-flop 509 shown in FIG. 5 is reset by the fall of the HSYNC signal 601 shown in FIG. 6, and the ▲ ▼ signal shown at 613 in FIG.
-SFTEN signal 605 goes to 1 through gate 508. When the SFTEN signal 605 is 1, the counter 107 shown in FIG. 6 is count enable. At the same time, the outputs C _{0 to} C ₁₂ held by the register 103 are given to the address of the ROM 105 at time t ₁ .
(10011XXXXXXXX in this example) and RM
Of the 105 outputs, the code lengths CL _{0 to} CL ₃ are gate 5
Code length counter 1 via 03 and gate 504
It is given to 07. At the same time, ▲ ▼ signal 607 is O
Therefore, the counter 107 enters the load mode and the values of CL ₀ to CL ₃ are loaded into the counter 107 by the clock of t ₁ . In this example, (-5) which is the two's complement of the code length 5 of the MH code WB ₈ indicating the white of the run length 8 is loaded.

Also, the outputs RL _{0 to} RL ₅ and M / of RM105 are provided as inputs to run length latch 513. At the same time, the Q output of the flip-flop 515 is also input to the run-length latch 513 as the B / -ROM signal 620. At this time, the RLCH signal 608 controls the latch 513 to be latch-enable by ₁ and changes the value of D _{0 to} D ₇ with the latch 51 at the clock of t _1.
Latch to 3.

At the same time, flip-flop 510 is set to 1 at time t ₁ . Also, flip-flop 515 is reversed. The BUSY signal 609, which is the Q output of the flip-flop 510, being 1 indicates that the latch 513 is latching a valid run length. Also, the fact that the B / -RM signal 620, which is the Q output of the flip-flop 515, is 1 means that the register 1
03 indicates that the color indicated by the MH code that should be “cue completed” is black. (Also, if the B / -RM signal 620 is O, the color is white.) The SFTEN signal 605 is given to the multiplexer 102 as the S signal via the gate 505 and the gate 506, and the data of the register 103 is stored. Control to shift by 1 bit. As a result, the transfer of the necessary data from the MH code in the register 103 to the subsequent stage is completed, so that the MH code has been used and is controlled by the SFTEN signal 605. Under the control of the counter 107 shown in FIG. Bit shift is performed until the carry-out signal CRO 606 is generated from the counter 107 as shown in, and the used MH code is registered.
Swept from 103. That is, in this example, the 1-bit shift of the register 103 is repeatedly continued until the value of the counter 107 set to -5 becomes the value of (-1).

When the value of the counter 107 becomes (-1), the MH that has been used now
Code (MH code WB that indicates white with run length 8 in this example)
After the sweep of 8) is completed, the next MH code (run length 6
The MH code BB ₆ ) that indicates the black color is “cue completed” in the register 103, but the latch 513 still has the previous MH code WB _8).
Flip Flop 51 due to the remaining run length
0 remains set. Therefore, when the CRO signal of the counter 107 becomes 1, the output of the gate 511 becomes 0,
Eventually, the SFTEN signal 605 becomes O, and the counter 107
Stops. Similarly, when the SFTEN signal 605 becomes O,
All of the S _{0 to} S ₂ signals also become O, the register 103 stops shifting, and the data is held. Therefore, "cue completion" BB ₆
The state of continues until time t ₂ .

At time t ₂ , the iNi signal 603 causes the ▲ ▼ signal 610 to go to O, and the run length (8 bits in this example) held in the latch 513 is transferred to the counter 108 by the ▲ ▼ signal 610 via the multiplexer 514. Be done. At the same time, the flip-flop 510 is reset by the signal 610. As a result, the latch 513 is emptied and the busy condition is eliminated. Therefore, the output of the gate 511 becomes 1 and the SFTEN signal 605 becomes 1 in the same manner as described above, and the run length obtained by the MH code which is “completion of cueing” in the register 103 is latched to the latch 513. .

Similarly, the MH code is sequentially decoded thereafter.

Based on (-5 in this example) run length is loaded into the counter 108 at time t _2, the generated from the next bit of the time t ₂
The VEN signal 602 causes the counter 108 to start counting.
Then, when the value of the counter 108 reaches (-1) (time t _{3 in} this example), the CR ₁ signal 611 is issued. Also, B / from Latch 513
A flip-flop 109 is set for each color of the image designated by signal 621. As a result, the first MH code could be converted into the image VIDEO (white 8 bits in this example) for the time being.

After the rising edge of the VEN signal 602, the iNi signal 603 remains O until a new HSYNC 601 arrives. Therefore V
After the EN signal 602 rises, for example, at time t ₃ , the iNi signal
CR ₁ instead of 603, showing the countup of counter 108
The signal 611 resets the flip-flop 510 to release its busy state, and the run length obtained by the subsequent decoding of the MH code can be taken into the latch 513.

By the way, in the above description, the code length of the MH code is equal to or shorter than the run length length,
If the used MH code to be swept out from the register 103 is serially shifted by setting the signals S0 = 1, S1 = S2 = 0 from the time point of “completion of cueing” the MH code, the MH code can be obtained. You can continue decoding without interruption. On the other hand, when the run length of the MH code is shorter than the code length, serial shifting is performed as described above while sweeping out the code from the register 103 (while shifting, 0 in the counter 108,
The run length of the MH code is completely counted. At this point, the next run length needs to be taken from the latch 513 to the counter 108 in order to eliminate the discontinuity of the image. However, since the register 103 is not in the “cue completed” state for the next MH code, the latch 513
It means that the run length that should be taken in is not output from ROM 105.

After all, in this case, the image recorded by the printer is interrupted, and the image cannot be output in real time. Such inconvenience occurs when decoding the above-mentioned HSC code, that is, the MH code indicating that the run lengths 1, 2 and 3 are white and the MH code indicating that the run length 1 is black.

Therefore, in such a case, only the above-mentioned four types of HSC codes, the MH code, are equivalent when serially shifted by the code length data CLO to CL3 from the ROM 105 using the MH code decoding logic 104. Activate the circuit in the latter stage. That is, the logic 104 generates a load value (-1) by the signal ▼ so that the counter 107 can be loaded with (-1), and loads it into the counter 107 through the gate 504.
At this time, the outputs CL0 to CL3 from ROM 105 are ▲ ▼
Inhibit at gate 503 by signal. In addition, the jump amount corresponding to the code length of the MH code decoded into the outputs SF1 and SF2 from the logic 104 is ▲ ▼ 〜 ▲
The signal is output as ▼ and the multiplexer 102 is operated via S0 to S2. As a result, it is possible to shift a plurality of bits in one bit time, in other words, "cue completion" in the register 103 of the next code to be decoded can be performed in one bit time. The jump amount is also input to the accumulator 106 and is cumulatively added to the number of empty bits in the register 103.

By the above two shift methods, a series of operations from "completion of cueing" to "run length latch" and "run length count" are repeated at high speed to execute decoding without interruption of the image supplied to the printer unit. An EOL detection circuit 112 outputs a signal OEOL when detecting that an EOL code appears at the outputs C0 to C11 of the register 103. When the EOL code indicating the end of one line is detected by the EOL detection circuit 112, the flip-flop 509 is set by the signal OEOL from the EOL detection circuit 112 via the timing adjustment circuit 523, and the signal 613 becomes O. . This eventually leads to S
Register until the FTEN signal 605 becomes O and the next HSYNC comes
103 is stopped, MH code is HSYNC with "cue completed"
You will have to wait. In this way, good synchronization between the printer and the decoding operation can be obtained.

An image is formed by repeating the scanning for each line as described above.

Next, the decoding error detection method will be described with reference to FIG. The circuit shown in FIG. 7 is connected to the appropriate position shown in FIG. 1 or 5. In FIG. 7, reference numeral 801 is an inverter.
802 is an adder, 803 is a latch, 804 is a comparator, 805 is a latch, and 806 and 807 are flip-flops.

7, 820 In FIG. 5, it is the same signal as the signal 820 output from the latch 513 through the multiplexer 514, and as described above, the run length of the result of decoding the MH code is 2
It is expressed in the complement of.

Now, the adder 802 and the latch 803 constitute an accumulator. The carry from the lower LSB of the adder 802 is 829 signals
It is set to 1 by (1) and eventually the output of adder 802 is 8
21 is the two's complement of the run length 820. Therefore output 821
Is a binary representation of the run length positive integer. Further, the addition to the latch 803 is continued at the timing of 610 in FIG. 6, that is, the timing of loading the run length to be counted into the counter 108 shown in FIG. The latch 803 is cleared for each line of the main scan and for each HSYNC signal 601 shown in FIG. That is, the output 822 of the latch 803 represents the cumulative value of the run length for each line by a binary number. On the other hand, the latch 805 has a constant run length for each line (in this example, 409 corresponding to the number of pixels on one line).
6) is held by being notified from the CPU or the like by the signal 824. The comparator 804 is the correct answer value 82 from the run length 822 (A) accumulated in the latch 803 and the latch 805.
It is a comparator circuit that compares 3 (denoted as B).

The flip-flop 806 is a comparator when the EOS signal 604 shown in FIG. 6 is output, that is, at the final bit of each line.
When the signal 831 indicating that A = B is not output from 804, it is set by the output 825 of the AND gate 808. That is, the setting of the flip-flop 806 means that the cumulative value A of the run length is the correct value B (40 in this example).
96) and that there is an error in the MH code or its decoding.

The flip-flop 807 is set immediately by the output 826 of the AND gate 809 which receives the signal 832 output from the comparator 804 when the condition of A> B is reached, even during the accumulation of run lengths. That is, the flip-flop's Q output 828 indicates that the cumulative run length value has exceeded the planned correct value (4096 in this example, that is, the number of pixels in the VEN 602 section) in the middle of the line. Indicates that a large erroneous decoding error has already occurred during the decoding of one line.

The flip-flops 806 and 807 are shown in FIG.
▼ 613 is "O", that is, EL (Eud of line) is not reset until the EOL detection circuit 112 detects the HSYNC 601 input, and is reset by the output of the gate 810 by the input of the HSYN signal 601. Therefore, by detecting the output 827 or the output 828 of each of the flip-flops 806 and 807 and devoting it to the EOL detection by the separate EOL detection circuit 112, it is possible to minimize the synchronization deviation due to a decoding error or the like.

In this example, the run length is cumulatively added by the accumulator, but this can be replaced with a method of sequentially subtracting the run length value from a predetermined number, for example, 4096, and detecting a borrow from the subtraction counter.

As described above, a decoding error occurs and the flip / flop
When 806 or 807 is set, its output is transmitted to the buffer switch control circuit 303 of the printer circuit shown in FIG.

The buffer switch control circuit 303 performs a buffer selection operation for alternately selecting the input / output of the line buffer of the printer having the double buffer structure as described above. Then, when the set signal from the flip-flop 806 or 807, that is, the decoding error detection signal is input, the image signal of the current line in which the decoding error occurs is invalidated, and the line of the previous line is replaced in place of the line in which the error occurred. In order to reuse the image signal, the selection control of the line buffer is performed so that the line buffer in which the image signal of the previous line is stored is read again. That is, for example, when a decoding error occurs while the image signal being decoded is being stored in the first line buffer 301, the image signal currently being stored in the first line buffer 301 is invalidated, and the image signal is currently read. After the reading of the second line buffer 302 is completed, the same image signal is read again from the second line buffer 302.

As a result, it is possible to eliminate the influence on the recorded image without performing the printing operation by the image signal of the line in which the decoding error occurs. It should be noted that the number of line buffers of the printer may be two or more in the same manner. A line buffer for correcting this error may be provided on the decoding circuit side.

Now, as described above, in this example, when decoding the MH coded image, the leading EL of the MH code is detected, and the decoding is started from the code following it as the first line of the image, Play the actual image.

This is because the MH-coded image is stored in, for example, an image memory or the like existing in the preceding stage of the storage circuit 101 shown in the first illustration, which is not shown in the present case. From there, the CPU or the like specifies the read start address of the image memory, reads the MH coded image, and supplies it to the decoder circuit via the memory circuit 101.

At that time, the MH code read from the image memory is, for example,
When reading from the middle of the image page, the EL code does not always come at the beginning. In order to start decoding correctly in this case as well, the first illustrated memory circuit 101 is set to the clear state before the decoding is started, and then the MH code read from the memory is full in the memory circuit 101 (state of FIG. 2). Until, the data (MH code) is sent to the inside of the decoder. Then, until the first EL code can be detected, it is not treated as an image code, and data is sent continuously one after another, and the focus is on detecting the EL code.

After the EL code is detected, the subsequent codes are treated as image information and are decoded while controlling the shift amount by the code length or the like. In this way, the first EL code is changed to the above-mentioned EO.
By finding it by the L detection circuit 112, it becomes possible to judge the delimiter of the MH code and to synchronously reproduce the image.

Now, after the decoding operation described above is started, the first input
When the operation of finding the EOL code of is started, data is sequentially sent from the memory circuit 101 to the register 103, but if all "0" s exist in the register 103 before the start, the memory circuit 101 actually Continuing with the MH code that came or part of the MH code (on the way), the EOL code (00000000000
1) will be erroneously detected. To avoid this, the initial state of the register 103 is all set to "1". That is, all of C _{0 to} C ₂₇ of the register 103 are set to “1”. This makes it possible to avoid the above-mentioned erroneous detection of EL.

A method of presetting all the registers 103 to "1" will be described. FIG. 12 shows an example of the structure of the register 103, that is, the register 103 is composed of 28 flip-flop F / Fs. Therefore, the preset pulse 901 is input from the CPU or the like to the preset terminals of all the flip-flops F / F, and the Q outputs of all the flip-flops are set to 1. Here, as the flip-flop F / F, for example, SN74S74N manufactured by American TI Co. can be used.

Although the present embodiment has been described by taking the decoding of the MH code as an example, the present embodiment can be applied to a decoding device for a code by another compression method. Also, the image signal after decoding can be used for various purposes such as displaying on a display such as a CRT or file as a bit image in addition to being recorded by a printer such as a laser beam printer. is there. Further, it goes without saying that the numerical values used in the present embodiment are not limited to those values, and may be appropriately selected depending on the application, environment and the like.

As described above, the decoding operation of the compressed code can be surely executed, and the decoding operation can be performed in real time even for the image processing that requires high speed processing. Further, it is possible to effectively decode and supply the compressed code to an output unit such as a printer that requires high-speed and high-quality image recording.

Further, it is possible to surely detect an abnormality related to the decoding operation or transmission of the compressed code, and to minimize the influence thereof.

Also, based on the image signal obtained by decoding the compressed code,
When the printing operation is performed, good synchronization can be obtained between the printer and the decoding processing unit.

Further, it is possible to surely detect the line synchronization code which is the reference of the decoding operation, and to eliminate the inconvenience such as the synchronization deviation of the decoding operation.

Further, even if the compressed code is supplied to the decoding circuit from the middle of one page or one line, the line synchronization in the decoding operation can be surely performed and erroneous decoding can be prevented.

As described above, according to the present invention, by decoding a plurality of compressed codes including the EOL code stored in the storage means, the decoded compressed code is discharged from the storage means and the compressed code to be decoded next is stored. The run length data and the code length data of the compressed code are output by decoding the compressed code set in the predetermined position of the storage means and the compressed code set in the predetermined position of the storage means. In the configuration in which the EOL code is present in the storage means in the case of recording at a constant speed, the EOL code is stored before the image recording of each line by the storage means when the EOL code is detected in the storage means. The compressed code following the EOL code is set at a predetermined position in the storage means, and the recording means opens the image recording of each line. Since the decoding of the compressed code following the EOL code is started in synchronism with the above, synchronization with the recording operation of the recording means for recording an image at a constant speed for each line without time delay due to detection and analysis of the EOL code, and The image recording operation and the decoding of the compressed code of each line following the EOL code can be executed in real time. Therefore, by the recording means for recording the image line by line at a constant speed,
An image represented by an indefinite length compression code including an EOL code can be recorded at high speed.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 (a) is a diagram showing a memory type of an MH code in a memory circuit 101, and FIG. 2 (b) is a plurality of MH codes. Shows a continuous state of the circuit, FIG. 3 is a circuit block diagram showing the configuration of a bit shifter, FIG. 4 is a circuit block diagram showing the configuration of an MH code decoding circuit, and FIG. 5 is a circuit block diagram shown in FIG. FIG. 6 is a detailed circuit diagram, FIG. 6 is a timing chart showing the operation timing of each part of the circuit shown in FIG. 5, FIG. 7 is a circuit block diagram showing the configuration of the decoding error detection circuit, and FIG. 8 is an example of the configuration of the printer. FIG. 9, FIG. 9 is a block diagram showing the circuit configuration for the printing operation of the printer shown in FIG. 8, FIG. 10 is a circuit block diagram showing the configuration of the EOL detection circuit, and FIG. 11 is the detection gate shown in FIG. Fig. 12 is a circuit diagram showing the configuration of A circuit diagram showing a configuration example, 101 memory circuit 102 is a multiplexer, 103 is a register, 104 MH code decoding Rojitsuku, 104 MH
It is a code table ROM.

Claims (1)

[Claims] 1. A compression code decoding device for sequentially decoding an indefinite length compression code including an EOL code indicating the end of each line of an image, and a storage means for storing a plurality of compression codes to be continuously input. Shift means for shifting the plurality of compressed codes stored in the storage means to discharge the decoded compressed code from the storage means and set the compressed code to be decoded next at a predetermined position of the storage means And decoding means for outputting the run length data and the code length data of the compressed code by decoding the compressed code set at a predetermined position of the storage means, and whether or not the EOL code exists in the storage means. And a plurality of compressed codes executed by the shift means according to the code length data output from the decoding means. Shift control means for controlling a shift amount, recording means for recording an image at a constant speed line by line according to the run length data output from the decoding means, and the detecting means for detecting the EOL code in the storage means. In this case, before recording the image of each line by the recording means, the EOL code is discharged from the storage means by the shift means, and a compression code following the EOL code is set at a predetermined position of the storage means, and the recording means is used. And a decoding control means for causing the decoding means to start decoding the compressed code following the EOL code in synchronization with the start of image recording of each line.