JPH0646777B2 - Decompression device for compression code - Google Patents

Description

The present invention relates to a decoding device for a compressed code by band compression encoding used for facsimiles, image electronic files and the like.

In an image transmission device such as a conventional facsimile or an image file device using an optical disk or a magnetic disk in recent years, by compressing and handling image data, the amount of data is reduced and transmission or storage operation is speeded up and efficiency is improved. I am trying to make it.

The image compression is a kind of so-called code conversion operation, and in the case of the modified Hoffman (MH) encoding which is a typical compression method, a continuous bit block of white or black pixels in an image is separately compressed. It is expressed in correspondence with the code. At this time, a compressed code having a short code length is made to correspond to a pixel bit block having a high occurrence frequency, while a compressed code having a long code length is made to correspond to a pixel bit block having a low occurrence frequency. The entire image is represented by another code string with a smaller number of bits by utilizing the bias in the occurrence frequency of the combination of.

Incidentally, the correspondence of the compressed code to the pixel bit block is determined based on an empirical rule, and the code lengths of the compressed code are not uniform.

Further, since the number of pixels individually expressed by the code is different, the image reproduction time corresponding to the code is also different. Therefore, it is difficult to obtain the timing of fetching the coded code to be decoded next into the decoding circuit. However, for example, when a printer or the like that cannot be intermittently driven is used as the image reproducing apparatus, the decoding circuit must supply the decoded data to the printer without interruption, and the decoding of continuous encoded codes also corresponds to it. There is a need.

Further, among the compressed codes obtained by the MH encoding described above, there are some compressed codes whose run length is shorter than the code length. When such compressed codes are decoded, the run length obtained by the high speed printer is The compressed code to be decoded next is not ready before the end of the image reproduction corresponding to, and in such a case, there is a possibility that the decoding operation of the compressed code is not in time for the image reproduction of the high speed printer.

The present invention has been made in view of the above points. By continuously supplying a compression code of an indefinite length including a specific compression code whose run length is shorter than the code length to a decoding means, a plurality of continuous codes can be obtained. For the purpose of high-speed decoding of the compressed code of and the output of the decoded image data to the device at the subsequent stage without interruption, in detail, in the decoding device of the compressed code that sequentially decodes the compressed code of indefinite length, The storage means stores a plurality of codes continuously, the reading means for reading the compressed code from the storage means in parallel for a predetermined number of bits, and the storage capacity for the number of bits larger than the predetermined number of bits. Storage means for successively storing a plurality of compressed codes read by the storage means, and a compression code to be decoded next by shifting the plurality of compressed codes stored in the storage means. A shift means for setting a code at a predetermined position of the storage means, and a decoding means for outputting the run length data and the code length data of the compressed code by decoding the compressed code set at the predetermined position of the storage means, When the compressed code decoded by the decoding means is not a specific compressed code having a run length shorter than the code length, the shift means sequentially executes shifts according to the code length data, and the specific compressed code. In the case of, the shift control means for causing the shift means to execute the shift according to the code length data at a time, the addition means for cumulatively adding the code length data output from the decoding means, and the addition means By controlling the storage position in the storage means of a predetermined bit parallel compressed code which is newly stored according to the added value. Providing a compressed code decoding device having storage control means for connecting a predetermined bit parallel compressed code newly read from the storage means to a previously stored compressed code and additionally storing the compressed code in the storage means. Is.

Details of the present invention will be described below.

First, an outline of an embodiment of the present invention will be described with reference to the circuit block diagram shown in FIG.

In FIG. 1, reference numeral 101 denotes a memory circuit, which has already been input from a reader that photoelectrically reads an image, an electronic file that fails an image, or a receiver that receives image information via a transmission line such as a telephone line. A 16-bit (1 word) MH (Modified Eye Hoffman) code, which can be obtained by compressing and coding an image signal using a separate means, is used.
It is a circuit that stores data in a sequentially readable form in units, and can be realized by, for example, a RAM (random access memory) or a latch circuit. The storage format of the MH code in the storage circuit 101 is as shown in FIG. 2 (a). That is, the MH code has an irregular nature of the code length (minimum 2 bits to maximum 13 bits), but regardless of the code length, there is no 1-bit vacancy and the MH code shown in FIG.
As in (b), the serially linked bit string is converted into parallel every 16 bits and arranged. In FIG. 2 (b), WB and BB are MH codes indicating white and black pixels, respectively, and the numbers after WB and BB represent the run lengths indicated by the codes. For example, WB8 is run length 8
Is an MH code indicating white. In this format, the MH code delimiter and the word (16 bit) delimiter do not necessarily match. In addition, the memory circuit 101 has a function of outputting subsequent words sequentially and in parallel in accordance with external control.

In FIG. 1, 102 is a so-called multiplexor (data selector). Further, 103 is a register having a 28-bit parallel input and an output, and from the memory circuit 101,
A function for temporarily storing the MH code given to the input side of the register 103 via the multiplexer 102 and an MH code decoding logic 104 and MH code decoding which will be described later using the MH code already stored in the register 103 as an output.・ Table ROM (read only memory)
It has a role to give to 105 etc.

The multiplexer 102 and the register 103 form a so-called loose bit shifter capable of serial and n-bit jump shift of data. This bit shifter is controlled by the outputs of the MH code decode logic 104 and the MH code decode RM105, which will be described later, and the MH code stored in the register 103 by the above-mentioned method regardless of the boundary of the MH code. It has the function of storing the code by shifting it by the required number of bits. FIG. 3 (details will be described later) is a diagram showing a detailed configuration of the bit shifter. The MH code string exemplified in the register 103 is the M code exemplified in the memory circuit 101 shown in FIG.
The MH code WB, which moves the H code into the register 103 through appropriate control and further shows the white run length 8.
1 (10011) is at a position where it can be decoded. That is, the output C0 of the register 103 shown in FIG. 3, that is, the state in which the leading bit of the MH code is output to the LSB output is set as a decodable position, and “cueing is completed” in the future.
Called. Therefore, the arrangement of the codes in the register 103 in FIG. 3 indicates that the MH code WB8 indicating the white run length 8 is in the "cue completion" state.

In FIG. 1, 104 is an MH code decoding logic (hereinafter referred to as a logic 104), which is the following four types of codes, that is, the run length indicated by the MH code is shorter than the code length of the MH code, that is, white code. Run length 1 (MH
Code is 000111, code length = 6> length =
1), white run length 2 (MH code 0111, code length = 4> run length = 2), white run length 3
(1000 in MH code, code length = 4> run length = 3) and black run length 1 (010 in MH code,
This is a circuit for decoding code length = 3> run length = 1). In the following explanation, the above four MH codes indicating the white run length 1, the white run length 2, the white run length 3 and the black run length 1, respectively, are collectively referred to as HS.
I will call it C code.

In FIG. 1, 105 is MH / code / decode / RM.
(Hereinafter referred to as RM105), and the above-mentioned logic 10
All MHs, including 4 MH codes, 4 of which is responsible for decoding
-A circuit that mainly decodes codes.

The logic 104 and the ROM 105 classify the MH code responsible for decoding according to the processing speed and method of the MH code, and these two decoders each time the MH code in the register 103 is "cue completed". The run length of the MH code, the code length, and the color of the image of black or white, and make-up
It outputs whether the code or the termination code is present or not.

Reference numeral 112 denotes an EOL detection circuit which detects whether or not a code for line synchronization, that is, an end of line (EOL) code exists in the MH code stored in the register 103 in bit serial, and the storage position thereof.

In FIG. 1, reference numeral 108 denotes a run length counter, which is a binary counter capable of counting from the count number "0" to the run length of the maximum make-up code, that is, "2560" or more. This run length counter 10
Reference numeral 8 outputs a count end signal (ripple / carry CR of the counter in this example) each time the run length of the MH code output from the logic 104 or ROM 105 is counted.

The flip-flop 109 receives the count end signal (ripple-carry CR) from the run-length counter 108 and inverts the output each time. However, as will be described later, the output is controlled so as not to be inverted by the count-up signal of the make-up code. The output of the flip-flop 109 is an image signal obtained by decoding the MH code read from the memory circuit 101.

Reference numeral 107 is a code length counter, which is a binary counter capable of counting the maximum code length “13” or more of the MH code, and “cue completed” in the register 103.
By performing serial shift or jump shift of the MH code that was being performed, the decoded code is 103
When the MH code is swept from the register and the subsequent MH code is shifted to the "cue completed" position, the shift amount is counted and controlled.

106 is a 4-bit accumulator. As described above, the MH fetched from the memory circuit 101 in the register 103
Once the code has been decoded, it is sequentially swept from register 103, which creates an empty bit in register 103. Therefore, the accumulator 106 counts the number of empty bits in the register 103, and every time 16 empty bits are created, a new MH code is added from the memory circuit 101 to the empty bits in the register 103 in one word (16 bits) in parallel. To do. As a result, the MH code sequence from the register 103 to the logic 104 and others is controlled so as not to be interrupted, thereby enabling a high-speed decoding operation.

Reference numeral 110 represents a control circuit for controlling input / output signals between the blocks 101 to 109 shown in FIG.

As described above, the MH code is converted into an image signal, that is, MH.
The code is decrypted. The decoded image signal is supplied to the printer 111, and an image is recorded on the recording material.
The printer 111 outputs a horizontal synchronizing signal HSYNC which is a synchronizing signal for each scanning, and this HSYNC is used for the timing of the decoding operation.

Next, examples of the present invention will be described more specifically. The present embodiment is a so-called "high speed" used for directly outputting an image signal resulting from decoding an MH code which is an image compression code to a high speed printer such as a laser beam printer without providing any image memory.・ Real time MH decoder. Sub connexion, image output processing speed high speed and MH-decoder of MH-decoder (this example assumes an image frequency = + number MH _Z) and the laser beam
The problem of synchronization with high speed printers such as printers must be solved. Therefore, in order to solve these problems,
A desired "high-speed, real-time MH-decoder" is realized based on the processing method described below.

(1) The MH / decoder and the printer are synchronized with the EL of the MH code and the horizontal synchronizing signal which is a synchronizing signal for each line of the printer.

(2) Sweeps out the MH code that has been decoded by "completion of cueing" in register 103 of Fig. 1 and succeeding MH
As a method for shifting the code to the "cue completed" position, either one of two methods, jump shift and serial shift, is used depending on the code to be swept.

A specific configuration for achieving these two points will be described with reference to the drawings.

FIG. 8 is a perspective view showing the configuration of an embodiment of the laser beam printer shown as an example of the output section in FIG.

This printer is of an electrophotographic type using a laser beam, and 201 is a photosensitive drum rotatably supported in a housing Ha. Reference numeral 202 denotes a semiconductor laser that emits a laser beam La, and the emitted laser beam La is made incident on the beam expander 203 and becomes a laser beam having a predetermined beam diameter. Further, the laser light is incident on a polyhedral mirror 204 having a plurality of mirror surfaces. Polyhedral mirror 204
Is rotated at a predetermined speed by a constant speed rotary motor 205. The laser light emitted from the beam expander 203 is scanned substantially horizontally by the polygon mirror 204. And f
An image is formed as spot light on the photosensitive drum 201 charged to a predetermined polarity by the charger 213 by the image forming lens 206 having the −θ characteristic.

A beam detector 207 detects the laser light reflected by the reflection mirror 208, and the photosensitive drum is detected by this detection signal.
The timing of the modulation operation of the semiconductor laser 202 is determined in order to provide desired optical information on the 201.

A high-resolution electrostatic latent image is formed on the photosensitive drum 201 by the laser light image-formed and scanned on the photosensitive drum 201. This latent image is visualized by the developing device 209, and then the cassette 210,
The image is transferred onto a recording material housed in any one of 211 and further passed through the fixing device 212, so that the image is fixed on the recording material and discharged as a hard copy to a discharge portion (not shown).

FIG. 9 shows an embodiment of a printer circuit for modulating the semiconductor laser of FIG. 8 with a predetermined image signal.

Image signal VI decoded and input from input terminal IN
DEO is a first line buffer 301 and a second line buffer 301, each of which includes a shift register having a number of bits equal to the number of pixels for at least one scan for each image signal group for one scan.
The signals are alternately input to 302 under the control of the buffer switch control circuit 303.

Further, the first line buffer 301 and the second line buffer 301
The image signal input to 302 is alternately read for each scanning by using the beam detection signal from the beam detector 304 as a trigger signal and applied to the laser driver 305.

The laser driver 305 modulates and controls the semiconductor laser 306 based on the input image signal to control the emission of laser light.

By having two line buffers, the image signals already stored in the other line buffer are output to the laser driver 305 while the image signals input one after the other are input to the laser driver 305. It can handle input.

The beam detection signal from the beam detector 304 is also transmitted to the decoding processing circuit as the horizontal synchronizing signal HSYNC, and is used for synchronizing the decoding processing and the printer operation as described later.

The image signal decoded by this printer is input via two line buffers, that is, a buffer having a double buffer structure consisting of a first line buffer 301 and a second line buffer 302. This double buffer structure is used to perform the correction operation when there is an error in the decoding operation. That is, if an error occurs in the decoding operation while the image signal decoded by the decoding circuit is being stored in one of the line buffers, the printing operation by the image signal of the current line in which the error has occurred is prohibited and the other line buffer is already in operation. The printing operation is performed by the stored image signal of the previous line.

As a result, printing is not performed due to the image signal that has been erroneously decoded, so that it is possible to remove the influence on the reproduced image.
It should be noted that the correction operation causes images of the same image signal to overlap by at least two lines, but in the high-resolution (for example, 16 Pel / mm) recording operation used in this example, the reproduced image is significantly affected. is not.

In FIG. 4, 105 is the MH code table ROM shown in FIG. 1, which is actually composed of a plurality of RMs (read only memory). Below R
Explaining the contents of M105 schematically, AD _{0 to} AD13 are R
Address terminal of M105, and 0 to 011 are RM
Output terminal of 105. The format of the contents stored in the ROM 105 is the MH to be decoded supplied from the register 103.
Align the LSB bit of the code to the address terminal AD0 of RM105, and sequentially set each bit of each MH code in the MSB direction.
It is given to AD1 to AD11 of the address terminal of M105.
A signal B / indicating the color of the MH code is supplied to the address terminal AD13.
-ROM (black = 1, white = 0) shall be given.
If the MH code is shorter than 12 bits, the insufficient bits are ignored (DON'T CARE). The EL code is treated as a make-up code. Also run length 1
Bits of 792 or more makeup code by color (AD13)
Is ignored (DON'T CARE).

In the ROM 105, the contents of the MH code to which each address is given are written as the storage data of the address determined as described above, and the output corresponding to each M MH code is output terminal O.
Output to 0 to O11. That is, the output terminal 0 outputs a signal M / which becomes "1" when the decoded MH code is a make-up code and "0" when it is a terminate code. The output terminal 1 outputs a "0" when the decoded MH code is a run length 0 white code (00110101) or a run length 0 black code (000010111), and is a signal "1" otherwise.
Is output.

Output terminals 2 to 5 are 4-bit outputs CL0 to CL3 in the form in which the code length (bit number) of each MH code is expressed in 2's complement.
Is output. However, the output terminal 5 is the LSB of the code length. The output terminals 6 to 11 output 6-bit outputs RL0 to RL5 in a format in which the run length of each MH code is represented in 2's complement. However, the output terminal 11 is the LSB of the run length.
Is. For the make up code, only the upper 6 bits of the run length binary number expression are output terminal 6
Assign to ~ 11. This is because the make-up code in the MH code can express its run length only in the upper 6 bits. Run length 8 at 402 in Figure 4
Outputs _{0 to} 11 of the ROM 105 in the case of decoding the MH code WB8 (10011) indicating the white color of FIG. (The MH code table used in this embodiment is CCITT YELLOW-BK Fa.
scicle VII.2 Rec.T.4 According to TABLE 1 / T.4 and TABLE 2 / T.4. 4) In FIG. 4, 104 is the MH code decoding logic shown in FIG. 1, and in this embodiment is a detection logic constructed by an AND gate and an OR gate. Logic 10
The signal (4) which is the output of 4 becomes "0" when the HSC code, that is, the MH code of run lengths 1, 2 and 3 indicating white and the MH code of run length 1 indicating black are detected. The outputs ▲ ▼ to ▲ ▼ represent the code lengths of the above-mentioned four types of MH codes (HSC codes) in binary numbers, which are inverted and output. Fig. 1
MH code white 1 WB1 showing run length 1 white on 404
The output when (000111) is decoded is illustrated.

The reason why the logic circuit is used for decoding the HSC code is that the current ROM address system cannot sufficiently cope with time because of high speed processing.

The operation of the bit shifter shown in FIG. 3 will be described with reference to Tables 1 and 2.

FIG. 3 102 shows the multiplexer shown in FIG. 1 and comprises two tri-state multiplexers 1021 and 1022. When the control line from the accumulator 106 to the multiplexer 102 is “0”, all the outputs A _{7 to} A ₂₇ from the multiplexer 1022 side to the register 103 are invalidated by the tri-state floating and become invalid in the register 103. Are the outputs A _{0 to} A from the multiplexer 1021 side
₂₇ becomes valid and becomes the outputs C _{0 to} C ₂₇ of the register 103. At that time, the multiplexer 1021 selects the input signals C _{0 to} C ₂₇ from the register 103 by the input lines S _{0 to} S ₂ .
Table 1 shows the selection method. For example, S ₀ = S ₁ = 1 and S ₂
In the case of = 0, the outputs C _{3 to} C ₂₇ of the register 103 are taken in and selected and output as outputs A _{0 to} A ₂₄ , respectively.

Next, when the control line to the multiplexer 102 is “1”, the outputs A _{0 to} A ₆ of the multiplexer 102 are selectively selected by the input lines S _{0 to} S ₂ from the multiplexer 1021 in the same manner as when the control line is “0”. Given to. Output from multiplexer 102 A ₇ ~
The multiplexer 1022 side is valid except for A ₂₇ indicated by Y in Table 2, and the outputs A _{7 to} A ₂₇ on the multiplexer 1021 side other than Y indicated in Table 2 are floating and invalid. The outputs A _{7 to} A ₂₇ given from the multiplexer 1022 to the register 103 are the multiplexers as shown in Table 2.
It is selected by the input lines Σ ₀ to Σ ₂ to 1022, except that the bit indicated by Y in Table 2 is selected from the multiplexer 1021 side. The number of Y is set by controlling the tri-state state of the multiplexer 1021 by the input lines ST7 to ST11 output corresponding to the input lines Σ ₀ to Σ ₂ to the multiplexer 1022. The circuits of the multiplexers 1021 and 1022 in FIG. 3 are commercially available multiplexers (for example, IC.F251 manufactured by Fairchild, USA).
And can be easily realized by a gate circuit or the like. Further, in the multiplexer 102, A ₀ to
The output selected by A ₂₇ is registered in register 10 by clock CK.
Latch to 3.

The bit shifter is configured as described above, and it is possible to shift the MH code signal input from the memory circuit 101 in 16 bit parallel by an arbitrary number of bits. This allows
For MH codes with irregular code lengths, the above-mentioned "cue completed"
Can be in a state.

As described above, what is the MH code is determined by observing the code string moving in the register 103. The moving method is a serial shift in which the bit shifter 102 or the like moves one bit at a time. When an MH code treated as an HSC code is detected, a jump shift of up to 6 bits occurs. That is, the code string in the 103 register is controlled so that it can be moved at most 6 bits or less within one clock time.

Therefore, when the EOL code (000000000001) moves in the register 103, the LSB bit always appears in C _{0 to} C ₅ of the register 103 even if the amount of movement is incorrect due to the passage from the previous time.

By the way, generally, when decoding an MH code, it is extremely important to detect the EL code from the code system. Hereinafter, the EL detection circuit 112 shown in FIG. 1 will be described in detail.

That is, the EOL code is a code that separates each line of the image, and at the same time, it has the role of indicating the position of the MH code that follows it. The MH code delimiter becomes unknown and the image for one line cannot be decoded. Also, the EOL of each subsequent image line cannot be detected depending on the detection method, and in the end, the image disturbance printed out can hardly be used. It will spread to a degree.

Therefore, it is important to have an EOL detection method that does not cause an error in the detection of the EOL code even if the MH code in the MH code sequence is slightly wrong due to transmission / reception errors.

If the EOL code is reliably detected, the code error can be recovered within one image line.

FIG. 10 is a diagram showing a detailed configuration of the EOL detection circuit 112. As shown in FIG. 10, the LSB of the 12-bit EL code (000000000001) can be anywhere in C _{0 to} C ₅ of the register 103 so that at least one shift amount of the register, that is, 6 corresponds to 6 Seed detection gate 1001
Installed in parallel. This prevents the EL code from being missed by monitoring the data stored in the register 103. And the detection gate 10 that detected the EOL code
From 01, EOL like ▲ ▼ 〜 ▲ ▼ respectively
A detection signal indicating the position of the code in the register 103 is output.

This method prevents the EL detection from being mistaken unless the EOL code itself contains an error bit. Therefore, the image code error can be recovered within one line without fail. Also, the probability that an error bit is included in the EOL code is extremely low compared to the probability that an error bit is included in the image code, and is extremely low in practical use and can be ignored.

FIG. 11 shows details of the detection gate for detecting the EOL code. As shown in the figure, the configuration is such that 12-bit data is fetched in parallel. The 11-bit data excluding the MSB is transferred to the 12-bit data together with the above-mentioned MSB through the inverting gate INV.
Applied to the input NAND gate 1002. This causes the EOL code to decode. When the EOL code is decoded, the output of the NAND gate 1002 becomes low level.

Outputs 0EOL to 5EOL of the EOL detection circuit 112 of FIG. 10 are transmitted to the code length counter 107 and the accumulator 106. This signal causes the accumulator 106 to
The register 103 shifts the code length of the code.

That is, the EL detection circuit 112 shown in FIG. 10 may already detect EOL from the detection position while the MH code or the Fill bit still remains before the EOL code in the register 103. Therefore, when an EOL code detection signal other than the signal ▲ ▼, that is, ▲ ▼ to ▲ ▼, is detected in the EOL code detected by the EOL detection circuit 112, the accumulator 106 outputs the EOL code in the register 103.
After the remaining code before the L code is swept from the register 103 by the shift operation described above, the register 103 is further shifted by the code length of the EL code, that is, 12 bits.

As a result, the EOL code has been swept out, and the state is that of "heading out" of the first image MH code of the next line to be decoded. In addition, this also eliminates the waste of time due to the decoding operation of the EOL code that is not image information in the same manner as other compressed codes.

Next, a detailed description of the entire block diagram shown in FIG.
Use figures and the like. Since the operation of the circuit shown in FIG. 5 is complicated, some conditions are set for facilitating the explanation, and the decoding operation of the MH code which seems to be more general is taken as an example to explain the basic operation of the circuit. I will explain the operation, and then
The establishment of the setting conditions will be described.

Fig. 2 (b) as an example of the MH code string to be decoded
Will be used. And, as the operating principle of this circuit, before the horizontal sync signal HSYNC of the printer arrives,
The EL code appearing at the end of (b) is the register 1 shown in FIG.
Swept from 03 by the above-mentioned bit shift operation, and E
The MH code WB8 indicating the white run length 8 which is the next MH code (that is, the MH code of the first image signal of the line to be decoded) at L is the register 103
As described above, the HS
Suppose YNC is waiting.

FIG. 6 is a time chart of the main part of the circuit shown in FIG. In FIG. 6, HSYNC 601 is a synchronizing signal in the main scanning direction of the above-mentioned printer, which is generated for each main scanning line. This is used as the standard for time chart, and this time is t ₀
And The CK600 is the basic clock and its frequency is the same as the image frequency. VEN 602 is a section signal that defines the effective image section within the main scanning line. INi 603 is the pulse one clock (one bit) before the start of the interval signal VEN, and EOS 604 is the last clock (bit) of the interval signal VEN.
Is the pulse of. As described above, the compressed code (MH
The recording operation based on the image signal obtained by decoding
When using a beam printer, the horizontal synchronization signal HSYNC is based on the beam detection signal that detects when the laser light reaches the predetermined position of the scan line of the raster scan line by the laser light, and the interval signal VEN is the laser signal. It is based on the section where the laser beam scans the photosensitive member (drum) which is scanned by light to form a latent image.

As is clear from these, the signals 600 to 600 in FIG.
The time relationship of 604 should generally be fixed to a fixed value. In this example, a fixed length of 64 clocks is set between HSYNC 601 and iNi 603. In addition, the section of VEN 602 is 1
The number of pixels in a line is 4096 bits (pixels) in this example.

In FIG. 6, at time t ₀ , the circuit of FIG. 5 is set to the initial state for each main scan of image output. That is,
As described above, the MH code of the leading image of each line (WB ₈ (10011) indicating the white run length 8 in this example) is “cue completed” in the register 103, and C ₀ to C ₁₂ (10011.0010.0 in this example)
001) is given to the logic 104, ROM 105, etc.

Similarly, the value of the code length counter 107 is (-1)
= (1111B) At this time, (-1) is defined to mean "cue completion". Also, each flip-flop 510,109,515 is in reset state, flip-flop
509 is in set state.

Since the flip-flop 509 is set (Q = 1), it is detected from the register 103 after detecting the EOL of the MH code.
Indicates that the sweep of the EOL code has been completed. Also, the flip-flop 510 is set (Q =
The state of 1) is the run length ratchet 513 as described later.
Is busy (BuSY). Flip Flop
515 outputs the B / -ROM signal as output Q. When the output Q of the flip-flop 515 is 1, it indicates that the color of the MH code to be decoded is black B /
A ROM signal. Similarly, when the output Q is 0, it indicates white.

Also, assume that the run length counter 108 is stopped,
The value is assumed to be 0. SFTEN605 is a control line and when it is 1, it means that the register 103 can shift data (MH code). Further, for simplicity, it is assumed that the output signals Σ _{0 to} Σ ₂ and the signal of the accumulator 106 are 0. That is, based on this assumption, 2 of register 103
All 8 bits are a valid MH code string, indicating a non-empty state.

The above is the state at time t ₀ .

Now, at time t ₁ , the flip-flop 509 of FIG. 5 is reset due to the fall of the HSYNC signal 601 shown in FIG. 6, and the ▲ ▼ signal shown by 613 in FIG. 6 becomes 1.
The SFTEN signal 605 goes to 1 via the AND gate 508. science fiction
When the TEN signal 605 is 1, the counter 107 shown in FIG. 6 is count enable. At the same time, at time t ₁ , ROM 10
At the address of 5, the outputs C ₀ to C held by the register 103 are held.
_Twelve is given. (10011 ××××××××× in this example)
And of the output of RM105, code length CL ₀
˜CL ₃ is given to the code length counter 107 via the gate 503 and the gate 504. At the same time ▲
Since the signal 607 is 0, the counter 107 becomes a load mote and the values of CL ₀ to CL ₃ are loaded into the counter 107 by the clock of t ₁ . In this example, it is the two's complement of the code length 5 of the MH code WB8 indicating run length 8 white (-
5) is loaded.

It is also provided as the output of RM 105, RL _{0 to} RL _5, and the input of M / run length latch 513. At the same time, the Q output of the flip-flop 515 is also input to the run-length latch 513 as the B / -ROM signal 620. At this time, the RLCH signal 608 controls the latch 513 to be latch enable by ₁ and the value of D0 to D7 is latched to the latch 513 at the clock of t ₁ .

At the same time, flip-flop 510 is set to 1 at time t ₁ . The flip-flop 515 is reversed. The fact that the BUSY signal 609, which is the Q output of the flip-flop 510, is 1 indicates that the latch 513 is latching a valid run length. Also, the fact that the B / -ROM signal 620, which is the Q output of the flip-flop 515, is 1, means that
103 indicates that the color indicated by the MH code that should be "cue completed" is black. (Also, if B / -RM620 is 0, the color is white.) The SFTEN signal 605 is given to the multiplexer 102 as the S signal through the gate 505 and the gate 506, and the register 10
Control so that the data of 3 is shifted by 1 bit. As a result, the transfer of the necessary data from the MH code stored in the register 103 to the subsequent stage is completed, so that the MH code has been used and is controlled by the counter 107, which is enabled to count by the SFTEN signal 605 in FIG. Bit shift is performed from the counter 107 until the carry-out signal CRO 606 is generated as shown in FIG.
The H code is swept from register 103. That is, in this example, the one-bit shift of the register 103 is continuously repeated until the value of the counter 107 set to -5 becomes the value of (-1).

When the value of the counter 107 reaches (-1), the MH code that has been used now (in this example, the MH indicating the white color of the run length 8) is used.
After sweeping out the code WB8), the next MH code (MH code BB6 indicating the black run length 6) is registered in the register 103.
However, since the run length of the previous MH code (WB ₈ ) still remains in the latch 513, the flip flop 510 remains set. Therefore, when the CRO signal of the counter 107 becomes 1, the gate 511
Becomes 0, and the SFTEN signal 605 eventually becomes 0, so that the counter 107 stops. Similarly, SFTEN signal 60
When 5 becomes 0, all of the S0 to S2 signals also become "0", the shift of the register 103 is stopped and the data is held. Therefore, the state of “cue completion” (BB6) continues until time t ₂ .

At time t ₂ , iNi signal 603 causes ▲ ▼ signal 610.
Becomes 0 and the run length (8 bits in this example) held in the latch 513 is transferred to the counter 108 by the signal 610 via the multiplexer 514. At the same time, flip-flop 510 is set by signal 610. This empties the latch 513, eliminating the busy. Accordingly, the output of the gate 511 becomes 1, the SFTEN signal 605 becomes 1 as described above, and the run length obtained by the MH code which is “cue completed” in the register 103 is latched to the latch 513. It

Similarly, the MH code is sequentially decoded.

Based on run length at time t ₂ is loaded into the counter 108 (-5 in this example), the VEN signal 602 generated from the next bit of the time t ₂ the counter 108 starts counting. And issue a CRI signal 611 (time t ₃ in this example) when the value of the counter 108 has decreased to (-1). Also, the flip-flop 109 is set for each color of the image designated by the B / signal 621 from the latch 513. As a result, the first MH code could be converted to the image VIDEO (white 8 bits in this example) for the time being.

After the rising edge of VEN signal 602, iNi signal 603
Remains at 0 until a new HSYNC 601 arrives. Therefore, after the rising of the VEN signal 602, for example, at time t ₃ , instead of the iNi signal 603, the flip-flop 510 is reset by the CRI signal 611 indicating the count-up of the counter 108, the busy state is released, and so on. The run length obtained by decoding the MH code can be taken into the latch 513.

By the way, in the above description, the code length of the MH code is equal to or shorter than the run length length, and the MH code is registered from the point of “completion of cueing”.
Multiplexed used MH code to be swept from 103
By serially shifting by setting the signals S ₀ = 1 and S ₁ = S ₂ = 0 given to 102, the MH code can be continuously decoded without interruption. However, on the other hand, M
When the run length of the H code is shorter than the code length, the serial shift is performed as described above, and while the code is being swept from the register 103 (during shift), the counter 108
At, the count of the run length of the MH code is completed. At this point, the next run length should be changed from the latch 513 to the counter 10 in order to eliminate the interruption of the image.
Need to go to 8. However, in register 103, the next M
Since it is not in the “cue completed” state for the H code, the run length to be incorporated in the latch 513 is ROM 105.
Will not be output more.

After all, in this case, the image recorded by the printer is interrupted, and the image cannot be output in real time. Such inconvenience occurs when the above-mentioned HSC code, that is, the MH code of run lengths 1, 2 and 3 indicating white and the MH code of run length 1 indicating black are decoded.

Therefore, in such a case, only the MH code, which is the above-mentioned four types of HSC codes, is MH code decode logic 10.
Code length data CL _{0 to} CL ₃ from ROM 105 using 4
Causes the circuit in the subsequent stage to operate in a manner equivalent to serially shifting the code to be decoded. That is, the counter 107
The logic 104 is ▲ so that (-1) can be loaded into
▼ The load value (-1) is created by the signal and the gate 504
To the counter 107 via. Also at this time ROM
Outputs CL0 to CL3 from 105 are inhibited at the gate 503 by the signal. The jump amount corresponding to the code length of the decoded MH code is output to the outputs SF1 and SF2 from the logic 104 as ▲ ▼ to ▲ ▼, and the multiplexer 102 is operated via S _{0 to} S ₂ . As a result, a shift of a plurality of bits can be performed in one bit time, in other words, the "cue completion" in the register 103 of the next code to be decoded can be performed in one bit time. The jump amount is also input to the accumulator 106 and is cumulatively added to the number of empty bits in the register 103.

By the above two shift methods, a series of operations from "cue completion" to "run length latch" and "run length count" are repeated at high speed to execute decoding without interruption of the image supplied to the printer unit. An EOL detection circuit 112 outputs a signal 0EOL when detecting that an EOL code appears at the outputs C _{0 to} C ₁₁ of the register 103. When the EOL code indicating the end of one line is detected by the EOL detection circuit 112, the EOL detection circuit 523 passes through the timing adjustment circuit 523.
Signal 0 EOL from 112 causes flip-flop 509
Is set and the signal 613 becomes 0. As a result, the SFTEN signal 605 eventually becomes 0, the register 103 is stopped until the next HSYNC comes, and the MH code waits for HSYNC in the "cue completed" state. In this way, good synchronization between the printer and the decoding operation can be obtained.

As described above, an image is formed by repeating the scanning for each line.

Next, the decoding error detection method will be described with reference to FIG. The circuit shown in FIG. 7 is connected to the appropriate position shown in FIG. 1 or 5. In FIG. 7, reference numeral 801 is an inverter. 802 is an adder, 803 is a latch, 804 is a comparator, 805 is a latch, and 806 and 807 are flip-flops.

FIG. 820 is the same signal as the signal 820 output from the latch 513 through the multiplexer 514 in FIG. 5, and as described above, the run length of the result of decoding the MH code is represented by 2's complement. It is a thing.

Now, the adder 802 and the latch 803 form an accumulator. The carry from the lower LSB of the adder 802 is 829.
It is set to 1 by the signal (1), and eventually the adder 802
The output 821 of is the two's complement of the run length 820. Therefore, the output 821 is a binary representation of the run length positive integer. Also, addition to the latch 803 is shown in Fig. 6 ▲
The addition is continued at the timing of 610, that is, the timing of loading the run length to be counted into the counter 108 shown in FIG. The latch 803 is cleared for each HSYNC 601 signal 601 in FIG. 6 output for each main scanning line. That is, the output 822 of the latch 803 represents the cumulative run length of each line by a binary number. Meanwhile, latch 80
Reference numeral 5 denotes a fixed run length of each line (in this example, 4096 corresponding to the number of pixels on one line), which is notified from a CPU or the like by a signal 824 and holds it.

Comparator 804 is the correct answer value 82 from the run length 822 (A) accumulated in the latch 803 and the latch 805.
3 is a comparator circuit for comparing with 3 (denoted as B).

The flip-flop 806 outputs the AND gate 808 when the EOS signal 604 shown in FIG. 6 is output, that is, when the signal 831 indicating A = B is not output from the comparator 804 at the final bit of each line. Set by 825. That is, the fact that the flip-flop 806 is set indicates that the run-length cumulative value A has become equal to the expected correct value B (4096 in this example), and that the MH code or its decoding has an error. Indicates.

When the flip-flop 807 is in the state of A> B, the flip-flop 807 is immediately set by the output 826 of the AND gate 809 which receives the signal 832 output from the comparator 804 even during the accumulation of run lengths. That is, the flip-flop Q output 828 is a correct value (4096 in this example, that is, VEN 602 in this example) in which the cumulative value of run lengths is scheduled in the middle of the line.
It means that the number of pixels in the section of 1) has been exceeded.
This indicates that a large decoding error has already occurred during the decoding of the line.

Also, the flip-flops 806 and 807 are shown in FIG.
▼ 613 is “0”, that is, EL (Eud of liue) is detected by the EOL detection circuit 112 and is not reset until HSYNC 610 is input, and the gate is input by the input of HSYNC signal 601.
Reset by 810 output. Therefore, the output 827 or the output 828 of each flip-flop 806, 807 is detected, and the separate EOL detection circuit 112 concentrates on the EOL detection, whereby the synchronization shift due to a decoding error or the like can be minimized.

In this example, the run length is cumulatively added by the accumulator, but this can be replaced with a method of sequentially subtracting the run length value from a predetermined number, for example, 4096, and detecting a borrow from the subtraction counter.

As described above, a decoding error occurs and the flip / flop
When 806 or 807 is set, its output is the buffer switch control circuit 303 of the printer circuit shown in FIG.
Be transmitted to.

As described above, the buffer switch control circuit 303 performs a buffer selection operation for alternately selecting the input / output of the line buffer of the printer having the double buffer structure. And the flip-flop 806 or 807.
More than that set signal, that is, when the decoding error detection signal is input, the image signal of the current line in which the decoding error occurred is invalidated, and the image signal of the previous line is reused instead of the line where the error occurred, To reread the line buffer where the image signal of the previous line is stored,
Performs line buffer selection control. That is, for example, the first
If a decoding error occurs while the image signal being decoded is stored in the line buffer 301, the first image signal currently stored in the line buffer 301 is invalidated, and the image signal is currently being read out. Line buffer 302
After the end of the reading, the same image signal is read again from the second line buffer 302.

As a result, it is possible to eliminate the influence on the recorded image without performing the printing operation by the image signal in which the decoding error has occurred. It should be noted that the number of line buffers of the printer may be two or more in the same manner. A line buffer for correcting this error may be provided on the decoding circuit side.

As described above, in the present example, when decoding the MH coded image, the leading EL of the MH code is detected, and the decoding is started from the code following it as the first line of the image, Play the actual image. This is because the MH-coded image is stored in, for example, an image memory or the like, which is not shown in the present case but exists in the preceding stage of the storage circuit 101 shown in the first diagram. From there C
The reading start address of the image memory is designated by the PU or the like, the MH-coded image is read out, and is given to the decoder circuit via the memory circuit 101.

At this time, the MH code read from the image memory does not always have the EL code at the beginning when the MH code is read from the middle of the image page. In this case as well, the first illustrated memory circuit 101 is set to the clear state before the decoding is started so that the decoding can be started correctly, and then the memory circuit 101 is full of the MH code read from the memory (the condition of FIG. 2). Read, and then starts sending data (MH code) inside the decoder. And the first E
It is not treated as an image code until the L code can be detected.
It keeps sending data one after another and concentrates on detecting the EL code.

After the EL code can be detected, the subsequent codes are treated as image information and decoded while controlling the shift amount by the code length or the like. In this way, the first EL code is changed to the above-mentioned EO.
By detecting it by the L detection circuit 112, it is possible to determine the MH code delimiter and to reproduce the image synchronously.

Now, the first input after the above decoding operation is started
When the operation to find the EOL code of is started, the memory circuit 101
Data is sequentially sent from the memory to the register 103, but if all "0" s exist in the register 103 before the start, the MH code that actually came from the memory circuit 101 or a part of the MH code (on the way) Connect with EOL code (000
00000001) is erroneously detected. To avoid this, the initial state of the register 103 is all set to "1". That is, all of C _{0 to} C ₂₇ of the register 103 are set to “1”. This makes it possible to avoid the above-mentioned erroneous detection of EL.

A method of presetting all the registers 103 to "1" will be described. FIG. 12 shows an example of the structure of the register 103, that is, the register 103 has 28 flip-flops.
Composed of F / F. Therefore, all the flip-flops F / F's preset terminals are connected to the preset pulse from the CPU, etc.
Input 901 and set Q output of all flip-flops to 1. Here, as the flip-flop F / F, for example, SN74S74N manufactured by American TI Co. can be used.

As described above, the present embodiment has been described by taking the decoding of the MH code as an example.
It can also be applied to a code decoding device using another compression method. Further, the image signal after decoding can be used for various purposes such as displaying on a display such as a CRT or a file as a bit image as well as being recorded by a printer such as a laser beam printer. . Further, it goes without saying that the numerical values used in the present embodiment are not limited to those values, and may be appropriately selected depending on the application, environment and the like.

As described above, the decoding operation of the compressed code can be surely executed, and the decoding operation can be performed in real time even for the image processing that requires high speed processing. Further, it is possible to effectively decode and supply the compressed code to an output unit such as a printer that requires high-speed and high-quality image recording.

Further, it is possible to surely detect an abnormality related to the decoding operation or transmission of the compressed code, and to minimize the influence thereof.

Further, when the printing operation is performed based on the image signal obtained by decoding the compressed code, the synchronization between the printer and the decoding processing section can be satisfactorily obtained.

Further, it is possible to surely detect the line synchronization code which is the reference of the decoding operation, and to eliminate the inconvenience such as the synchronization deviation of the decoding operation.

Further, even if the compressed code is supplied to the decoding circuit from the middle of one page or one line, the line synchronization in the decoding operation can be surely performed to prevent the decoding error.

As described above, according to the present invention, the compressed code is read in parallel in a predetermined bit from the storage means in which a plurality of compressed codes of indefinite length are continuously stored, and the compressed code read in parallel is continuously stored in the storage means. By storing a plurality of compressed codes stored in the storage means, the compressed code to be decoded next is set at a predetermined position of the storage means, and the compressed code set at the predetermined position is decoded. In the configuration that outputs the long data and the code length data of the compressed code, if the decoded compressed code is not a specific compressed code whose run length is shorter than the code length, shift the code length data sequentially. , If it is a specific compressed code, the shift according to the code length data can be executed at a time, so the run length is better than the code length. Even if a specific compressed code is decoded, the compressed code to be decoded next can be immediately set in a predetermined position of the storage means, so that the compressed code following the specific compressed code can be quickly decoded. In addition, by cumulatively adding the code length data of the decoded compressed code and controlling the storage position in the storage means of the predetermined bit parallel compressed code which is newly stored in accordance with the added value, the new data is stored in the storage means. The predetermined bit-parallel compressed code read out in step S1 is connected to the previously stored compressed code and additionally stored in the storage means. Therefore, in the structure for decoding the compressed code including the specific compressed code at high speed, the decoding means is undefined. It is possible to supply a long compressed code without interruption, and therefore a plurality of compressed codes can be decoded at high speed by the decoding means. It is possible to output the decoded image data without interruption to a subsequent device.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a schematic configuration of an embodiment of the present invention, FIG. 2 (a) is a diagram showing a memory type of an MH code in a memory circuit 101, and FIG. 2 (b) is a plurality of MH codes. 3 shows a continuous state of FIG. 3, FIG. 3 is a circuit block diagram showing the configuration of a bit shifter, FIG. 4 is a circuit block diagram showing the configuration of an MH code decoding circuit, and FIG. 5 is a circuit block diagram shown in FIG. FIG. 6 is a detailed circuit diagram of the figure, FIG. 6 is a timing chart showing operation timings of respective parts of the circuit shown in FIG. 5, and FIG.
FIG. 8 is a circuit block diagram showing the configuration of the decoding error detection circuit, FIG. 8 is a diagram showing an example of the configuration of the printer, and FIG. 9 is a block diagram showing the circuit configuration for the recording operation of the printer shown in FIG. 11 is a circuit block diagram showing the configuration of the EOL detection circuit, FIG. 11 is a circuit diagram showing the configuration of the detection gate shown in FIG. 10, FIG. 12 is a circuit diagram showing an example of the configuration of a register, and 101 is a memory circuit. , 102 is a multiplexer, 103
Is a register, 104 is an MH code decoding logic,
104 is an MH code table ROM.

Claims (1)

[Claims] 1. A compression code decoding device for sequentially decoding compression codes of indefinite length, wherein storage means stores a plurality of compression codes of indefinite length in succession, and compression codes are read from the storage means in parallel for a predetermined number of bits. Read-out means, storage means for storing a plurality of compressed codes read in parallel from the storage means, the storage means having a storage capacity for the number of bits larger than the predetermined bit, and the storage means. Shift means for setting a compressed code to be decoded next at a predetermined position of the storage means by shifting a plurality of compressed codes; and run length data by decoding the compressed code set at the predetermined position of the storage means. And decoding means for outputting the code length data of the compressed code, and the compressed code decoded by the decoding means has a run length shorter than the code length. If the compression code is not a fixed compression code, the shift means sequentially executes shifts according to the code length data, and if the compression code is the specific compression code, the shift means performs shifts according to the code length data at a time. In the storage means for executing the shift control means, the addition means for cumulatively adding the code length data output from the decoding means, and the predetermined bit parallel compressed code newly stored according to the addition value of the addition means. Storage control means for connecting the compression code newly read from the storage means to the compression code previously stored by controlling the storage position and additionally storing the compression code in the storage means. Characterized compressed code decoding device.