JPH0648437B2 - Image memory access device and color image display device using the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method of reading and writing a multi-layered image memory at high speed, and in particular, an arithmetic unit is provided in each layer of the image memory to display graphics and images. The present invention relates to an image memory access device having a multilayer structure suitable for high-speed processing.

[Prior art]

A conventional color image display control device will be described with reference to FIGS. 1 and 2.

FIG. 1 shows an image memory 407, 408, 409 made up of N layers having color information of 1 pixel N bit in units of image memory of each layer, and a control device 401 such as a micro-processor.
FIG. 3 is a block diagram showing a method of access by a user. The control device 401 designates one word of the image memory by the address signal 402 of the image memory. A part of the address signal 402 is input to the data switch 406 and the memory control switch 405, and the memory control signal 403 from the control device 401 and the data line 404 are one of the N layer image memories 407, 408, 409. Connected to. The one-word data designated in this way is read and written according to the memory control signal 403 of the control device 401. Image memory 40
The data of 7, 408, and 409 are constantly read by the display controller 410 and displayed on the display device 4 such as a CRT.
11 is displayed.

FIG. 2 shows a block diagram of the control circuit of the image memory for accessing the image memory in image units.

N-bit data line 404 from controller 401
Is connected to each layer 412, 413, 414 of the image memory by one bit. The address signal 402 designates one bit of each layer 412, 413, 414 of the image memory, and the N bit signal, that is, the data of one pixel is written by the memory control signal 403.
Alternatively, reading is performed.

[Problems to be Solved by the Invention]

In the above conventional technique, in the former memory access method, the number of layers of the image memory for writing one pixel,
That is, the memory access must be performed N times, and the processing time increases as the number of layers of the image memory increases. However, in the case of this system, if the number of bits forming one word is W, horizontally arranged W pixels can still be accessed by N times of memory access.

On the other hand, the latter memory access method is effective in the case of drawing a straight line, but is not suitable for raster-based processing such as filling. This is because, when the image memories 412, 413, 414 are read by the normal display controller 410, a plurality of pixels are read and displayed on the display device 411. Therefore, since one plane of the pixel memory does not actually have one bit but a plurality of bits and only one bit is used when accessing the image memory, memory access in the raster direction is performed. When doing, there is a problem that the same memory address is accessed multiple times, which is inefficient.

An object of the present invention is to provide a color image capable of speeding up processing by writing in parallel to each layer of an image memory and simultaneously writing a plurality of pixels when writing image data such as painting with a single color. It is to provide a display device.

[Means for Solving the Problems]

According to the present invention, an arithmetic unit is provided in each layer of the image memory, the pixel information to be written in the image memory sent from the control unit is taken in each arithmetic unit, and the pixel information of one pixel is composed of a plurality of pixels. Expansion means for expanding the image data of 1 word, and the expanded image data of 1 word,
The image data stored in advance at the writing destination of the 1-word image data is input, and the arithmetic means for executing the logical operation and the 1-word image data composed of a plurality of pixels obtained by the arithmetic means It is characterized in that selection means is provided for selecting and outputting at least two pixels or more among the calculation results.

[Action]

The pixel information of one pixel to be written to the image memory, which is input from the control unit by the expansion unit provided in each arithmetic unit, is expanded to one word of image data composed of a plurality of pixels. The expanded 1-word image data is logically operated by the arithmetic means with the image data stored in advance in the writing destination of the expanded 1-word image data. At least two or more pixels are selected by the selecting means from the operation result of one word composed of a plurality of logically operated pixels, and a plurality of pieces of pixel information which are the selected operation results are simultaneously written in the image memory. As a result, it becomes possible to write image data at a high speed such that the image data is filled with a single color.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5.

FIG. 3 shows that the read / write data width is 8 pixels and is 10
An image memory 1 for storing a binary image of 24 pixels × 1024 pixels and a parallel / serial converter 8 for converting the contents of the image memory 1 into a video signal 151 are provided. The configuration is shown. Control signal bus 4
Reference numeral 1 includes a read / write signal, and the read / write signal is connected to a read / write terminal of a memory element forming the image memory 1.

FIG. 4 shows an example of the configuration of a color image display device for realizing the image memory access device of the present invention.
Image memories 102, ..., 10N having the same configuration as the image memory 101 shown in FIG.
, ..., 11N are connected by local data buses 121, 122 ,. Control device 5 and arithmetic devices 111, 112, ..., 11N
In between, the 8-bit data bus 2 and the control signal bus 41
It is tied with. The data bus 2 is the first bit, and the data input / output signal 21 is the first arithmetic unit 111.
The second bit is connected to the second arithmetic unit, and the eighth bit is sequentially connected to the eighth arithmetic unit. When N is 9 or more, the Nth bit data is connected to the (Nmod8) th bit arithmetic unit.

FIG. 5 is a diagram showing the configuration of the first arithmetic unit 111 in FIG. 4, and shows the second to Nth arithmetic units 112,
..., 11N have the same configuration. Arithmetic unit 111
Is a first register 202 for latching 8-bit data on the local data bus 121 and a first register 2
A second register 203 for latching the contents of 02, a barrel shifter 204 for shifting these 16-bit data from 0 to 15 bits and outputting the lower 8 bits, an output of this barrel shifter 204 and data on the local data bus 121. An arithmetic unit 205 for performing a logical operation with the third register 208 to be latched, a mask selector 206 for selecting the result of the logical operation, and the contents of the third register 208 in bit units, and an output of the mask selector 206. It comprises a fourth register 207 connected to the local data bus 121, and a fifth bidirectional register 201 for interfacing the local data bus 121 and the data bus 2. Fifth bidirectional register 201
Is a function for latching the 1-bit data input / output signal 21 and 8 bits by the 1-bit data "0", "1".
The data width is expanded to either "00000000" or "11111111", and the control for sending to the local data bus 121 and the one bit out of the 8 bit data on the local data bus 121 are latched. It is composed of a function and a function of controlling the transmission of the 1-bit data to the data input / output signal 21, which includes two D-type flip-flops, one 8-to-1 selector and nine 3-state buffers. Can be easily configured.

By the way, the control signal bus 41 expands the read / write signal 1 bit of the image memory 1 and the signal 1 bit for fetching 1 bit data of the data input / output signal 21 into the fifth bidirectional register 201 and the fetched data. Both the signal 1 bit for controlling transmission to the local data bus 121, the 3 bit data for deciding which one of the 8 bit data of the local data bus 121 to select, and the selected 1 bit data for the fifth bit A control signal 2 of 7 bits in total for the fifth bidirectional register 201 consisting of a signal 1 bit fetched in the directional register 201 and a signal 1 bit for controlling transmission of the fetched 1 bit data to the data input / output signal 21.
13, the latch signal 210 of the first register, the latch signal 211 of the second register, the 4-bit control signal 212 for controlling the shift number of the barrel shifter 204, and the function of the arithmetic unit 205 (TTL IC74LS181).
(Depending on the logical operation mode), an 8-bit control signal 215 for controlling selection of each bit of each input of the mask selector 206, a latch signal 217 of the third register 208, It consists of a latch signal 1 bit of the four registers 207 and a control signal 216 of the fourth register 207 of a total of 2 bits consisting of a signal 1 bit for sending out the fetched data to the local data bus 121. Of these control signal buses 41, a signal for controlling the sending of the data of the fifth bidirectional register 201 in the control signal 213 to the local data bus 121 and the local data bus 121.
3 bit data for deciding which one of 8 bit data is selected, a signal for fetching the signal into the fifth bidirectional register 201, and a latch signal 210,
211, 217 and control signals 212, 214, 21
5, 216 are the respective arithmetic units 111, 112, ..., 11N
Are all connected in common. In addition, the control signal bus 41
Of the data input / output signal 21 in the control signal 213
To the fifth bidirectional register 201 and a signal for controlling transmission of the contents of the fifth bidirectional register 201 to the data input / output signal 21 when the image memory number N is 8 or less. Similarly to the control line of FIG.
2, ..., 11N are commonly connected. If N exceeds 8, then every eight, these two signals are (N-1) / 8 + 1.
It is divided into the largest integers that do not exceed. That is,
When the control unit 5 accesses the fifth bidirectional register of the arithmetic units 111, 112, ... 11N, the data bus 2
However, since it is 8 bits, these control signals are divided so as to access the unit of eight fifth bidirectional registers. Hereinafter, for convenience, N will be described as 8 or less.

Now, in FIG. 4, screen memories 101, 102, ..., 10N
, 15N are read out from the video signal 151, and the color conversion circuit 13 causes the color video signal 14 to be read.
The operation of converting into the color CRT and displaying the color image on the color CRT 6 is performed as follows.

First, the serial data 151, 15 from the image memory
2, ..., 15N display an image 71 from the CRT controller 7 (for details, refer to the section of HD46505 in the Hitachi Micro Computer System Device Data Book) via the selector 9 and the image signal by the address signal 91 of the image memory. It is obtained by converting the read image data of each image memory, which is given to the memory, into serial data by the parallel-serial converter 8. The obtained N-bit data is a color code for one pixel, is input to the color conversion circuit 13, and is converted into an RGB video signal 14. This video signal 14 and CRT
The periodic signal 72 output from the controller 7 is a color CRT.
6 and the color image is displayed on the CRT.

In the following, the control device 5 uses the arithmetic devices 111, 112, ..., 1
Screen memory 101, 102, ..., 10N via 1N
A method of accessing the image memory 1 in the inside will be described.

First, in order to bring information for one pixel consisting of N bits with an image memory to the data bus 2, the control device 5 sets the address bus 3 to the address of the image memory including the pixel to be read. It is sent out and the address selection signal 42 is set on the address bus 3 side. Next, the 3 bit signal for selecting 1 bit from the 8 bit data of the control signal 213 is set to the number of the read 8 pixels of the image to be read, and the local signal of the control signal 213 is set. A latch signal for taking in the data from the data bus 121 is given. At the same time, the data input / output signal 2 of the control signal 213
In response to the transmission control signal to 1, the fifth bidirectional register 20
The target pixel information fetched in 1 is sent to the data bus 2.

Next, in order to write the N-bit pixel information to a certain point on the image memory, the control device 5 first sends the pixel information to be written on the data bus 2, and the control signal 213 causes the fifth information to be written. It is taken into the bidirectional register 201. The fetched 1-bit data is expanded into 8-bit data, sent to the local data bus 121 by the control signal 213, and fetched in the first register 202 by the control signal 210. And the control signal 2 of 4 bits of barrel shifter
12 is set as the shift number 0 so that one input of the arithmetic unit 205 has the same data as the first register 202. On the other hand, the control circuit 5 gives the address of the image memory 1 including the target writing point to the address bus 3, sets the address selection signal 42 on the address bus 3 side, and the data of the image memory is sent to the local data bus 121. At that time, the data is sent to the third register 208 as a latch signal 217.
Take in by. At this time, the fifth bidirectional register 201
Control unit 5 controls the address selection signal 4 so that the output to the local data bus and the output of the image memory do not conflict with each other.
2. Control the control signal 213. Further, the control device 5 is
The control signal 214 gives what kind of logic is used to calculate the pixel information to be written and the pixel information of the point currently to be written in the image memory, and the point to be written corresponds to the address of the image memory including that point. The number of the 8th pixel to be used is given to the control signal 215 of the mask selector 206 by the information of 8 bits. For example, if there is a second pixel to be written from the left, the control signal 215 is a signal of binary number "01000000". Now mask selector 2
After the output of 06 is confirmed, the output of the mask selector 206 is fetched into the fourth register 207 by the control signal 216, and the data fetched onto the local data bus 121 is sent out. The control device 5 writes the read / write signal of the control signal bus 41 to write the logical operation result of the given pixel information and the pixel information obtained before the writing to the point to be written. By appropriately changing the control signal 215 in this process, the same image information can be written in up to 8 pixels.

Next, 8 arbitrary pixels arranged in the horizontal direction on the image memory are designated for one address of the image memory.
A method of performing a logical operation for each pixel and transferring the pixel will be described. First, the 8 pixels to be transferred are designated by two addresses over two words. 1 on the left side of the screen
An address with a word is called a source address. On the other hand, the address of the 8 pixels to which the data is transferred is called a destination address.

The controller 5 first sends the source address to the address bus 3 and sends the address selection signal 42 to the address bus 3.
Set to the side. When the image memory data corresponding to the source address is sent to the local data bus 121,
The image data is loaded into the first register 210 by the latch signal 210. At the same time, the control device 5 sends the address obtained by adding 1 to the source address (on the right side of the screen) to the address bus 3.

When the data of the image memory at the address obtained by adding 1 to the source address is transmitted to the local data bus 121, the contents of the first register 202 are latched to the second register 203 by the latch signal 211 and the latch signal 210. At the same time, the data on the local data bus 121 is loaded into the first register 202. Next, the control device 5 controls the control signal 212 so that the leftmost pixel of the eight pixels transferred is
A 4-bit signal is given as a binary number indicating the position from the left of the 8 pixels of the source address. Also,
The control signal 214 sets what kind of logical operation is performed. Next, the control device 5 gives the destination bus address to the address bus 3 and, when the data of the image memory is sent to the local data bus 121, fetches it into the third register 208 by the control signal 217. The control signals 215 are all set to "1", and the output of the arithmetic unit 205 is set to be the output of the mask selector 206.
After the output of the barrel shifter 204 and the logical operation result of the third register 208 are confirmed as the input of the fourth register 207, the fourth register 207 is controlled by the control signal 216.
At the same time that the output of the mask selector 206 is taken into
It is sent to the local data bus 121. Then, by setting the read / write signal of the control signal bus 41 to write, image data of any continuous 8 pixels of 16 continuous pixels of the source address on the image memory and the address obtained by adding 1 to the source address. The result of performing a logical operation with the image data of 8 pixels existing in the day stay address before being transferred is written in the day stay address. By this processing, the mask selector 206
By supplying the mask information to the control signal 215 of 1, the image transferred through the mask can be transferred.

As described above, according to the present embodiment, each image memory is provided with an arithmetic unit, and all of them access the single image memory 1 in parallel. Therefore, compared with the conventional method shown in FIG. The processing can be performed several times faster, which is eight times faster than the method shown in FIG. In addition, the first and second registers that hold pixel information of the transfer source in the arithmetic unit, the barrel shifter that shifts them by an arbitrary number of bits, the third register that holds the pixel information of the transfer destination, and the output of the barrel shifter And a mask selector capable of performing a logical operation with the third register, the output of the calculator, the third register in bit units, and a fourth register holding the pixel information to be transferred. This significantly speeds up the transfer of images in the image memory.

〔The invention's effect〕

According to the present invention, it is possible to simultaneously write one-word image data composed of a plurality of pixels in the horizontal direction in parallel in each layer of the image memory. In particular, high-speed writing of image data for filling with a single color is possible. Can be done.

[Brief description of drawings]

FIG. 1 is a block diagram of a display control device for accessing the image memory on a word-by-layer basis, FIG. 2 is a block diagram of a display control device for accessing the image memory on a pixel-by-pixel basis, and FIG. FIG. 4 is a block diagram of a color image display controller of the embodiment, FIG. 4 is a block diagram of a color image display controller of one embodiment of the present invention, and FIG. 5 is a block diagram of an arithmetic unit. is there. 1 ... Image memory, 2 ... Data bus, 3 ... Address bus, 41 ... Control signal bus, 42 ... Address selection signal, 5 ... Control device, 6 ... Color CRT, 7 ... CR
T control circuit, 71 ... Display address, 72 ... Sync signal, 8 ... Parallel / serial converter, 9 ... Selector, 101,
102, ..., 10N ... 1st to Nth screen memory, 111, 112, ..., 11N ... 1st to Nth arithmetic unit, 13 ... Color conversion circuit, 204 ... Barrel shifter, 205 ... … Calculator, 206 …… Selector, 2
07,208,210,211 ... Register, 401 ...
... Memory control device, 402 ... Address signal, 403 ...
... memory control signal, 404 ... data line,
407, 408, 409, 412, 413, 414 ... Image memory, 410 ... Display controller, 41
1 ... CRT.

Claims (2)

[Claims] 1. A multi-layered image memory for storing color image data, a display unit, and a display control unit for sequentially reading out the image memory in a raster direction and sending the image memory to the display unit.
A control unit that generates an address of the image memory and controls reading and writing of the image memory, in which the pixel information to be written to the image memory sent from the control unit is fetched and the pixel information of the one pixel is acquired. To expand to 1-word image data composed of a plurality of pixels, 1-word image data expanded by the expanding means, and image data stored in advance in the writing destination of the 1-word image data. And an input unit for executing a logical operation, and an operation unit having an operation unit for selecting and outputting at least two pixels or more out of the operation result of the image data of one word by the operation unit. A color image display device characterized by being provided for each layer. 2. An image memory access device for controlling the reading and writing of image data to and from the image memory based on read and write commands from the respective control units to the image memory, wherein the image memory is sent from the control unit. Expansion means for taking in the pixel information to be written to, and expanding the pixel information of the one pixel into image data of one word composed of a plurality of pixels, image data of one word expanded by the expansion means, and the one word The image data stored in advance in the destination of writing the image data is input, and at least two pixels or more are selected from the operation means for executing the logical operation and the operation result of the one-word image data by the operation means. An image memory access device, characterized in that selection means for outputting is provided.