JPH065007A - Data regenerating apparatus - Google Patents

Abstract

(57) [Summary] [Purpose] The time constant of mono-multi is set longer than the longest inversion cycle of the encoded read data, and it is detected that signal inversion does not occur in the encoded read data for a period longer than the period determined by this time constant. In this case, by stopping the phase comparison operation of the PLL circuit, it is possible to detect the signal loss promptly regardless of the magnitude of the signal loss, so that the PLL can be prevented from being unnecessarily shaken, and good circuit operation can be achieved. To be able to get. In a disc reproducing apparatus for reproducing data from a disc 1 on which data modulated by the 8-10 modulation method is recorded, a PLL circuit 9 to which the data reproduced from the disc 1 is supplied, a capacitor 22 and a resistor. The mono-multi 21 whose time constant is set to 23 longer than the longest inversion cycle of the encoded read data, and the PLL circuit when it is detected that the signal inversion does not occur in the encoded read data for a period longer than the period determined by this time constant. 9 and a NAND circuit 24 for stopping the phase comparison operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing apparatus suitable for application to a disk reproducing apparatus for reproducing an optical disk such as a write-once.

[0002]

2. Description of the Related Art Conventionally, in a disc reproducing apparatus for reproducing an optical disc such as a write-once, a recording signal recorded on the optical disc is read by an optical head,
After amplifying the read signal, synchronization detection, PLL
Phase comparison and data extraction are performed, and the processed signals are subjected to binary / digital conversion, serial / parallel conversion, 10-8 conversion, etc., and ECC (error correction). ·code)
The processor performs error correction processing, and after performing this error correction processing, predetermined signal processing is performed and output.

There are various types of optical discs on which information can be written. For example, an optical disc (WORM) called a write-once is 5 inches (130 m).
m) WORM (ISO / IEC 9171), and a magneto-optical disk (MO) is 3.5 inches (90 mm) MO (ECMA-154).

When data is lost due to scratches or dirt on the disc, a read operation is continued until a PLL is locked again by a code called a resync code, or a drop in the RF level of a reproduction signal is detected. However, when this is detected, it is regarded as data loss and the operation is performed.

[0005]

By the way, when the read operation is continued until the PLL is locked again by the resync code, the data loss is not detected or corrected, so that the data loss is large. Had the inconvenience that the PLL could not be relocked with the resync code.

Further, when a drop in the RF level of the reproduced signal is detected, and when this is detected and it is assumed that the operation is to be performed assuming that there is data loss, when it is considered that there is data loss, the PLL synchronization has already largely shifted. Then, there was an inconvenience that it could not operate normally.

The present invention has been made to solve such a problem, and can detect a signal loss promptly regardless of the magnitude of the signal loss, thereby preventing the PLL from unnecessarily swinging. An object of the present invention is to propose a data reproducing device which can obtain a good circuit operation.

[0008]

The data reproducing apparatus of the present invention is, for example, as shown in FIGS. 1 to 3, a data reproducing apparatus for reproducing data from a recording medium 1 on which a data signal modulated according to a predetermined modulation method is recorded. In, the PLL circuit 9 to which the data signal reproduced from the recording medium 1 is supplied, and the period slightly longer than the maximum period of the data signal modulated by the predetermined modulation method from the arrival of the pulse in the reproduced data signal are measured. When the next pulse does not arrive within the measurement period by the measuring means 21, 22, 23, and the measuring means 21, 22, 23, it is determined that the reproduced data is defective and the PLL circuit 9 compares the phases. It has control means 24, 25 for controlling so as to stop the operation.

[0009]

According to the above-described structure of the present invention, the measuring means 21, 22, 23 use the measuring means 21, 22, 23 for a period slightly longer than the maximum period of the data signal modulated by the predetermined modulation method from the arrival of the pulse in the reproduced data signal. This measurement means 21,
When the next pulse does not arrive within the measurement period of 22 and 23, the control means 24 and 25 determine that the reproduced data is defective and control the PLL circuit 9 to stop the phase comparison operation. .

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the data reproducing apparatus of the present invention will be described in detail below with reference to FIGS.

First, a case where the data reproducing apparatus of the present invention is applied to a disk reproducing apparatus will be described with reference to FIG.

In FIG. 2, reference numeral 1 denotes a disk, which is, for example, a write-once (W) of 5 inches (130 mm).
ORM: ISO / IEC 9171), 12 inches (3
00mm) write-once, 3.5 inch (90mm)
Optical disk (MO: ECMA-154) or an optical disk such as CDR.

Data recording will be described below.
At the time of recording data, for example, 8-bit data is subjected to 8-10 conversion (8 bits to 10 bits), converted into serial digital data, and then RZ (Return).
to Zero) recording or NRZ (Non Ret)
urn to Zero) Recording. That is, the data is recorded on the disc by emitting light in the RZ or NRZ method corresponding to the data "1" and "0".

As the conversion (modulation), in addition to the 8-10 conversion, conversion from 8 bits to 16 bits is performed (2, 7).
Conversion (there is a condition that 2 or more and 7 or less 0s always exist between 1 and 1), conversion from 8 bits to 12 bits (1, 7) conversion (always 0 between 1 and 1) Has the condition that 1 or more and 7 or less are included).

The format of the data recorded in this way will be described. The sector is composed of an address area and a data area, and the address area is called a VFO (Variable Frequency Oscillator). It is composed of an address mark indicating the beginning, address data, data and a gap.

The data area is VFO (Variable
It is composed of a sync called “frequency oscillator”, a data mark indicating the beginning of data, data, a data mark, data, ... Data mark, data, and buffer.

Disc 1 in this disc reproducing apparatus
When the disc 1 is mounted on the mounting portion of the disc reproducing device (not shown) and the operating portion (not shown) is operated,
The signal processing circuit 16 supplies a control signal to the drive unit 4, the drive unit 4 drives the spindle motor 3, and the disk 1 mounted on the shaft 2 is rotated.

Reference numeral 2 is an optical pickup, which is a signal processing circuit 1.
The reading surface of the disk 1 is moved by the driving operation of the driving unit 6 based on the control signal from the disk 6, and the recording signal of the disk 1 is read.

The read recording signal of the disk 1 is amplified by the amplifying circuit 7, encoded and converted into binary binary information, and supplied to the synchronizing signal detecting circuit 8 as encoded read data.

As will be described later, the sync signal detection circuit 8 is a circuit for detecting the sync of the encoded read data, and this circuit 8 outputs the read gate signal based on the preamble detected signal from the PLL circuit 9 in the next stage. Get
This read gate signal is supplied to the PLL circuit 9.

This PLL circuit 9 detects the read gate signal from the sync signal detection circuit 8 and obtains a preamble detected signal indicating that the sync has been detected when a predetermined number of syncs have continued after the gate was opened. The preamble detected signal is supplied to the sync signal detection circuit 8 as described above.

The PLL circuit 9 extracts the data of the encoded read data, and supplies the extracted data to the binary / digital conversion circuit 11.

The binary / digital conversion circuit 11 converts the binary data extracted by the PLL circuit 9 into serial digital data, and supplies this serial digital data to the serial / parallel conversion circuit 12.

The serial / parallel conversion circuit 12 converts the serial digital data from the binary / digital conversion circuit 11 into parallel digital data and supplies the parallel digital data to the 10-8 conversion circuit 13.

The 10-8 conversion circuit 13 is for returning to the original because it is 8-10 converted at the time of recording. The original data (original data and ECC (error correction code)) converted to 8 bits by 10-8 conversion is once written in the memory 14 and subjected to error correction processing and the like by the ECC processor.

The data which has been subjected to this error correction processing is supplied to a device using data such as a computer through an output terminal 17 after passing through a signal processing circuit 16.

FIG. 1 is a block diagram showing a main part of the above-mentioned disc reproducing apparatus. FIG. 1 shows an internal constitution of a sync signal detecting circuit 8 and a PLL circuit 9 of the disc reproducing apparatus shown in FIG. .

In FIG. 1, reference numeral 20 denotes an input terminal to which the encoded read data from the amplifier circuit 7 shown in FIG. 2 is supplied, and the encoded read data (FIG. 3A) from the amplifier circuit 7 is supplied via the input terminal 20. Is supplied to the input terminal of the monostable multivibrator 21.

This monostable multivibrator 2
Reference numeral 1 (hereinafter referred to as mono-multi) is retriggerable, and the time constant determined by the capacitor 22 and the resistor 23 is set as follows. As shown in FIG. 3, for example, 8-10
In the case of conversion, as is well known, when the minimum inversion interval in 8-10 conversion is T (see FIG. 3A), the longest inversion period is 4T, and the longest inversion period is 8T (shown as Tmax in FIG. 3A). Becomes Therefore, the capacitor 2
2 and the time constant determined by the resistor 23 are the longest inversion period 8
It is set longer than T (shown as Tset in FIG. 3A).

Therefore, the signal output from the output terminal Q of the mono-multi 21 becomes a high level "1" signal continuously (see FIG. 3B). This signal is supplied to the NAND circuit.

A read gate circuit 25 generates a gate signal from the encoded read data supplied through the input terminal 20. This read gate signal is supplied to the NAND circuit 24 and the read gate signal input terminal RG of the PLL circuit 9, respectively.

Therefore, in the NAND circuit 24, the output from the monomulti 21 and the read gate signal from the read gate circuit 25 are logically ANDed and inverted. This NAND output is supplied as a control signal to the control input terminal of the PLL circuit 9. The PLL circuit 9 stops the phase comparison operation when the control signal supplied to this control input terminal becomes active (for example, low level “0”), holds the state of the immediately preceding PLL, and outputs the read gate signal. When it becomes active (for example, high level “1”), the read operation is performed.

Next, the operation when ideal encoded read data cannot be obtained due to scratches or stains will be described.

In such a case, the time Ts shown in FIG.
The result is that signal inversion does not occur for longer than et. Then, in this case, the retrigger operation of the mono-multi 21 cannot be repeated while it is at the high level "1", and the output of the mono-multi 21 becomes the low level "0".

The output of the monomulti 21 is at the low level "0" and the read gate signal is at the high level "1".
The signal obtained by performing NAND operation on the above state is supplied to the PLL circuit 9 as a control signal.

The PLL circuit 9 stops the phase comparison operation while the control signal is active (for example, low level "0"), and holds the immediately preceding PLL state. When the reproduction signal changes from the signal missing portion to the normal portion, the output of the mono-multi 21 becomes low level "0", whereby the control signal output from the NAND circuit 24 becomes high level "1", which causes the PLL circuit 9 to operate. Performs phase comparison operation.

In the above example, the case where the NRZ recording is performed by the 8-10 conversion modulation system has been described, but not only this modulation system but also another modulation system, for example, (2,7) P.
It is also applicable to the LL system and the (1,7) PLL system.

(2, 7) In the case of NRZ recording by the PLL system, assuming that the minimum inversion interval is T, the maximum inversion interval is 8/3.
It becomes T. Also, the (1, 7) PLL system can be handled in exactly the same way, only the ratio is different.

As described above, in this example, the time constant of the monomulti 21 is set longer than the longest inversion period of the encoded read data, and the signal inversion occurs for a period longer than the period in which the encoded read data is determined by this time constant. Since the phase comparison operation of the PLL circuit 9 is stopped when it is detected that there is no signal, regardless of the magnitude of the signal loss,
A signal loss can be detected promptly, which makes unnecessary P
It is possible to prevent the LL from swinging and obtain a good circuit operation.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0041]

According to the present invention described above, the measuring means measures a period slightly longer than the maximum period of the data signal modulated by the predetermined modulation method from the arrival of the pulse in the reproduced data signal, and this measurement is performed. When the next pulse does not arrive within the measurement period by the means, the control means determines that the reproduced data is defective and controls the PLL circuit to stop the phase comparison operation. Regardless of the size of the dropout, the dropout of the signal can be promptly detected, whereby the PLL can be prevented from unnecessarily oscillating, and good circuit operation can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main part of an embodiment of a data reproducing apparatus of the present invention.

FIG. 2 is a block diagram showing an example of a disc reproducing apparatus to which the data reproducing apparatus of the present invention is applied.

FIG. 3 is a timing chart for explaining an embodiment of the data reproducing apparatus of the present invention.

[Explanation of symbols]

 9 PLL circuit 21 Monostable multivibrator 22 Capacitor 23 Resistor 24 NAND circuit 25 Read gate signal

Claims (3)

[Claims] 1. A data reproducing apparatus for reproducing data from a recording medium on which a data signal modulated according to a predetermined modulation method is recorded, wherein the data signal reproduced from the recording medium is supplied.
The LL circuit, a measuring means for measuring a period slightly longer than the maximum period of the data signal modulated in the above-mentioned predetermined modulation method from the arrival of the pulse in the reproduced data signal, and the following period within the measuring period by this measuring means: And a control means for controlling the PLL circuit to stop the phase comparison operation when the pulse does not arrive and determines that the reproduced data is defective. 2. A retrigger monostable oscillator having a time constant slightly longer than the maximum period to which the regenerated data signal is supplied, the PLL being the output signal from the retrigger monostable oscillator as a control signal. The data reproducing device according to claim 1, which is supplied to a circuit. 3. The data reproducing apparatus according to claim 1, wherein the modulation method is an 8-10 conversion method.