JPH065009A - Recording / playback error analysis device - Google Patents

Abstract

(57) [Abstract] [Purpose] An error analysis device for a recording / reproducing system that allows various recording signals to pass through a non-linear system path and to compare this recording signal with a reproduction signal corresponding to this recording signal and an error state. obtain. [Configuration] A system capable of loading data from the CPU 11 into the memory 10 and fetching data from the memory 10 to the CPU 11, and a recording signal on the memory 10 is transferred to the DAC 1
The signal is output to a non-linear system path such as a recording / reproducing system via 6 and is taken from this system path via the ADC 15 to store the reproduced signal in the memory 10 and the CPU 11 displays the recorded and reproduced signal in a corresponding manner on the display device. At the same time, the error position is displayed at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing system error analyzing apparatus useful for analyzing the error state of recording and reproducing signals of a digital recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art Conventionally, high frequencies such as digital magnetic recording
In order to perform high density recording, it was necessary to strictly analyze the nonlinearity of the magnetic recording system. In particular, when the reproduction signal is evaluated in the recording / reproduction system, for example, considering a digital VTR, the state of the reproduction signal is observed at the stage of error correction or the like. Hereinafter, this error correction method will be described.

In FIG. 13, a composite analog video signal of, for example, the NTSC system is supplied to the processor 2. The processor 2 converts the analog video signal into a digital video signal, which is recorded on the magnetic recording medium in the VTR unit 1, and the processor 2 converts the recorded digital video signal into an analog video signal for display on a CRT or the like. Display on the device 3.

In the processor 2, the analog signal is detected by the detection circuit 4 at the time of reproduction, binarized and supplied to the error correction circuit 5, and if there is an error in the encoded data, an error flag or the like is set. Then, a video signal or the like is displayed on the display device 3 via the digital-analog conversion circuit (DAC) 6.

By checking the error flag of the error correction circuit 5 as described above, it is possible to judge whether or not the data can be used in a wide range such as at which position on the track of the magnetic recording medium of the VTR section 1 the data signal has many errors. You can However, evaluation of the reproduction signal to determine how the recording waveform changes at the time of reproduction and what kind of error occurs during reproduction, for example, is performed by supplying this reproduction signal to the oscilloscope and Was observing the waveform of.

However, in such an observation on an oscilloscope, the transmission characteristic must be judged by observing the worst pattern in a specific pattern. Also, when recording and reproducing a pseudo-random sequence, you can see the size of the averaged data error by looking at the eye pattern.
In this case, it was not possible to know specifically what kind of recording waveform the error occurs in the reproduced waveform.

[0007]

As described above, in order to see the analysis result of each waveform, not to see the magnitude of the data error obtained by averaging the binarized or encoded data with a pseudo-random sequence or the like. For example, although a reproduced signal can be fetched into a computer (CPU) or the like using a digitizer or the like configured to digitize an analog signal through an analog-digital conversion circuit (ADC) and store it in a memory at high speed, The recording signal is generated using another signal generator,
Since it needs to be loaded into the CPU, the labor is complicated and it is difficult to generate various recording signals. Although the waveform itself can be analyzed, for example, to analyze the non-linearity generated in the magnetic recording / reproducing system, It was impossible to analyze what kind of error occurs in the reproduced signal when the data digitally recorded on the recording medium is reproduced through the magnetic recording / reproducing system.

The present invention has been made in order to solve the above problems, and its purpose is to generate a recording signal and a reproducing signal as well as a recording signal and a reproducing signal for a recording signal of various forms. An object of the present invention is to provide a recording / reproducing system error analysis device capable of clearly analyzing an error position.

[0009]

As shown in FIG. 1, an error analysis apparatus for a recording / reproducing system according to the present invention is used for analyzing the non-linearity of the recording / reproducing system. In the apparatus, recording / reproducing means capable of recording / reproducing signals of the recording / reproducing system, storage means 10 connected to the computer 13 via the bus 12, and data stored in the storage means 10 as recording data. A computer 11 capable of outputting to a recording / reproducing means and taking in a reproduction signal from the recording / reproducing means as reproduction data via a storage means 10; Possible display means 13
And is provided.

[0010]

According to the error analyzing apparatus of the recording / reproducing system of the present invention, since various kinds of recording signals and reproducing signals as well as error positions can be simultaneously displayed on the same screen of the display device, S / N deterioration and It is possible to separate and evaluate the causes of errors such as the magnitude of intersymbol interference.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an error analyzing device for a recording / reproducing system according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an overall system diagram of an error analysis device used in the present invention.

In FIG. 1, reference numeral 10 is a storage element such as a semiconductor, and 128 MB of 256K × 4 bit SRAM is used for 4 MB.
The memory of. This is a large-scale dual port memory as a whole, and can perform read / write via the bus 12 such as VEM interposed between the CPUs 11 and 16 parallel read / write via the back plane. It is made like.

The CPU 11 of course has a display device such as a CRT or LCD. Bus 11 is control register 1
The control signal output from the control register 14 is also connected to the memory 4 and the analog-digital conversion circuit (ADC) 15 and the digital
It is supplied to the analog conversion circuit (DAC) 16 to perform synchronous pattern control and 16 parallel read / write control of the memory 10.

The ADC 15 has, for example, VT at the input terminal T ₂ .
An analog signal is supplied as a reproduction signal through a magnetic medium such as R, converted into digital data, and further converted into 16 parallel data through a serial-parallel conversion circuit (SPC), and 8 × 16 = 128 Parallel data is provided to the memory 10 via the backplane bus 12. Therefore,
Eight channels of digital data can be simultaneously acquired and analyzed.

The DAC 16 receives 16 parallel digital data from the memory 10 and outputs the parallel-serial conversion circuit (PS).
After serial conversion in C), the DAC 16 converts the digital data into an analog signal and records it as a recording signal on the recording medium such as the VTR from the output terminal T _{3 in the} form of a test signal.

The clocks for the ADC 15 and the DAC 16 may be supplied from the terminal T ₁ as an external clock, or may be extracted from the reproduced signal through a PLL circuit, for example.

FIG. 2 shows a system diagram of an analyzing device connected to a more detailed recording / reproducing system having the above-mentioned structure. Portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 2, the bus 12 from the CPU 11
Is connected to the real mode controller 14A in the control register 14 and the memory 10 via the interface (I / F) 17 for the CPU 11, and the memory control signal 18 from the real mode controller 14A is supplied to the memory 10 as a control signal. Further, the real mode address controller 14B is supplied with the address control signal 19 from the real mode controller 14A, and the real mode address controller 14B is supplied with the real address 20 to the memory 10.

This real mode controller 14A,
Real mode address controller 14B, memory 10, SPC15B, PSC16A PL
A signal line of a clock 21 obtained by dividing the clock from the L circuit 25C by 1/16 is connected.

As described above, the ADC 15 outputs 16 bits of 8-bit serial data 24 as well as 8-bit ADC 15A.
It has SPC15B for converting to parallel data, and DAC16
Similarly, for example, an 8-bit DAC 16B as well as a PSC 16A for converting 16 parallel data 26 into serial data are provided. Each of these circuits 15A, 15B, 16A, 16B has a clock for ADC and DAC from an equalizer and PLL circuit 25C. 23 is supplied. SPC1
The 16 parallel data 26 from 5B is of course supplied to the memory 10. Reference numeral 22 is a clock obtained by dividing the clock from the PLL circuit 25C transmitted between the lines connected between the SPC 15B and the PSC 16A by 1/4.

A recording signal recorded on a magnetic medium 27 such as a VTR is converted into a reproducing signal (PB) via a reproducing head 28,
This reproduction signal is amplified through the preamplifier 25A of the equalizer and PLL circuit 25, and is connected to the fixed contact b of the switch SW ₁ for selecting the non-equalized state and the equalizer 25B.

The output equalized linearly by the equalizer 25B is connected to the PLL circuit 25C and the fixed contact c of the switch SW ₁ for selecting the equalized state, the movable contact a of the switch SW ₁ is connected to the reproduction amplifier 26, and the ADC 15 To the ADC15 and D from the PLL25C.
The clock 23 for the AC 16 is taken out.

From the PSC 16A of the DAC 16, for example,
8-channel digital data is output and 8-bit D
An analog recording signal is output from the AC 16B, and the recording head 31 passes through the recording amplifier 30 and the magnetic medium 27.
Is recorded as an analog signal.

The general operation of the above configuration will be described below.
In the present example of FIG. 2, the CPU 11 and the memory 10 are connected via the bus 12 and the I / F 17 to exchange binary signals. That is, the data on the CPU 11 can be loaded on the memory 10, and the data on the memory 10 can be loaded on the CPU 11, and the data on the memory 10 can be read by the DAC1.
It is possible to output as a recording signal via 6. Also, an external reproduction signal can be stored in the memory 10 via the ADC 15,
These operations are performed based on the control data in the control register 14, and the control data in the control register 14 can be rewritten from the CPU 11 side via the bus 12.

FIG. 3 shows an overall flow chart for analyzing an error waveform or the like which occurs in the recording / reproducing system with the above-mentioned configuration.

In FIG. 3, in the first step ST ₁ , the CPU 11 generates a recording signal to be a test signal to be analyzed. As this recording signal, as shown in FIG. 9A, a synchronizing signal (SYNC) 35 is put and placed, and a parity for error correction is added if necessary. The recording signal 36 is recorded as binary data of 0.1. However, when recording M series (pseudo random series) data, the sync signal 35 appears only once in one cycle "0". A continuous pattern of is selected.

The recording signal is subjected to recording encoding, recording equalization and the like in the CPU 11.

This processing is performed as shown in FIG. 4 when it is shown by a functional block. That is, the binarized recording signal is record-encoded by the record encoder 37. This encoding is, for example, 8-10 conversion or encoding such as M ² according to the characteristics of the recording / reproducing system (digital VTR, etc.) 39.

The recording signal thus recorded and encoded, for example, as shown in FIG. 5A, is normally recorded and equalized by a recording amplifier or the like, but in this example, the recording and equalization unit 38 performs the recording and equalization. To be done. That is, recording equalization such as the waveform shown in FIG. 5B or 5C is performed.

FIG. 5B shows the rising and falling portions 42 and 43 of the recording signal 36, and FIG. 5C shows the rising and falling changing positions of the recording signal 36 by arrows 44, 45 and 46. By slightly shifting the waveform as shown, an operation for performing waveform modification for better recording of the rectangular wave of the recording signal is performed. In the present example, since the encoding and recording equalization of these recording signals can all be performed within the software in the CPU 11, the examination of the recording encoding system, the recording equalization system, etc. is very efficient. I can do it.

In the next second step ST ₂ , the recording signal as described above generated on the CPU 11 is transferred to the memory 10 as an I / F.
Load via 17 etc.

The recording signal stored in the memory 10 is DA
C16 digitally - analog converted recorded recording signal of the analog to the recording amplifier 30 and a recording head 31 a magnetic medium 27 of the recording and reproducing system, for example, VTR via is made (third step ST _3).

In the next fourth step ST ₄ , the recording signal recorded on the magnetic recording medium 27 is reproduced by the reproducing head 28,
The reproduction signal is picked up and supplied to the equalizer and PLL circuit 25, and the reproduction signal is stored in the memory 10 via the ADC 15.

That is, in the fourth step ST _4, the reproduction signal picked up by the reproduction head 28 is amplified by the preamplifier 25A in the equalizer and PLL circuit 25 as shown in FIG. The PLL circuit 25C converts the ADC, DAC
The clock 23 for is extracted. Here, the clock extracted by the PLL circuit 25C is multiplied by 2 to 8 times in order to sufficiently cover the band to be equalized of the reproduction signal.

The equalized or non-equalized reproduction signal is supplied to the fixed contact b or c of the switch SW _{1 by} the equalizer and PLL circuit 25, and the movable contact a and the reproduction amplifier 26 as well as, for example, 8 bits. It is supplied to the ADC 15A. This reproduction signal is subjected to analog-digital conversion with an ADC and DAC clock synchronized with this reproduction signal, and then converted into a memory (SRA).
M) The serial 8-bit data 24 output from the 8-bit ADC 15A is serial-parallel converted by the SPC 15B in order to slow down the speed to read / write to 10 and the 16 parallel data 26 is written in the memory 10 as a reproduction signal. Be done.

The real mode control 14A and the real mode address controller 14B in the control register 14, as well as the memory 10 and the PSC 16A, are supplied with a 1 / 16-divided clock 21 from the SPC 15B, and further 1/4 from the SPC 15B. The divided clock 22 is supplied to the PSC 16A. Control data is written from the CPU 11 to the real mode controller 14A via the I / F 17 and the bus 12, and a memory control signal 18 is sent from the real mode controller 14A to the memory 10 and an address is sent to the real mode address controller 14B. A control signal is supplied, the real mode address controller 14B supplies the real address 20 to the memory 10, and the real address 20 is supplied to the memory 10.
6 parallel data read / write control is performed, and the reproduction signal is written in the memory 10. This write data is fetched by the CPU 11 via the bus 12 and the I / F 17 as in the fifth step ST ₅ .

The CPU 11 stored in the memory 10 in this way
As shown in the functional block of FIG. 4, the 16 parallel reproduction signals taken in are subjected to reproduction equalization in which waveform shaping is performed so that the reproduction equalization unit 40 and the detection unit 41 can easily detect them as binary data. To be done.

This reproduction equalization is usually performed by the L.P. C. It is performed by an analog filter such as R or a digital filter after being digitalized by an ADC, but in the case of equalization for integral detection of a magnetic recording system, a recording signal 36 is reproduced as shown in FIG. As shown in FIG. 6C, the reproduced signal is integrated and the reproduced signal is integrated to obtain an integrated waveform 48.
Equalization waveform 50 is obtained by performing pulse slimming as shown by D and performing equalization for reducing interference so that interference with adjacent bits does not occur (arrow 49).

After such equalization, the signal is detected by the detecting section in FIG. 4 and is converted into a binary signal of 1.0. For example, in the integral detection in the magnetic recording / reproducing system, the integral detection such as "1" is performed when the threshold value SH exceeds a predetermined threshold level SH as shown in FIG.

Of course, since the reproduction equalization and detection are performed by the software in the CPU 11 in this example, the reproduction equalization method can be studied efficiently and the hardware can be omitted.

After the end of the fifth step ST ₅ , the process proceeds to the sixth step ST ₆ to analyze the synchronization pattern detection, averaging, error detection, etc. by CP.
After the data is generated on U11, the data generated by the CPU 11 is written to the memory 10 via the I / F 17 and the bus 12.
The data written in the memory 10 is read in 16 parallels, converted into serial data by the PSC 16A, and further converted into analog data by the 8-bit DAC 16B, and displayed on the display device 13 (seventh step ST ₇ ).

The above-mentioned sixth and seventh steps ST ₆ and S
The flowchart of T ₇ is shown in FIG. 8 and the operation waveforms and the display waveforms are shown in FIGS. 9 to 12, which will be described in detail.

The analysis on the CPU 11 in the sixth step ST ₆ is performed as shown in FIG. That is, the first step STE
_{At 1} , the sync signal (SYNC) is detected. As shown in FIG. 9A, since the synchronizing signal 35 is added to the recording signal 36, reproduction is performed as shown in FIG. 9B.
By detecting the reproduction synchronization signal 35R in FIG.
Synchronize with 6.

Next, as shown in the second step STE ₂ , the detection signal 5 binarized by 0.1 detected from the reproduction signal 47.
If the 1 series and the binarized series of 0.1 of the recording signal 36 are compared in the CPU 11 and they do not match, an error 5
An error detection of 2 is made.

In the next third step STE ₃ , it is judged whether or not the reproduced signal is a periodic signal. Here, if the reproduced signal is a periodic signal, averaging is performed.

This average zinc will be described with reference to FIGS. 10A and 10B. This averaging is performed to average the periodic signals T, T, T ... Of the reproduced signal 47 to reduce random noise. That is, when a reproduced signal 47 digitized by the ADC 15 when a periodic signal such as an M sequence is recorded and reproduced is z (t), this is the original signal component x (t) and random noise n (t). ) Is considered to be the sum. That is, z (t) = x (t) + n (t) Consider that the original signal x (t) is obtained from the reproduced signal z (t). Assuming that x (t) is a signal of cycle T, x (t) = x (t + T) = x (t + 2T) = ... Then, the reproduction signal z (t) is added for each cycle T, and FIG.
When averaged like B, [z (t) + z (t + T) + z (t + 2T) + ... + z
(T + KT)] / K = [x (t) + x (t + T) + x
(T + 2T) + ... + x (t + KT)] / K + [n
(T) + n (t + T) + n (t + 2T) + ... + n (t
+ KT) / K = x (t) + N (0 <t <T) Here, since n (t) is random noise, as K increases, that is, as the number of averaging increases, N becomes 0. Approach. Therefore, by performing the averaging, the averaging waveform 53 in which the noise amount N is reduced can be obtained.

This average zinc is the fourth step STE.
₄ take place in CPU11 as the fifth step STE ₅
Proceed to. If it is not a periodic signal in the third step STE ₃ , the process also proceeds to the fifth step STE ₅ .

Fifth step STE _{5 to} seventh step S
TE ₇ corresponds to the display mode of the seventh step ST ₇ of FIG. 3, and in this mode as well, it is determined in the fifth step STE ₅ whether it is a periodic signal or not, and if it is NO, it is the sixth step STE ₆ Proceed to step 7 to perform the display shown in display example (I), and if YES as the periodic signal, the seventh step ST
Proceeding to E ₇ , the display shown in the display example (II) is displayed on the display device 13.

One example of the display example (I) and the display example (II) is shown in FIGS. 11A and 11B and FIGS. 12A and 12B. 11A and 12A show a recording signal 36, and FIGS. 11B and 12B show a reproducing signal 47, which are arranged in parallel and displayed on a screen such as a CRT of the display device 13. The position of the error 52 is displayed as a straight line across the recorded signal 36 and the reproduced signal 47, and the correspondence is displayed clearly and easily visually.

The waveform of the broken line in FIG. 12B shows the averaged reproduced waveform 53. In this case, the averaged reproduced waveform 53 with improved S / N is displayed overlapping the reproduced waveform 47, which is an error cause. For example, it is easy to understand whether the S / N is bad or the intersymbol interference is large.

According to the error analyzing apparatus for the recording / reproducing system of the present invention, since the recording signal can be generated and the reproducing signal can be analyzed by the same apparatus, the comparison with the recording signal, which has conventionally been troublesome, can be performed very easily. It is possible to analyze whether an error has occurred due to any cause.

Since the data generated in the CPU can be output at an arbitrary data rate, it can be used as a recording data generator.

Furthermore, it is possible to construct a system having many effects such as a new modulation method can be studied without constructing hardware.

[0055]

According to the error analyzing apparatus of the recording / reproducing system of the present invention, it is possible to obtain a digital recording / reproducing of higher frequency and high density by analyzing the non-linearity of the recording / reproducing system.

[Brief description of drawings]

FIG. 1 is a principle system diagram of an error analysis device of a recording / reproducing system of the present invention.

FIG. 2 is a block diagram showing an embodiment of a recording / reproducing system error analyzing apparatus of the present invention.

FIG. 3 is a flow chart showing an embodiment of a recording / reproducing system error analyzing apparatus of the present invention.

FIG. 4 is a functional block diagram of recording encoding, recording equalization, as well as reproduction equalization, and detection used in the error analysis device of the recording / reproduction system of the present invention.

5 is a waveform explanatory diagram of a recording equalization unit in FIG.

FIG. 6 is a waveform explanatory diagram of the reproduction equalization unit of FIG.

FIG. 7 is a waveform explanatory diagram of the detection unit in FIG.

8 is a more detailed flow chart of steps 6 and 7 of the flow chart of FIG. 3;

FIG. 9 is a diagram of a sync signal and an error detection waveform according to the present invention.

FIG. 10 is an averaging waveform diagram of the present invention.

FIG. 11 is a waveform diagram showing a first display example of the present invention.

FIG. 12 is a waveform diagram showing a second display example of the present invention.

FIG. 13 is a conventional error detection configuration diagram.

[Explanation of symbols]

 10 Memory 11 CPU 13 Display Device 14 Control Register 15 ADC 16 DAC

Claims (3)

[Claims] 1. An error analysis device for a recording / reproducing system for analyzing non-linearity of a recording / reproducing system, comprising: a recording / reproducing means capable of recording and reproducing a signal of the recording / reproducing system; and a computer via a bus. A connected storage means, a computer capable of outputting the data stored in the storage means as recording data to the recording / reproducing means and taking in a reproduction signal from the recording / reproducing means as reproduction data through the storage means, An error analysis apparatus for a recording / reproducing system, comprising: a display unit which is connected to a computer and can display the error signal position as well as the recording and reproducing signals. 2. The error detection is performed by adding a sync pattern signal to the recording signal and comparing a 0.1 series from a reproduced signal having a period with a recording signal series. 1. An error analysis device for recording / reproducing system according to 1. 3. The error analysis device for a recording / reproducing system according to claim 1, wherein the reproduced signals are added for each cycle and averaged to reduce noise.