JPH0650529B2 - Data processing device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a data processing device based on a data flow processing system.

<Prior Art> Conventionally, as a data processing device by a data flow processing method, a plurality of microprocessors (hereinafter abbreviated as PE) of the data flow processing method are connected by a network, and an external memory is accessed to each PE. There are those that are connected via a circuit.

An example of such a data processing device is shown in FIG.

This data processing device has four PEs (PE1, PE2,
PE3, PE4) are connected by an inter-PE network 30 connected to a host computer, and external memories 31, 32, 33, 34 are respectively connected to the four PEs and access circuit 3
It is connected via 6, 37, 38 and 39.

Then, for example, when the PE1 accesses the external memory 32 of the PE2, the token for external memory access passes through the inside of the PE2 as shown by a dashed arrow and then reaches the external memory 32 via the access circuit 37. , Necessary writing to the external memory 32, or reading the content written in the external memory 32. After the processing, the resulting token is returned to PE1 via the access circuit 37 and PE2.

That is, when each PE accesses an external memory connected to a PE other than its own PE, the access token passes through the inside of a PE other than its own PE.

<Problems to be Solved by the Invention> As described above, in the above-described conventional data processing device, when each PE accesses the external memory connected to a PE other than its own PE, the access token is not Since it has to pass through the inside of the PE, it is necessary to perform processing for accessing the external memory in the passing PE, and the access time is longer than that in the case of accessing the external memory connected to the self PE. Time and P
There was a problem that it was delayed by the passage time in E.

Therefore, an object of the present invention is that each PE is a PE other than its own.
Another object of the present invention is to provide a data processing device which shortens the access time when accessing an external memory connected to the.

<Means for Solving the Problems> In order to achieve the above object, the present invention provides a data processing device in which a plurality of PEs are connected by a network, and an external memory is connected to each PE through an access circuit. The plurality of access circuits are connected to each other via a network, and the PEs connected to the PEs other than the self PE through the network connect the external memories to PEs other than the self PE.
The feature is that it can be accessed without going through.

<Operation> In the above configuration, each PE accesses an external memory connected to a PE other than its own PE via a network connecting a plurality of access circuits without passing through a PE other than its own PE. Therefore, the time required for each PE to access the external memory connected to a PE other than the self PE becomes short.

<Example> Hereinafter, the present invention will be described in detail with reference to illustrated examples.

FIG. 1 is a block diagram of a data processing device of this embodiment, and FIG. 2 is a block diagram of an access circuit for accessing an external memory in this data processing device.

As shown in FIG. 1, this data processing device has four PEs.
(PE1, PE2, PE3, PE4) are connected by the PE-to-PE network 10 connected to the host computer.
The PE1, PE2, PE3, and PE4 are connected to the external memories 11, 12, 13, and 14 via access circuits 16, 17, 18, and 19 for accessing the external memories. Then, the access circuits 16 and 1
7, 18 and 19 are connected by a network 20 between external memories.

The access circuits 16, 17, 18, and 19 have the same configuration, and the configuration is shown in FIG. 2 by taking the access circuit 16 as an example. The access circuit 16 includes a PE number setting circuit 21, an external memory access pre-merging circuit 22, a branch circuit 23, an external memory access post-merging circuit 24, and a branch circuit 2.
It is composed of 5. Then, the merging circuits 22 and 2
4. The network 20 between external memories is connected to the branch circuits 23 and 25.

The operation of the access circuit 16 will be described below.

The PE number setting circuit 21 sets the PE number used as a return destination in the external memory access token issued from PE1, and outputs this token to the merging circuit 22.
In the merge circuit 22, this token and the token for external memory access issued from another PE merge, and the branch circuit 2
3 is output. The branch circuit 23 determines the destination of the token from the access address or the designated flag attached to the input token, and outputs it to the external memory 11 according to the destination or the network between the external memories 2
Output to 0.

When the token output to the external memory 11 is subjected to the necessary processing there, the result token is output to the merging circuit 24. In the merging circuit 24, as a result, the token and the token that has passed through the external memory network 20 are merged and output to the branch circuit 25. The branch circuit 25 determines the PE number of the input token, and if the PE number is the number set by the PE number setting circuit 21, outputs the token to PE1. Output to 20.

Now, if the destination of the external memory access token output from PE1 is the external memory 11, it is output from the branch circuit 23 to the external memory 11, and as a result, the token returns to the PE1 via the merge circuit 24 and the branch circuit 25. On the other hand, if the destination is an external memory other than the external memory 11, it is output from the branch circuit 23 to the inter-external memory network 20, and after the necessary processing is performed in the external memory of the destination,
As a result, the token returns to PE1 via the external memory network 20, the merge circuit 24, and the branch circuit 25. For example,
When PE1 accesses the external memory 12 of PE2, the token flow is as shown by the broken arrow in FIG.

In this way, each PE connects an external memory connected to a PE other than its own PE via the inter-memory network 20 to its own PE.
It can be accessed without going through PEs other than. Therefore, the access time to the external memory connected to the PE other than the self PE becomes short. Also, since the external memory can be accessed without passing through a PE other than the own PE, it is not necessary to write a procedure for accessing the external memory for a PE other than the own PE, and the procedure related to the external memory access is simplified. As a result, when a high-level language for this device is created, code generation related to external memory access becomes easy. In addition, the external memory network 20
By providing the above, the traffic on the network for each PE to access the external memory increases, and the processing capacity increases.

In the above embodiment, the number of PEs and external memories is 4
The PE-to-PE network and the external-memory-to-PE network connecting these are connected as shown in FIG. 1, but the number of PEs and external memories is not limited to four, and the PE-to-PE network is not limited to four. The connection method of the network and the network between the external memories is not limited to the method shown in FIG.

In the above embodiment, the PE number setting circuit 21, the merging circuits 22 and 24, and the branch circuits 23 and 25 are provided in the access circuit for accessing the external memory.
The number setting circuit may be incorporated in each PE, and the merging circuit and the branch circuit may be incorporated in each external memory.

<Effects of the Invention> As is apparent from the above, the data processing device of the present invention connects the access circuits of the external memories connected to each of the plurality of PEs connected by the network with the network, and through the network. Each PE uses an external memory connected to a PE other than its own PE as a PE other than its own PE.
Since it can be accessed without going through, there are the following effects.

It is not necessary to write a procedure for external memory access to PEs other than the self PE, and the procedure for external memory access becomes simple.

Therefore, when a high-level language for this device is created, code generation related to external memory access becomes easy.

The traffic on the network for the PE to access the external memory increases, and the processing capacity increases.

The access time to the external memory connected to the PE other than the self PE becomes short.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a block diagram showing an access circuit in the above embodiment, and FIG. 3 is a block diagram showing a configuration of a conventional example. PE1, 2, 3, 4 ... Microprocessor of data flow processing system, 10 ... Network between PEs, 11, 12, 13, 14 ... External memory, 16, 17, 18, 19 ... Access circuit, 20 ... Network between external memories .

Claims (1)

[Claims] 1. A data processing device comprising a plurality of microprocessors of a data flow processing system connected by a network, and an external memory connected to each of the microprocessors via an access circuit, wherein the plurality of access circuits are connected by a network. It is characterized in that each of the microprocessors can be connected via this network to access an external memory connected to a microprocessor other than the own microprocessor without going through a microprocessor other than the own microprocessor. Data processing device.