JPH0650765B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0650765B2 JPH0650765B2 JP60190704A JP19070485A JPH0650765B2 JP H0650765 B2 JPH0650765 B2 JP H0650765B2 JP 60190704 A JP60190704 A JP 60190704A JP 19070485 A JP19070485 A JP 19070485A JP H0650765 B2 JPH0650765 B2 JP H0650765B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- silicon
- insulating film
- groove
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 52
- 239000010703 silicon Substances 0.000 claims description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
- 239000003990 capacitor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 18
- 238000003860 storage Methods 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に１つの絶縁
ゲート型電界効果トランジスタと１つの溝型情報蓄積容
量部とからなるメモリセルを有する半導体装置の製造方
法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor having a memory cell including one insulated gate field effect transistor and one groove type information storage capacitor section. The present invention relates to a method of manufacturing a device.
シリコン半導体基板に搭載してなる半導体記憶装置の大
容量化・高密度化は、新規な回路構成の考案、半導体基
板表面の微細加工技術の発展と共に急速な進展をしてい
る。従来、この種の半導体装置は、情報蓄積部が１個の
絶縁ゲート型電界効果トランジスタ（以下ＭＩＳ ＦＥ
Ｔと称す）と１個の情報蓄積容量部で構成され、しかも
情報蓄積容量部が単一のシリコン半導体基板に延在して
なる溝表面に形成した構造となっている。The increase in capacity and density of semiconductor memory devices mounted on a silicon semiconductor substrate is rapidly advancing along with the devising of a new circuit configuration and the development of fine processing technology on the surface of the semiconductor substrate. Conventionally, this type of semiconductor device has been known as an insulated gate field effect transistor (hereinafter referred to as MIS FE) having one information storage unit.
(Referred to as “T”) and one information storage capacitor section, and the information storage capacitor section is formed on the surface of a groove extending to a single silicon semiconductor substrate.
上述した従来の半導体装置は、溝表面に形成した絶縁膜
を誘電体膜とし、この誘電体膜を挟んで溝に埋込んだ容
量電極とシリコン基板とで容量部を形成し、この容量部
の一方の電極となるシリコンの基板側溝表面に電荷を蓄
積するような構造になっているため、さらに高密度化し
情報蓄積容量部間隔が狭くなってくると、情報蓄積容量
部間の電気的干渉が顕著となり、正常な情報蓄積が不可
能となる欠点を有している。これは情報蓄積の電位によ
りシリコン表面に空乏層が生じ、蓄えた情報電荷が隣接
した他の情報蓄積容量部に移ってしまうためであり、更
にこのシリコン表面に生じる空乏層はリーク電流を増加
させるため、蓄積した電荷が消失し易くする。又、α粒
子の透過によるソフトエラーが起り易くなる。このよう
なことから従来の半導体装置の構造では半導体記憶装置
の素子密度をさらに向上する事はむずかしいという問題
があった。In the conventional semiconductor device described above, the insulating film formed on the surface of the groove is used as a dielectric film, and the capacitor electrode and the silicon substrate buried in the groove sandwiching the dielectric film form a capacitor portion. Since the structure is such that charges are accumulated on the surface of the silicon substrate side groove, which is one of the electrodes, when the density is further increased and the interval between the information storage capacitor portions becomes narrower, electrical interference between the information storage capacitor portions may occur. It has a drawback that it becomes remarkable and normal information cannot be stored. This is because a depletion layer is generated on the silicon surface due to the potential of information storage, and the stored information charges are transferred to another adjacent information storage capacitor portion. Further, the depletion layer generated on the silicon surface increases the leak current. Therefore, the accumulated charges are easily lost. In addition, a soft error due to the transmission of α particles is likely to occur. For this reason, in the structure of the conventional semiconductor device, it is difficult to further increase the element density of the semiconductor memory device.
本発明の目的は、情報蓄積容量部相互の電気的干渉を減
らし、半導体記憶装置の素子密度をさらに向上させるこ
とが出来る半導体装置の製造方法を提供することにあ
る。An object of the present invention is to provide a method of manufacturing a semiconductor device, which can reduce electric interference between the information storage capacitors and further improve the element density of the semiconductor memory device.
本発明の半導体装置の製造方法は、１つの絶縁ゲート型
電界効果トランジスタと１つの溝型情報蓄積容量部とか
らなるメモリセルを有する半導体装置の製造方法におい
て、不純物濃度が高い一導電型シリコン基板の表面に不
純物濃度が低い一導電型シリコン層を設ける工程と、こ
のシリコン層の所定領域を選択的に酸化して底面がシリ
コン基板に達する素子分離用の第１の絶縁膜を形成する
工程と、前記シリコン層の表面から一導電型記シリコン
基板の内部に延在する溝を形成する工程と、に誘電体膜
を形成する工程と、シリコン層を覆う誘電体膜における
溝の上端部を含めたその近傍に開口部を形成する工程
と、この開口部を覆い、溝表面に形成された誘電体膜を
覆い、かつ溝を埋め込む姿態に、不純物濃度が高い逆導
電型のシリコン膜からなる容量電極を形成し、この容量
電極からの拡散により底面がシリコン基板から離れた姿
態でシリコン層に不純物濃度が高い逆導電型の拡からな
るコンタクト領域を形成する工程と、容量電極の表面を
熱酸化して容量電極の表面に第２の絶縁膜を形成する工
程と、シリコン層の表面にゲート絶縁膜を形成し、容量
電極から所定距離はなれた位置のゲート絶縁膜の表面に
絶縁ゲート型電界効果トランジスタのゲート電極を形成
する工程と、半導体層の表面に底面が上記コンタクト領
域の底面より浅い姿態の不純物濃度が高い逆導電型のド
レイン領域，および底面が上記コンタクト領域の底面よ
り浅く上記コンタクト領域に接続する姿態の不純物濃度
が高い逆導電型のソース領域を形成する工程と、を有し
ている。The method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device having a memory cell including one insulated gate field effect transistor and one groove type information storage capacitor section, wherein a single conductivity type silicon substrate having a high impurity concentration is used. A step of providing a one-conductivity-type silicon layer having a low impurity concentration on the surface of, and a step of selectively oxidizing a predetermined region of this silicon layer to form a first insulating film for element isolation whose bottom surface reaches the silicon substrate. Including a step of forming a groove extending from the surface of the silicon layer into the silicon substrate of one conductivity type, a step of forming a dielectric film in the step of forming a dielectric film, and an upper end portion of the groove in the dielectric film covering the silicon layer. And a step of forming an opening in the vicinity thereof and a method of covering the opening, covering the dielectric film formed on the groove surface, and filling the groove with a silicon film of a reverse conductivity type having a high impurity concentration. Forming a capacitor electrode, and forming a contact region having a reverse conductivity type expansion with a high impurity concentration in the silicon layer with the bottom surface separated from the silicon substrate by diffusion from the capacitor electrode, and the surface of the capacitor electrode. A step of forming a second insulating film on the surface of the capacitor electrode by thermal oxidation, and forming a gate insulating film on the surface of the silicon layer, and insulating gate type on the surface of the gate insulating film at a position apart from the capacitor electrode by a predetermined distance. A step of forming a gate electrode of a field effect transistor, and a drain area of a reverse conductivity type having a high impurity concentration in which a bottom surface is shallower than the bottom surface of the contact area on the surface of the semiconductor layer, and a bottom surface shallower than the bottom surface of the contact area. And a step of forming a source region of the opposite conductivity type having a high impurity concentration that is connected to the contact region.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例にもとずいて形成された半導
体装置を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device formed according to an embodiment of the present invention.
この半導体装置は、先ず、比抵抗が0.001〜0.01−cm
のP++型シリコン基板１０１上に比抵抗が0.1〜10−cm
で膜厚が１〜５μｍのＰ型シリコン層１０２を設け、さ
らにＰ型シリコン層１０２の表面に膜厚が0.2〜1.0μｍ
のシリコン酸化膜等の絶縁膜１０３を形成する。次に、
Ｐ型シリコン層１０２表面からP++型シリコン基板１０
１に延在した深さが２〜10μｍの溝を形成し、この溝表
面にシリコン酸化膜又はシリコン窒化膜等の誘電体膜１
０４を設ける。更に、この誘電体膜１０４を被覆してＮ
型の不純物を含む多結晶シリコン等で容量電極１０５を
設け、誘電体膜１０４を挟んで容量電極１０５とP++型
シリコン基板１０１並びにＰ型シリコン層１０２との間
で情報蓄積部の容量部を形成する。更に、情報を出し入
れする為のMIS FETはＮ型シリコン層のドレイン領域１
０７及びソース領域１０８並びにＰ型シリコン層１０２
の上にゲート絶縁膜１０９を介して設けられたゲート電
極１０６とで構成される。そして、ソース領域１０８は
Ｎ型シリコン層のコンタクト領域１１０を通して容量電
極１０５に電気的に接続されている。最後に、絶縁膜１
１１上に電極配線１１２を形成し、本発明の第１の実施
例である半導体装置ができる。ここで、ドレイン領域１
０７をビット線、ゲート電極１０６をワード線とすれ
ば、本発明の一実施例にもとずく半導体装置は半導体記
憶装置の情報蓄積部を構成する。First, this semiconductor device has a specific resistance of 0.001 to 0.01-cm.
On the P + + type silicon substrate 101 of 0.1 to 10-cm
A P-type silicon layer 102 having a thickness of 1 to 5 μm is provided, and the thickness of the P-type silicon layer 102 is 0.2 to 1.0 μm.
An insulating film 103 such as a silicon oxide film is formed. next,
From the surface of the P-type silicon layer 102 to the P ++- type silicon substrate 10
1 is formed with a groove having a depth of 2 to 10 μm, and a dielectric film 1 such as a silicon oxide film or a silicon nitride film is formed on the surface of the groove.
04 is provided. Further, by covering the dielectric film 104, N
The capacitive electrode 105 is formed of polycrystalline silicon containing a type impurity, and the capacitive electrode 105 is sandwiched between the capacitive electrode 105 and the P ++ type silicon substrate 101 and the P type silicon layer 102. To form. Furthermore, the MIS FET for transferring information in and out is the drain region 1 of the N-type silicon layer.
07 and source region 108 and P-type silicon layer 102
And a gate electrode 106 provided over the gate insulating film 109. The source region 108 is electrically connected to the capacitor electrode 105 through the contact region 110 of the N-type silicon layer. Finally, insulating film 1
By forming the electrode wiring 112 on the semiconductor device 11, the semiconductor device according to the first embodiment of the present invention can be obtained. Here, the drain region 1
If 07 is a bit line and gate electrode 106 is a word line, the semiconductor device according to one embodiment of the present invention constitutes an information storage unit of a semiconductor memory device.
第２図(a)〜(h)は本発明の一実施例を説明するための工
程順の断面図である。2 (a) to 2 (h) are sectional views in the order of steps for explaining one embodiment of the present invention.
第２図(a)に示すように、比抵抗が0.001〜0.01−cmの
P++型シリコン基板１０１表面に比抵抗が0.1〜10−c
m、膜厚が１〜５μｍのＰ型シリコン層１０２をエピタ
キシャル成長又はＣＶＤ法にて堆積した後、このシリコ
ン層１０２を選択的にシリコン酸化し絶縁膜１０３を形
成する。As shown in Fig. 2 (a), the specific resistance is 0.001-0.01-cm.
The resistivity of the P ++ type silicon substrate 101 is 0.1 to 10-c.
After a P-type silicon layer 102 having a thickness of m and a thickness of 1 to 5 μm is deposited by epitaxial growth or a CVD method, the silicon layer 102 is selectively silicon-oxidized to form an insulating film 103.
次に、第２図(b)に示すように、パターニングされた絶
縁膜又はホトレジスト膜でエッチング用のマスク材１１
３を形成する。Next, as shown in FIG. 2 (b), a mask material 11 for etching is formed of a patterned insulating film or photoresist film.
3 is formed.
次に、第２図(c)に示すように、上記マスク材１１３を
エッチング用のマスクとして、Ｐ型シリコン層１０２及
びP++型シリコン基板１０１の所定の領域をリアクティ
ブ イオン エッチングし、容量溝１１４を形成する。Next, as shown in FIG. 2 (c), using the mask material 113 as a mask for etching, reactive ion etching is performed on predetermined regions of the P type silicon layer 102 and the P ++ type silicon substrate 101, and the capacitance is increased. The groove 114 is formed.
次に、第２図(d)に示すように、容量溝１１４の側壁及
びＰ型シリコン層１０２表面を被覆する姿態に膜厚４０
〜２００Åの薄いシリコン酸化膜又はシリコン窒化膜を
形成し誘電体膜１０４を被覆する。Next, as shown in FIG. 2D, a film thickness of 40 is formed so as to cover the side wall of the capacitor groove 114 and the surface of the P-type silicon layer 102.
A thin silicon oxide film or silicon nitride film of about 200 Å is formed to cover the dielectric film 104.
更に、第２図(e)に示すように、コンタクト領域１１０
を設けるべきＰ型シリコン層１０２の表面の誘電体膜１
０４を除去した後、容量溝を埋込むようにＮ型不純物
（例えばリン，砒素）を含む多結晶シリコンを誘電体膜
１０４を被覆する姿態で形成し、これを容量電極１０５
とする。この工程で、多結晶シリコン膜に含有されたＮ
型不純物はコンタクト部１１０となるべき領域に拡散し
Ｎ＋型不純物領域が形成される。Further, as shown in FIG. 2 (e), the contact region 110
Dielectric film 1 on the surface of P-type silicon layer 102 to be provided with
After removing 04, polycrystalline silicon containing N-type impurities (for example, phosphorus and arsenic) is formed so as to cover the dielectric film 104 so as to fill the capacitance groove, and this is formed as the capacitance electrode 105.
And In this step, N contained in the polycrystalline silicon film
The type impurities are diffused into a region to be the contact portion 110, and an N + type impurity region is formed.
次に、第２図(f)に示すように、多結晶シリコンよりな
る容量電極１０５表面を熱酸化し、絶縁膜１１５を形成
する。Next, as shown in FIG. 2 (f), the surface of the capacitor electrode 105 made of polycrystalline silicon is thermally oxidized to form an insulating film 115.
更に、第２図(g)に示すように、Ｐ型シリコン層１０２
の上にゲート酸化膜１０９を介して、ゲート電極１０６
を多結晶シリコン又は高融点金属のシリサイド等で形成
し、このゲート電極１０６をマスクとしてＮ型不純物
（例えば砒素原子）をイオン注入法によりＰ型シリコン
層１０２表面に打込み、ドレイン領域１０７及びソース
領域１０８を設ける。ソース領域１０８はコンタクト領
域１１０と接するように設けられ、互いに電気的に接続
する。Further, as shown in FIG. 2 (g), the P-type silicon layer 102
On the gate electrode 106 via the gate oxide film 109.
Is formed of polycrystalline silicon or a refractory metal silicide, and N-type impurities (for example, arsenic atoms) are implanted into the surface of the P-type silicon layer 102 by ion implantation using the gate electrode 106 as a mask to form the drain region 107 and the source region. 108 is provided. The source region 108 is provided in contact with the contact region 110 and electrically connected to each other.
最後に、第２図(h)に示すように、絶縁膜１１１をＣＶ
Ｄ法により形成し、その上にアルミニウム又は高融点金
属等で電極配線１１２を設ける。Finally, as shown in FIG. 2 (h), the insulating film 111 is changed to CV.
It is formed by the D method, and the electrode wiring 112 is provided thereon with aluminum or a refractory metal.
以上、第２図(a)〜(h)で説明した方法により本発明の一
実施例にもとずいて形成された半導体装置ができる。As described above, a semiconductor device formed according to one embodiment of the present invention can be manufactured by the method described in FIGS. 2 (a) to 2 (h).
上記一実施例にもとずいて形成された半導体装置でわか
るように、情報電荷の蓄積は、絶縁ゲート型電界効果ト
ランジスタを通して容量部のソース領域と接続している
上部容量電極側で行なわれるので、誘電体膜を介した反
対側に高濃度の不純物を有する半導体基板を用いること
により誘電体膜に接する半導体基板表面の反転を抑え容
量値が低下することを防ぐことができる。As can be seen from the semiconductor device formed according to the above-mentioned one embodiment, since the information charge is accumulated on the side of the upper capacitance electrode connected to the source region of the capacitance portion through the insulated gate field effect transistor, By using the semiconductor substrate having a high concentration of impurities on the opposite side of the dielectric film, it is possible to suppress the inversion of the surface of the semiconductor substrate in contact with the dielectric film and prevent the capacitance value from decreasing.
また、上記一実施例にもとずいて形成された半導体装置
では、上記容量電極からの拡散により形成されたコンタ
クト領域の接合の深さに比べてソース領域（及びドレイ
ン領域）の接合の深さを浅くすることが可能なため、上
記絶縁ゲート型電界効果トランジスタの微細化が容易に
なる。更に、素子分離用の絶縁膜の底面は、Ｐ++型シリ
コン基板に接続しているため、別途チャネル・ストッパ
ー用の拡散層をこの絶縁膜の下に形成することなく、こ
の絶縁膜は隣接する溝型情報蓄積容量部間の素子分離
（および隣接する溝型情報蓄積容量部間の相互干渉の防
止）に十分機能する。In addition, in the semiconductor device formed according to the one embodiment, the junction depth of the source region (and the drain region) is larger than the junction depth of the contact region formed by diffusion from the capacitance electrode. Since it is possible to make shallow, it becomes easy to miniaturize the insulated gate field effect transistor. Furthermore, since the bottom surface of the insulating film for element isolation is connected to the P ++ type silicon substrate, this insulating film is adjacent without forming a diffusion layer for channel stopper separately under this insulating film. It sufficiently functions for element isolation between the groove type information storage capacitor sections (and prevention of mutual interference between adjacent groove type information storage capacitor sections).
以上説明したように本発明にもとずいて形成された半導
体装置は、高濃度不純物を含む半導体基板上に同一導電
型の低濃度不純物を含む半導体層を設け、その半導体層
表面から半導体基板に到る溝を設け、溝の表面に誘電体
膜を介して容量電極を設け、この容量電極を半導体基板
上に設けたMIS FETのソース電極と接続した構造となっ
ているので、従来構造に比べて情報蓄積部の間の電気的
干渉がなくなり情報蓄積部間隔をせばめることが可能と
なると共に情報電荷が絶縁物である誘電体膜上に形成し
た容量電極に蓄わえられるため、リーク電流が減少し情
報の保持時間を長くできるという効果がある。As described above, in the semiconductor device formed according to the present invention, a semiconductor layer containing a low concentration impurity of the same conductivity type is provided on a semiconductor substrate containing a high concentration impurity, and the semiconductor layer surface is transferred to the semiconductor substrate. It has a structure that connects the source electrode of the MIS FET provided on the semiconductor substrate with a capacitor electrode provided on the surface of the groove through the dielectric film, compared to the conventional structure. As a result, electrical interference between the information storage parts is eliminated, and it is possible to reduce the distance between the information storage parts, and information charges are stored in the capacitive electrode formed on the dielectric film, which is an insulator. Is reduced, and the information retention time can be lengthened.
更に、本発明では、α粒子の透過によるソフトエラーを
減少させるという効果もある。Furthermore, the present invention has the effect of reducing soft errors due to the transmission of α particles.
第１図は本発明の一実施例にもとずいて形成された半導
体装置の断面図、第２図は本発明の一実施例を説明する
ための工程順の断面図である。 １０１……P++型シリコン基板、１０２……Ｐ型シリコ
ン層、１０３……絶縁膜、１０４……誘電体膜、１０５
……容量電極、１０６……ゲート電極、１０７……ドレ
イン領域、１０８……ソース領域、１０９……ゲート絶
縁膜、１１０……コンタクト領域、１１１……絶縁膜、
１１２……電極配線、１１３……マスク材、１１４……
容量溝、１１５……絶縁膜。FIG. 1 is a sectional view of a semiconductor device formed according to an embodiment of the present invention, and FIG. 2 is a sectional view in order of steps for explaining the embodiment of the present invention. 101 ... P ++ type silicon substrate, 102 ... P type silicon layer, 103 ... Insulating film, 104 ... Dielectric film, 105
...... Capacitance electrode, 106 ...... Gate electrode, 107 ...... Drain region, 108 ...... Source region, 109 ...... Gate insulating film, 110 ...... Contact region, 111 ...... Insulating film,
112 ... Electrode wiring, 113 ... Mask material, 114 ...
Capacitance groove, 115 ... Insulating film.
フロントページの続き (56)参考文献 特開 昭60−126861（ＪＰ，Ａ) 特開 昭60−128657（ＪＰ，Ａ) 特開 昭60−152058（ＪＰ，Ａ) 特開 昭60−136367（ＪＰ，Ａ) 特開 昭60−65559（ＪＰ，Ａ) 特開 昭61−84053（ＪＰ，Ａ)Continuation of the front page (56) Reference JP 60-126861 (JP, A) JP 60-128657 (JP, A) JP 60-152058 (JP, A) JP 60-136367 (JP , A) JP 60-65559 (JP, A) JP 61-84053 (JP, A)
Claims (1)
と１つの溝型情報蓄積容量とからなるメモリセルを有す
る半導体装置の製造方法において、 不純物濃度が高い一導電型シリコン基板の表面に、不純
物濃度が低い一導電型のシリコン層を設ける工程と、 前記シリコン層の所定領域を選択的に酸化して底面が前
記シリコン基板に達する素子分離用の第１の絶縁膜を形
成する工程と、 前記シリコン層の表面から前記シリコン基板の内部に延
在する溝を形成する工程と、 全面に誘電体膜を形成する工程と、 前記シリコン層を覆う前記誘電体膜における前記溝の上
端部を含めたその近傍に開口部を形成する工程と、 前記開口部を覆い，前記溝表面に形成された前記誘電体
膜を覆い，かつ前記溝を埋め込む姿態に、不純物濃度が
高い逆導電型のシリコン膜からなる容量電極を形成し、
前記容量電極からの拡散により、底面が前記シリコン基
板から離れた姿態で前記シリコン層に不純物濃度が高い
逆導電型の拡散層からなるコンタクト領域を形成する工
程と、 前記容量電極の表面を熱酸化し、前記容量電極の表面に
第２の絶縁膜を形成する工程と、 前記シリコン層の表面にゲート絶縁膜を形成し、前記容
量電極から所定距離はなれた位置の前記ゲート絶縁膜の
表面に前記絶縁ゲート型電界効果トランジスタのゲート
電極を形成する工程と、 前記シリコン層に底面が前記コンタクト領域の底面より
浅い姿態の不純物濃度が高い逆導電型のドレイン領域，
および底面が前記コンタクト領域の底面より浅く前記コ
ンタクト領域に接続する姿態の不純物濃度が高い逆導電
型のソース領域を形成する工程と、 を有することを特徴とするシリコン装置の製造方法。1. A method of manufacturing a semiconductor device having a memory cell comprising one insulated gate field effect transistor and one groove type information storage capacitor, wherein the impurity concentration is high on the surface of a single conductivity type silicon substrate. A silicon layer of one conductivity type having a low conductivity, a step of selectively oxidizing a predetermined region of the silicon layer to form a first insulating film for element isolation whose bottom surface reaches the silicon substrate, and the silicon Forming a groove extending from the surface of the layer to the inside of the silicon substrate; forming a dielectric film on the entire surface; and including the upper end of the groove in the dielectric film covering the silicon layer. A step of forming an opening in the vicinity, a state of covering the opening, covering the dielectric film formed on the surface of the groove, and filling the groove; Forming a capacitor electrode made of silicon film,
Forming a contact region of a diffusion layer of a reverse conductivity type having a high impurity concentration in the silicon layer with the bottom surface separated from the silicon substrate by diffusion from the capacitance electrode; and thermally oxidizing the surface of the capacitance electrode. A step of forming a second insulating film on the surface of the capacitor electrode; forming a gate insulating film on the surface of the silicon layer; and forming a gate insulating film on the surface of the gate insulating film at a position apart from the capacitor electrode by a predetermined distance. Forming a gate electrode of an insulated gate field effect transistor; and a drain region of a reverse conductivity type in which a bottom surface of the silicon layer is shallower than a bottom surface of the contact region and the impurity concentration is high,
And a step of forming a source region of a reverse conductivity type in which the bottom surface is shallower than the bottom surface of the contact region and is connected to the contact region and the impurity concentration is high, and a method for manufacturing a silicon device, comprising:
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60190704A JPH0650765B2 (en) | 1985-08-28 | 1985-08-28 | Method for manufacturing semiconductor device |
| DE8686104427T DE3681490D1 (en) | 1985-04-01 | 1986-04-01 | DYNAMIC MEMORY ARRANGEMENT WITH OPTIONAL ACCESS WITH A VARIETY OF INTRANSISTOR CELLS. |
| EP86104427A EP0201706B1 (en) | 1985-04-01 | 1986-04-01 | Dynamic random access memory device having a plurality of improved one-transistor type memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60190704A JPH0650765B2 (en) | 1985-08-28 | 1985-08-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6249650A JPS6249650A (en) | 1987-03-04 |
| JPH0650765B2 true JPH0650765B2 (en) | 1994-06-29 |
Family
ID=16262452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60190704A Expired - Lifetime JPH0650765B2 (en) | 1985-04-01 | 1985-08-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650765B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63258061A (en) * | 1987-04-15 | 1988-10-25 | Nec Corp | Semiconductor memory device and manufacture thereof |
| JPH0233721A (en) * | 1988-07-22 | 1990-02-02 | Mitsubishi Electric Corp | Magnetic head |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184053A (en) * | 1984-10-01 | 1986-04-28 | Hitachi Ltd | semiconductor equipment |
| JPH0640573B2 (en) * | 1983-12-26 | 1994-05-25 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| JPS6065559A (en) * | 1983-09-21 | 1985-04-15 | Hitachi Ltd | Semiconductor memory |
| JPS60126861A (en) * | 1983-12-13 | 1985-07-06 | Fujitsu Ltd | Semiconductor memory device |
| JPS60128657A (en) * | 1983-12-15 | 1985-07-09 | Toshiba Corp | Semiconductor memory device |
| JPS60152058A (en) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | Semiconductor memory device |
-
1985
- 1985-08-28 JP JP60190704A patent/JPH0650765B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6249650A (en) | 1987-03-04 |
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