JPH0650917B2 - Time division multiple time switch control system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex time switch control system for time division switching, and more particularly to a time division multiplex time switch which handles various types of traffic at various speeds in a multiple manner. Regarding control method.

[Prior art]

Currently, Digital Integrated Services Network (ISDN: Integrat)
ed Service Digital Network) is being energetically pursued both inside and outside the country. ISDN is a network that comprehensively handles not only voice communication but also various communication services such as data images and images.

In this case, if these various communication services can be provided by a single network with little overhead, simplification of the communication network,
It is considered that there are considerable advantages such as centralized maintenance and operation. It is also well known that ISDN is required to provide not only services of 64 kb / s or 1 / n or n times that of voice communication, but also communication services in an extremely wide speed range including images. Therefore, it is desired to realize a switch with a single architecture that can handle these as easily and uniformly as possible.

Based on the above idea, a new switching system called "line / packet integrated switching system" (patent application) for exchanging various communication services in an extremely wide speed range with a single architecture integrated switching system including circuit switching / packet switching. Japanese Patent Application No. 58-044740 and Japanese Patent Application No. 58-095169, the following document 1
And 2) are proposed.

In the method of the invention described in the above-mentioned documents 1 and 2, as shown in FIG. 2, an exchange is used as a building block communication node, and these are connected by a plurality of loops, and a plurality of lines extending between specific communication nodes are provided. For example, a method is adopted in which an exchange call is assembled into one mixed packet every 125 µsec of a voice sampling period and transmitted / received.

The "line / packet integrated switching system" according to the documents 1 and 2 will be briefly described below with reference to FIG. However, in FIG. 2 and the following description, the additional portion generated by the mixture of packet calls relating to the above method is not directly related to the description of the present invention, and therefore will be omitted.

In FIG. 2, the INF unit (interface circuit) in each communication node has an interface function for accommodating information from a subscriber line and an inter-office relay trunk group accommodated in the exchange, and digitally multiplexes these information. Alternatively, it has a function of demultiplexing. Further, the time division multiplex time switch memory circuit T temporarily buffers the call information in the digital multiplexed channel from the INF section in the forward direction from the INF section to the plurality of loops to convert the time phase between channels ( (Time switch function), and a function of editing a plurality of circuit-switched calls extending between specific communication nodes into a mixed packet format, which will be described later with reference to FIG. 3, and a transmission waiting function for a plurality of loops,
The reverse function described above is provided in the reverse direction from the multiple loops to the INF section. Further, CM in the figure is a time switch control memory circuit, which is an address for writing the digitally multiplexed call information coming from the INF section to the time division multiplexing time switch memory circuit T for each time slot, or vice versa. Divided / multiple time switch memory circuit T to INF
It has a function to specify the address from which the call information to be digitally multiplexed and sent to each unit is read out for each time slot.

Secondly, D / I is an interface circuit between the time division multiplex time switch memory circuit T of the communication node and multiple digital multiplex loops (multiple loops). Has the function of inserting (Insert function) or, conversely, the function of branching communication information addressed to its own module from multiple loops (Drop function).

FIG. 3 shows a mixed packet format used when assembling a plurality of circuit-switched calls spanning the specific communication nodes shown in FIG. 2 into one mixed packet and transmitting / receiving it through a loop. In the figure, DA is the number of the incoming communication node, SA is the number of the outgoing communication node, and DA and SA form a header section. Further, CH _{1 to} CH _n are n-channel call message parts in which a call is being made at the same time between the call-originating communication node and the call-receiving communication node, respectively. The size of the call message part of each channel is secured in proportion to the communication speed of the circuit switched call. For example, in the case of voice, the information amount of one voice channel included in one mixed packet can be one sample (8 bits). In addition, this method enables uniform switching of multiple communication services in an extremely wide speed range.

Now, an economical and concrete realization method of the conventional "line / packet integrated switching system" described above, in particular, a time division multiplex time switch memory circuit T shown in FIG. 2 and a time switch control memory which is its control circuit. As an economical and concrete method for realizing the circuit CM, a time division multiple time switch circuit shown in FIG. 4 (Japanese Patent Application No. 58-155581, reference 3).
Is proposed.

FIG. 4 is a time-division multiplex time switch memory circuit T described in FIG. 2 and a time switch control circuit CM for controlling the same.
FIG. 3 is a block diagram showing the outline and operation of the configuration of FIG. However, for the sake of simplicity in FIG. 4, the time division multiplex time switch memory circuit T shows a schematic circuit configuration related to the forward direction of the signal flow from the INF section to the loop side in FIG. The flowing circuit is omitted (the circuit in the reverse direction has almost the same structure as the forward direction, and can be easily inferred because the operation is just the reverse relationship).

The time division multiplex time switch memory circuit T shown in FIG. 4 is composed of two surfaces of the memory circuit configured by a so-called random access memory (RAM). The first memory side writes the call information for one frame of each digital multiplexed channel received from the INF section in an even time frame, and reads it in the next odd frame to execute the loop branch / insertion shown in FIG. It is sent to the interface circuit D / I having a function. On the contrary, the second memory surface writes the call information in the odd time frame and reads the call information in the next even time frame. The call information of the digital multiplexed channels from the INF section to the memory circuits of these two sides is written to the memory address designated by the time switch control memory circuit CM for each input time slot (random writing). The time switch control memory circuit CM, on the time division multiplex time switch memory circuit T, indicates that the call information of the input channel is addressed to the communication node # 1 in order from the head address of the memory (node in the figure). # 1) call information, node # 2 call information, ...
..., the call information addressed to the node #N, and the call information addressed to the communication node having the same number (for example, # 1), if there are n calls at that time, are also included in the channels # 1, # 2.
, #N (CH ₁ , ..., CH _{n in} FIG. 3) are arranged in order, and the write address is indicated for each input time slot.

As described above, as a result of writing the call information of the input channel to the time division multiplex time switch memory circuit T, the content is read from the head address at a speed consistent with the transmission speed of the loop side sequentially (sequential read). By adding the destination node address DA and the source node address SA as shown in FIG. 3 to each of a series of call information groups addressed to the same communication node, a desired mixed packet can be formed.

The reason why the time division multiplex time switch memory circuit T is provided on two surfaces for even and odd frames is to avoid the phenomenon of "slip" which is well known to those skilled in the art (for details, refer to the above-mentioned document 3). .

By the way, on the time division multiplex time switch memory circuit T, in order to arrange and write call information in order from the first address to # 1 channel, # 2 channel, ... With the occurrence of new calls,
It is necessary to update the content of the switch control memory circuit CM each time. Now, for example, when the call of the #j channel addressed to the communication node #i is restored, this call uses k words on the time division multiplex time switch memory circuit T, that is, this call is k times the basic communication speed. Assuming that the call is a speed call, the call memory use area of each call channel, which used the memory area located in the oldest number on the time division multiplex time switch memory circuit T, may be moved up by k addresses. . To do this, CM for each input time slot
Of the memory content of the memory, and the result is sent to the time division multiplex time switch memory circuit T, and at the same time, the result is compared with the address indicating the area used by the restored call,
If it is larger than the address of the restored call, the content may be subtracted by k and rewritten to the original position. On the other hand, when a k-fold call occurs, the call memory use area of each call channel that used the memory area located in the older area than the area on the time division multiplex time switch memory T to be used It is necessary to carry back each k address. For that purpose, as in the case of the memory contents of the CM, as described above, only the contents of the memory contents larger than the address indicating the area used by the new call may be added by k. Although not shown in the figure, the ASU (address shift unit) in FIG. 4 is an operation for performing the above-mentioned comparison of the memory contents of the CM and the correction operation according to an instruction from the control processor that controls the exchange call processing. Circuit.

[Problems of conventional technology]

In the conventional method described above, two communication nodes connected to the loop (hereinafter referred to as node i and node j) are communicating and a call in the direction from node i to node j is restored or a new call occurs. In such a case, the length of the mixed packet assembled in the time division multiplex time switch of the transmitting node i changes according to the above-described operation principle, the changed mixed packet is transmitted on the loop, and the time division multiplex in the receiving node j is performed. Written to the time switch. The mixed packet after this change goes down when the call data after the call or restoration channel is called, and goes up when the call data is restored,
Since the position is shifted, when the call data forming the mixed packet is read at the read address supplied by the switch control memory before the change at the node j,
Interference occurs because another call data is read.

That is, between the communication nodes, the time switch control memory needs to be updated at the time of making and receiving a call by synchronizing the time in frame units between the call originating and terminating nodes. Since no means for updating the switch control memory has been provided, the interference cannot be completely prevented.

[Object of the Invention]

The present invention has been made to solve the above-mentioned drawbacks, and time-division multiplexing time switch control in which the frame time for updating the time switch control memory of each node associated with call origination and restoration is made coincident and the above-mentioned interference is prevented. The purpose is to provide a scheme.

[Structure of Invention]

The present invention relates to a time division multiplex time of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control method for controlling a switch, an N-ary counter for counting the number of time division multiplex frames is provided in the communication node, and when communication is set or released between communication nodes, the communication node is connected between the communication nodes each time. The value m of 0 ≦ m ≦ N−1 is selected by the meeting, and then the communication node determines that the value of the N-ary counter is the value at the time of the meeting and the selected value m and mod.
When it becomes equal to the sum of N, the contents of the time switch control memory of the communication node are changed so that the communication is set or released.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram showing the configuration of each node in the embodiment of the time division multiplex time switch control system of the present invention. Figure 1 shows
It shows a case where an input call signal coming from the INF section is transmitted to the INF section on the outgoing side through the route of the transmission node → loop → reception node. The transmitting node includes an INF unit, a transmission time division multiplex time switch 10, a transmission time switch control memory 11, a loop interface 12, and a control processor 1.
3, an N-ary counter 14, a comparison circuit 15, and a holding circuit 16. The receiving node includes an INF unit, a receiving time division multiplex time switch 20, a receiving time switch control memory 21, a loop interface 22, a control processor 23,
It comprises an N-ary counter 24, a comparison circuit 25, and a holding circuit 26. The transmitting node and the receiving node are connected by loops # 1 to # in the loop interface.

In FIG. 1, the operations of the transmission time division multiplex time switch 10, the transmission time switch control memory 11, and the transmission loop interface 12 are the same as those of the conventional time division multiplex time switch shown in FIGS. 2 and 4. Memory circuit T, time switch control memory circuit CM, interface circuit D / I
And the same respectively.

In addition, the reception time division multiplex time switch 20, the reception time switch control memory 21, the reception loop interface 22.
The operation of is almost the same as the operation of the transmitting side, except that the data flow is in the opposite direction. On the other hand, N-base counters 14 and 24
Is 1 frame time at each node (eg 125μ
Every s), +1 is added and the frame time from 0 to N-1 is counted.

Here, the operation when a new call originates from the transmitting node to the receiving node will be described. The control processor 13 that controls the transmitting node uses an appropriate value m (0 ≦ m ≦ N−
Select 1). This value m is m from the time the call originates.
This means that the transmission time switch control memory 11 is updated after the frame time. Control processor of sender node
13 transmits this value m and the update information of the time switch control memory associated with the call to the receiving node via the loop.
At the same time, the value K _s (0 ≦ K _s ≦ N−1) of the N-ary counter 14 is read and stored.

The control processor 23, which controls the receiving node, checks whether or not it is possible to update the reception time switch control memory 21 m frame time after the information from the control processor 13 is received. This is because there are cases where it has already been decided that the receiving node should update the receiving time switch control memory 21 with another communication node after m frame time designated by the transmitting node.

In this case, the control processor 23 of the reception node indicates that it is impossible to update the reception time switch control memory 21 after the m frame time designated for the control processor 13 of the transmission node. "Frame time block signal" through loop interface 22, loop, loop interface 12 control processor of the sending node
Reply to 13.

On the other hand, when the designated m frame time has elapsed, the control processor 23 stores this value m and the update information of the reception time switch control memory 21 and, at the same time, sends m frames to the control processor 13 of the transmitting node. After hours,
A “frame time / space signal” indicating that the reception time switch control memory 21 can be updated is returned to the control processor 13 of the transmission node via the loop interface 22, loop, and loop interface 12.

Control processor 23 of the receiving node at the same time reads the value of the N-ary counter _{24 K R (0 ≦ K R} N-1), a counter value after m frames _{(K R + m) modN (} K R + m
Is divided by N) and set in the holding circuit 26. This value and the value of the N-ary counter 24 are compared by the comparison circuit 25, and the reception time switch control memory 21 is updated according to the instruction of the control processor 23 in the coincident frame.

On the other hand, when the reply information is the "frame time block signal", the control processor 13 of the transmitting node which has received the reply information reselects the value of m and retries the above process. If you receive a "frame time empty signal" Conversely, it is a K _S call is a value of N-ary counter 14 at the time of the occurrence, the value of the N-ary counter 14 after m frames (K _S + m ) Mod N is calculated and the holding circuit 16 is set. This value and the value of the N-ary counter 14 are compared by the comparison circuit 15, and the transmission time switch control memory 11 is updated so that the call time is set by the instruction of the control processor 13 in the coincident frame.

In the above, the case where a new call originates between the transmitting node and the receiving node has been described, but the same is true except that the contents of the update information in the time switch control memories 11 and 21 are different when the call in progress is restored. Can be processed in steps.

In this embodiment, the update processing of the time switch control memory associated with the origination and restoration of a call has been described with respect to one communication node and a maximum of one call. However, the origination and restoration of a plurality of calls in one frame. The same procedure can be applied to a configuration capable of performing. In this case, since the probability that the frame time after the selected m frames is blocked by the partner node decreases, the invalid processing decreases, and the processing capacity of the system increases. 1 more
If you configure a system that can generate and recover an arbitrary number of calls in a frame, select the minimum m (0 ≤ m ≤ N-1) necessary for meeting between nodes and preparation for update, and notify the other node You do not need to send a reply from the partner node. Further, the value of N itself can be made smaller than that of the present embodiment.

The present invention is also applicable to general communication systems having shapes other than those shown in the above embodiments. For example, it is also effective for an ordinary electronic exchange system in which a communication node having a time division multiplex time switch and a time switch control memory is connected by a space division switch, and a communication system in which the communication nodes are connected by a bus. In these systems, the interference as shown in the conventional example of the present invention does not always occur even if the frame time for updating the time switch control memory is different between the communication nodes. However, if the frame time for updating the time switch control memory is different between the transmission node and the reception node, there is a problem that unnecessary data other than the transmission data appears at the reception node.
Therefore, by similarly applying the present invention and matching the frame times, these drawbacks can be completely eliminated.

[Effects of the Invention] As described above, according to the present invention, it is possible to match the frame times for updating the time switch control memory between the sending and receiving nodes at the time of origination and restoration of a call. The effect that the interference which was a fault can be prevented is acquired.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of each node in an embodiment of a time division multiplex time switch control system of the present invention, and FIG. 2 is a block diagram showing a configuration of a communication system to which the present invention is applied, FIG. 3 is a diagram showing an example of a mixed packet format when transmitting and receiving call information between communication nodes which are made into building blocks, and FIG. 4 is a block diagram showing a configuration of a time switch according to the prior art and its operation outline. It is a figure. 10 …… Time-division multiplexed time switch for transmission 11 …… Time switch for transmission Control memory 12 …… Loop interface 13 …… Control processor 14 …… N-ary counter 15 …… Comparison circuit 16 …… Holding circuit 20 …… Reception Time division multiple time switch 21 …… Reception time switch Control memory 22 …… Loop interface 23 …… Control processor 24 …… N-ary counter 25 …… Comparison circuit 26 …… Holding circuit INF …… Interface circuit T …… Time division Multiple time switch memory circuit CM …… Time switch control memory circuit D / I …… Loop interface circuit ASU …… Address shift unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H04Q 11/04 301 B 9076-5K 8529-5K H04L 11/20 102 F

Claims (1)

[Claims] 1. A time division multiplex of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control system for controlling a time switch, an N-ary counter for counting the number of time division multiplex frames is provided in the communication node, and when communication is set up or released between communication nodes, the communication node concerned each time A value m of 0 ≦ m ≦ N−1 is selected by a meeting between them, and then the communication node concerned mod N of the value at the time when the value of the N-ary counter is at the meeting and the selected value m. When the sum is equal to the sum, the contents of the time switch control memory of the communication node are set or released for the communication. A time division multiplex time switch method characterized by changing to.