JPH0650919B2 - Time division multiple time switch control system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex time switch control system for time division switching, and more particularly to a time division multiplex time switch which handles various types of traffic at various speeds in a multiple manner. Regarding control method.

[Prior art]

Currently, Digital Integrated Services Network (ISDN: Integrat)
ed Service Digital Network) is being energetically pursued both inside and outside the country. ISDN is a network that comprehensively handles not only voice communication but also various communication services such as data images and images.

In this case, if these various communication services can be provided by a single network with little overhead, simplification of the communication network,
It is considered that there are considerable advantages such as centralized maintenance and operation. It is also well known that ISDN is required to provide not only services of 64 kb / s or 1 / n or n times that of voice communication, but also communication services in an extremely wide speed range including images. Therefore, it is desired to realize a switch with a single architecture that can handle these as easily and uniformly as possible.

Based on the above idea, a new switching system called "line / packet integrated switching system" (patent application) for exchanging various communication services in an extremely wide speed range with a single architecture integrated switching system including circuit switching / packet switching. Japanese Patent Application No. 58-044740 and Japanese Patent Application No. 58-095169, the following document 1
And 2) are proposed.

In the method of the invention described in the above-mentioned documents 1 and 2, as shown in FIG. 2, a switching system is used as a communication node in which building blocks are formed, and these are connected by a plurality of loops, and a plurality of lines extending between specific communication nodes are connected. For example, a method is adopted in which an exchange call is assembled into one mixed packet every 125 µsec of a voice sampling period and transmitted / received.

The "line / packet integrated switching system" according to the documents 1 and 2 will be briefly described below with reference to FIG. However, in FIG. 2 and the following description, the additional portion generated by the mixture of packet calls relating to the above method is not directly related to the description of the present invention, and therefore will be omitted.

In FIG. 2, the INF unit (interface circuit) in each communication node has an interface function for accommodating information from a subscriber line and an inter-office relay trunk group accommodated in the exchange, and digitally multiplexes these information. Alternatively, it has a function of demultiplexing. Further, the time division multiplex time switch memory circuit T temporarily buffers the call information in the digital multiplexed channel from the INF section in the forward direction from the INF section to a plurality of loops to convert the time phase between channels ( Time switch function),
In addition, it has a function of editing a plurality of circuit-switched calls extending over a specific communication node into a mixed packet format, which will be described later with reference to FIG. 3, and a transmission waiting function for a plurality of loops. Has the reverse function described above. Further, CM in the figure is a time switch control memory circuit, which is an address for writing the digitally multiplexed call information coming from the INF section to the time division multiplexing time switch memory circuit T for each time slot, or vice versa. It has a function of designating an address for reading out, for each time slot, call information to be digitally multiplexed and sent from the division / multiplex time switch / memory circuit T to the INF section.

Further, in FIG. 2, D / I is an interface circuit between the time division multiplex time switch memory circuit T of the communication node and a plurality of digital multiplex loops (a plurality of loops), and a call from the communication node is made at an idle time position on the plurality of loops. It has a function of inserting information (Insert function), or conversely, a function of branching communication information addressed to its own module from multiple loops (Drop function).

FIG. 3 shows a mixed packet format used when assembling a plurality of circuit-switched calls spanning the specific communication nodes shown in FIG. 2 into one mixed packet and transmitting / receiving it through a loop. In the figure, DA is the number of the incoming communication node, SA is the number of the outgoing communication node, and DA and SA form a header section. CH _{1 to} CH _h are n-channel communication message portions that are simultaneously talking between the source communication node and the destination communication node at that time. The size of the call message part of each channel is secured in proportion to the communication speed of the circuit switched call. For example, in the case of voice, the information amount of one voice channel included in one mixed packet can be one sample (8 bits). In addition, this method enables uniform switching of multiple communication services in an extremely wide speed range.

Now, an economical and concrete realization method of the conventional "line / packet integrated switching system" described above, in particular, a time division multiplex time switch memory circuit T shown in FIG. 2 and a time switch control memory which is its control circuit. As an economical and concrete method for realizing the circuit CM, a time division multiple time switch circuit shown in FIG. 4 (Japanese Patent Application No. 58-155581, reference 3).
Is proposed.

FIG. 4 is a time-division multiplex time switch memory circuit T described in FIG. 2 and a time switch control circuit CM for controlling the same.
FIG. 3 is a block diagram showing the outline and operation of the configuration of FIG. However, for the sake of simplicity in FIG. 4, the time division multiplex time switch memory circuit T shows a schematic circuit configuration related to the forward direction of the signal flow from the INF section to the loop side in FIG. The flowing circuit is omitted (the circuit in the reverse direction has almost the same structure as the forward direction, and can be easily inferred because the operation is just the reverse relationship).

In FIG. 4, the time division multiplex time switch memory circuit T is composed of two surfaces of the memory circuit configured by a so-called random access memory (RAM). The first memory plane writes the communication information for one frame of each digital multiplexed channel received from the INF section in the even time frame, and reads it in the next odd frame to execute the loop branch / insertion shown in FIG. It is sent to the interface circuit D / I having a function. On the contrary, the second memory surface writes the call information in the odd time frame and reads the call information in the next even time frame. The call information of the digital multiplexed channel from the INF section to the memory circuits on these two sides is written to the memory address designated by the time switch control memory circuit CM for each input time slot (random writing). The time switch control memory circuit CM is arranged on the time division multiplex time switch memory circuit T so that the call information of the input channel is addressed to the communication node # 1 in order from the head address of the memory (node in the figure). Call information for # 1), call information for node # 2, ...
..., the call information addressed to the node #N, and the call information addressed to the communication node at the same address (for example, # 1) are also channel # 1, # 2, if there are n calls at that time. …, #
The write address is instructed for each input time slot so as to be arranged in order n (CH ₁ , ..., CH _{h in} FIG. 3).

As described above, as a result of writing the call information of the input channel to the time division multiplex time switch memory circuit T, the content is read from the head address at a speed consistent with the transmission speed of the loop side sequentially (sequential read). By adding the destination node address DA and the source node address SA as shown in FIG. 3 to each of a series of call information groups addressed to the same communication node, a desired mixed packet can be formed.

The reason why the time division multiplex time switch memory circuit T is provided on two surfaces for even and odd frames is to avoid the phenomenon of "slip" which is well known to those skilled in the art (for details, refer to the above-mentioned document 3). .

By the way, on the time division multiplex time switch memory circuit T, in order to arrange and write call information in order from the head address to # 1 channel, # 2 channel, ... Alternatively, the content of the switch control memory circuit CM needs to be updated each time a new call occurs. Now, for example, # addressed to communication node #i
When the call of the j channel is recovered, if this call uses k words on the time division multiplex time switch memory circuit T, that is, if this call has a communication speed k times the basic communication speed, On the multi-time switch memory circuit T, the memory use area of the call of each communication channel, which has used the memory area located in the older number than this, may be advanced to the address k. To do this, enter C for each input time slot.
When the memory content of M is read out and the result is sent to the time division multiplex time switch memory circuit T, the result is compared with the address indicating the area used by the restored call, and when the result is larger than the address of the restored call, K the contents
Just subtract and rewrite to the original position. Conversely, k
When a new call of double call occurs, the memory use of the call of each communication channel was used in the time division multiplex time switch memory T. It is necessary to move the area down by k addresses.
For that purpose, as in the case of the memory contents of the CM, as for the memory contents larger than the address indicating the area used by the new call, the contents may be added by k. Although not shown in the figure, the ASU (address shift unit) in FIG. 4 is an operation for performing the above-mentioned comparison of the memory contents of the CM and the correction operation according to an instruction from the control processor that controls the exchange call processing. Circuit.

[Problems of conventional technology]

In the conventional method described above, two communication nodes connected to the loop (hereinafter referred to as node i and node j) are communicating and a call in the direction from node i to node j is restored or a new call occurs. In this case, the length of the mixed packet assembled in the time division multiplex time switch of the utterance node i changes according to the above-mentioned operation principle, the changed mixed packet is transmitted on the loop, and the time division multiplex in the receiving node j is performed. Written to the time switch. The mixed packet after this change goes down when the call data after the call or restoration channel is called, and goes up when the call data is restored,
Since the position is shifted, when the call data forming the mixed packet is read at the read address supplied by the switch control memory before the change at the node j,
Interference occurs because another call data is read.

That is, between the communication nodes, the time switch control memory needs to be updated at the time of making and receiving a call by synchronizing the time in frame units between the call originating and terminating nodes. Since no means for updating the switch control memory has been provided, the interference cannot be completely prevented.

[Object of the Invention]

An object of the present invention is to provide a time division multiplex time switch control system in which the frame times for updating the time switch control memories of respective nodes associated with call origination and restoration are made coincident to prevent the above-mentioned interference.

[Structure of Invention]

The present invention relates to a time division multiplex time of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control system for controlling a switch, the communication node is provided with an N-ary counter for counting the number of time-division multiplex frames and means for matching the value of the N-ary counter of each communication node. When communication is set or released between the communication nodes, a discussion is made that the communication is set or released between the communication nodes, and then, in the communication node, the value of the N-ary counter is 0 ≦ determined by the combination of the communication nodes. When the value m becomes equal to m ≦ N−1, the time switch control memo of the communication node The content, and changes to the communication are set or restored.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram showing the configuration of each node in the embodiment of the time division multiplex time switch control system of the present invention. First
The figure shows the case where the input call signal coming from the INF section is transmitted to the INF section on the output side through the route of the transmission node → loop → reception node. The transmitting node is an INF section,
Transmission time division multiplex time switch T _S , transmission time switch control memory CM _S , loop interface circuit D /
I, transmission counter / reset / data detection circuit DET
₁ , a N-ary counter CNT ₁ , a comparison circuit CMP ₁ , a holding circuit REG ₁ , and a control processor PROC ₁ .
The reception node includes an INF section, a reception time division multiplex time switch T _R , a reception time switch control memory CM _R , a loop interface circuit D / I, a reception counter / reset / data detection circuit DET ₂ , and an N-ary counter CNT _2. , Comparison circuit CMP ₂ , holding circuit REG ₂ , control processor PRO
It is composed of C ₂ . The transmitting node and the receiving node are connected by loops # 1 to #l in the loop interface circuit D / I.

In FIG. 1, a transmission time division multiplex time switch T _S ,
The operations of the transmission time switch control memory CM _S and the loop interface circuit D / I are the same as those of the conventional time division multiplex time switch memory circuit T shown in FIGS. 2 and 4.
This is similar to the time switch control memory circuit CM and the loop interface circuit D / I.

The operations of the reception time division multiplex time switch T _R , the reception time switch control memory CM _R , and the loop interface circuit D / I are almost the same as those of the transmission side, except that the data flow is in the opposite direction. is there. Further, in FIG. 1, N-ary counters CNT ₁ and CNT ₂ count frame times from 0 to N−1.

The N-ary counter of each communication node is controlled so that its value matches, for example, by the following procedure. That is, a specific pattern (hereinafter referred to as counter reset data) is defined as data transmitted on the loop. Counter reset data detection circuit DET ₁ , D
The ET ₂ monitors the received data from the loop supplied from the loop interface circuit D / I, and when detecting the counter reset data, the N-ary counter CNT ₁ ,
Supply reset pulse to CNT ₂ . Then, the reset pulse clears the N-ary counter. When one node (system management node, etc.) sends counter reset data to the loop during system initialization, each node connected to the loop receives this and resets the N-ary counter of its own node. It is cleared by a pulse and transferred to the next node. Since the counter reset data goes around the loop until the node that first sends it receives it again, the counter values of all the nodes become 0, and the counter values of each node match.

After that, the N-ary counter counts the frame time from 0 to N-1 by adding +1 at each node every frame time (for example, 125 μs).

Next, the operation when a new call originates from the transmitting node to the receiving node will be described. The control processor PROC ₁ which controls the transmitting node transmits the update information of the time switch control memory CM _S associated with the call to the receiving node via the loop interface circuit D / I and any loop, and at the same time receives the transmitting node and the receiving node. A value m (0 ≦ m ≦ N−1) determined by the combination of nodes is set in the holding circuit REG ₁ .

On the other hand, a control processor PROC for controlling the receiving node
₂ receives the update information from the loop interface circuit D / I, calculates the value m from the transmission node number attached to the update information, and sets the value of m in the holding circuit REG ₂ .

After that, both nodes compare the values of m set in the holding circuits REG ₁ and REG ₂ with the values of the N-ary counters CNT ₁ and CNT ₂ by the comparators CMP ₁ and CMP ₂ , and in the frame where these match, the control processor Then, the contents of the time switch control memories CM _S and CM _R are updated respectively, and desired communication is newly established between both nodes.

In the above, the case where a new call originates between the transmitting node and the receiving node has been described, but it is exactly the same except that the update information content of the time switch control memory is different even when the call in progress is restored. It can be processed by the procedure.

By the way, for the combination of the sending node and the receiving node, m
Various methods are conceivable as the method of determining. For example, m
There is a method (first example) of matching the number with the sending node number. In this case, the value of N in the N-ary counter matches the number of all communication nodes. This first example corresponds to providing a dedicated call setup / release frame time for each communication node. By doing so, even when the call setup / release requests from the respective nodes overlap, the overlapping of the update processing times is automatically avoided, and the control between the nodes can be simplified. In this case, if the update processing capacity of the time switch control memory is one call at the maximum for one communication node in one frame, the call setting / release processing capacity of the entire communication system is also one call / frame.

On the other hand, as another example (second example), there is a method of predetermining the value of m in each node for each of the partner nodes. When the update processing capacity of the time switch control memory is one call / frame / communication node, the value of m must be different for each communication node in each communication node. In this case, the value of N of the N-ary counter is the maximum value of m + 1. However, by doing so, at each frame time m, it becomes possible to set / release a call in a set of a plurality of transmission / reception nodes to which m is assigned, so that the call setting / release processing capability of the entire communication system is given first. It can be increased over the first example mentioned.

Furthermore, as a third example, there is a method of determining the value of m by a meeting between the nodes. With this method, in the communication system, control information and the like are transmitted and received between a new node and an existing node every time a communication node is added, and m is determined for each combination of nodes. After that, the call setup / release processing is performed using the value of m as in the second example. Also in this method, when the update processing capacity of the time switch control memory is 1 call / frame / communication node,
At the time of meeting between nodes, it is necessary to select the value of m such that the value of m for each node does not match. In this case, the call setup / release processing capability of the entire communication system can be increased more than that in the first example, as in the second example. Compared to the second example, since each node autonomously determines the value of m, system expansion,
It has the advantage of being easy to change.

Other than the above, a method of assigning a value of m is conceivable,
Whichever method is used, the interference problem described in the conventional example can be solved, and since the update processing time is automatically determined by the combination of the transmitting and receiving nodes, it is possible to simplify the control between nodes. is there.

By the way, the present invention can be applied to a general communication system having a shape other than those shown in the above embodiments.

For example, it is also effective for an ordinary electronic exchange system in which a communication node having a time division multiplex time switch and a time switch control memory is connected by a space division switch, and a communication system in which the communication nodes are connected by a bus. In these systems, the interference as shown in the conventional example of the present invention does not always occur even if the frame time for updating the time switch control memory is different between the communication nodes. However, if the frame time for updating the time switch control memory is different between the transmission node and the reception node, there is a problem that unnecessary data other than the transmission data appears at the reception node. Therefore, by similarly applying the present invention and matching the frame times, these drawbacks can be completely eliminated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to match the frame times for updating the time switch control memories between the sending and receiving nodes when a call is originated and restored. It is possible to obtain the excellent effect of preventing the interference.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration of each node in an embodiment of a time division multiplex time switch control system of the present invention, and FIG. 2 is a block diagram showing a configuration of a communication system to which the present invention is applied, FIG. 3 is a diagram showing an example of a mixed packet format when transmitting and receiving call information between communication nodes which are made into building blocks, and FIG. 4 is a block diagram showing a configuration of a time switch according to the prior art and its operation outline. It is a figure. T S _...... transmitting time division multiplexing time switch T R _...... time for receiving division multiplexing time switch CM S _...... transmission time switch control memory CM R _...... reception time switch control memories D / I ...... loop interface circuit DET ₁ , DET ₂ ... counter reset data detection circuit CNT ₁ , CNT ₂ ... N-ary counter CMP ₁ , CMP ₂ ... comparison circuit REG ₁ , REG ₂ ... holding circuit PROC ₁ , PROC ₂ ... control Processor INF ... Interface circuit T ... Time division multiple time switch CM ... Time switch control memory ASU ... Address shift unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H04Q 11/04 301 B 9076-5K 8529-5K H04L 11/20 102 F

Claims (1)

[Claims] 1. A time division multiplex of a communication system comprising a plurality of communication nodes having a time division multiplex time switch and a time switch control memory for controlling the time division multiplex time switch, and a communication network connecting the communication nodes. In a time division multiplex time switch control system for controlling a time switch, the communication node is provided with an N-ary counter for counting the number of time-division multiplex frames and means for matching the value of the N-ary counter of each communication node, When setting or releasing communication between the nodes, a discussion is made that the communication is set or released between the communication nodes, and then the value of the N-ary counter of the communication node is 0 determined by the combination of the communication nodes. When it becomes equal to the value m of ≦ m ≦ N−1, the time switch control method of the communication node concerned is obtained. Re contents, division multiplexing time switch control system when and changes such that the communication is set or restored.