JPH065100A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device capable of performing highly accurate speed selection in a wafer state. A semiconductor memory device includes a memory cell array 14 for storing information, a control circuit 18 for turning a data output control signal from on to off at a predetermined timing based on a reference clock input from the outside, and this control circuit. A sense amplifier circuit 15 that outputs the storage information read from the memory cell array 14 only when the data output control signal input from 18 is ON, and an output data latch that latches the storage information input from the sense amplification circuit 15. And a circuit 19. [Effect] Since speed selection can be performed depending on whether or not stored information is output from the latch circuit, the accuracy of this speed selection can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device containing a speed selection circuit for inspecting whether or not a read speed at the time of reading stored information from a memory cell meets a desired specification. is there.

[0002]

2. Description of the Related Art Generally, in manufacturing a semiconductor memory device, after the manufacturing process of the integrated circuit is completed, various characteristic tests such as an operation confirmation test are carried out in a wafer state, which results in a non-defective product. We are sorting out defective products and those that meet specifications and those that do not meet specifications.

As one of the characteristic inspections, an inspection called "speed selection" is known. This is done by measuring the access time of the read system of the semiconductor memory device (that is, the time required to read the stored information from the memory cell in the semiconductor memory device) and confirming that this access time is within the time set in advance as a specification. It is to inspect whether or not.

A read system of a conventional semiconductor memory device and a method of performing "speed selection" in this read system will be described below with reference to FIGS. 9 and 10. Figure 9
It is a block diagram which shows notionally the structure of the read system 60 in the conventional semiconductor memory device. In the figure, the address circuit 62 as an address buffer outputs the input address signal to the address decoder 63. The address decoder 63 outputs a read control signal according to the input address signal, and causes the memory cells in the memory cell array 64 to output stored information. This stored information is amplified by the sense amplifier circuit 65 and then output from the data output terminal 67 via the output circuit 66.

FIG. 10 is a timing chart showing the operation of the read system 60. As shown in the figure, when an address signal is input to the address circuit 62 (time t _A ), a control signal is output from the address decoder 63 to the memory cell array 64, and stored information is output from the sense amplifier circuit 65. This memory information data output terminal 67
Output (time t _B ) is delayed by a predetermined time. At this time, the elapsed time T ₀ from time t _A to time t _B is the access time of the read system 60.

The speed selection in the conventional read system 60 is performed by connecting the address input terminal 61 and the data output terminal 67 to the evaluation device and measuring the access time T ₀ by the evaluation device. It was This evaluation device is configured to output the address signal to the address input terminal 61, start the timer at the same time, and output the stored information from the data output terminal 67 to read the value of the timer at this time. . That is, the access time T ₀ is measured by this device, and the speed selection is performed depending on whether or not the access time T ₀ is within a predetermined time.

[0007]

When performing speed selection in this way, the access time T _{0 is determined} by the parasitic inductance, electrostatic capacity, electric resistance, etc. of the evaluation device described above.
There is an error in the measured value of. Further, this measurement error also changes depending on how the needle is brought into contact with the pad portions of the address input terminal 61 and the data output terminal 67, the wiring of the wiring connecting to the evaluation device, and the like. This is because these factors change the rounding of the waveform of the test clock supplied to the address input terminal 61, the output load condition, and the measurement accuracy.

Therefore, conventionally, in consideration of the factors of these measurement errors and the accuracy of the evaluation device, speed selection is performed with a sufficient margin, and further dicing of the wafer is performed for packaging. Later, it was decided to perform a second inspection with a high-performance evaluation device.

However, since the processing time of the semiconductor memory device has been increased in recent years, the access time T ₀ as a specification value tends to be shortened accordingly. For this reason, the influence of the measurement error as described above is increasing, and it becomes impossible to obtain sufficient measurement accuracy.

In recent years, there has been a case where such a semiconductor memory device is shipped to a user in a wafer state. In such a case, it is desirable to perform high-accuracy speed selection in the wafer state.

The present invention has been made in view of the above drawbacks of the prior art, and an object of the present invention is to provide a semiconductor memory device capable of performing highly accurate speed selection in a wafer state.

[0012]

[Means for Solving the Problems]

(1) A semiconductor memory device according to a first aspect of the invention is a control unit that switches a data output control signal from ON to OFF after a read reference time has elapsed, based on a storage unit that stores information and a reference clock input from the outside. A circuit, a sense amplifier circuit that outputs the storage information read from the storage unit only when the data output control signal input from the control circuit is ON, and the storage information input from the sense amplification circuit. And a latch circuit for latching. (2) A semiconductor memory device according to a second aspect of the present invention inputs a storage unit for storing information and at least one of a predetermined read control signal and an enable signal for reading the stored information from the storage unit, and performs the read operation. A reference clock generation circuit that generates a reference clock based on the timing of a control signal or an enable signal; and a control circuit that turns the data output control signal from ON to OFF after the read reference time has elapsed, based on the input reference clock. , A sense amplifier circuit which outputs the storage information read from the storage section only when the data output control signal input from the control circuit is ON, and the storage information input from the sense amplification circuit is latched And a latch circuit.

[0013]

According to the first aspect of the invention, the control circuit is configured so that the stored information is output from the sense amplifier circuit only when the stored information in the memory cell is read within the read reference time determined by the reference clock. Can be controlled with.
As a result, it is possible to determine whether or not the stored information is read within the read reference time, depending on whether or not the stored information is output from the latch circuit. Therefore, if this read reference time is made to correspond to the time defined as the specification of the access time, the speed selection can be performed depending on whether or not the stored information is output from the latch circuit.

Further, according to the second invention, at least one of the predetermined read control signal and the enable signal for reading the stored information is input to the reference clock generating circuit, and the reference clock is generated based on the timing of these signals. Since the reference clock is generated in the circuit, it is not necessary to input the reference clock from the evaluation device. Therefore, more accurate speed selection can be performed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) First, an embodiment of the first invention will be described. FIG. 1 is a block diagram conceptually showing the structure of a read system 10 in a semiconductor memory device according to this embodiment.

In the figure, an address signal is input to an address input terminal 11 from an evaluation device (not shown). The address circuit 12 also converts the input address signal into an address signal of a predetermined code. The address decoder 13 converts the input address signal into a control signal for controlling the memory cell array 14. In the memory cell array 14, memory cells that store binary information are arranged in a matrix, and the address decoder 13
Information about the memory cell selected in is stored or read.

The sense amplifier circuit 15 amplifies and outputs the stored information read from the memory cell array 14 when the control signal input from the control circuit 18 is on (here, "high"). When the control signal is off (here, "low"), the stored information is not output. The output data latch circuit 19 latches the stored information input from the sense amplifier circuit 15, and outputs the output circuit 20.
Is output from the data output terminal 21 via.

The input buffer 17 has a test input terminal 16
The reference clock input from is sent to the control circuit 18. The control circuit 18 has a normal sense amplifier control terminal 22.
When the sense amplifier control signal input from is in the read mode, the data output control signal is turned on / off by delaying the reference clock input timing by a predetermined time.

FIG. 2 shows an example of a specific electric circuit configuration of the sense amplifier circuit 15, the input buffer 17, and the control circuit 18, which are the main parts of the read system 10. In the figure, the input buffer 17 is a two-stage NOT circuit 3
It is composed of 5, 36. The pMOS transistor 37 is a pull-up transistor.

The control circuit 18 is a 2-terminal NAND circuit 23.
And a NOT circuit 24 and a pMOS transistor 25. The NAND circuit 23 inputs the reference clock from the input buffer 17 and the sense amplifier control signal from the sense amplifier control terminal 22, respectively. The NOT circuit 24 inverts the input value from the NAND circuit 23 and outputs it. Further, the pMOS transistor 25 has a gate connected to the output terminal of the NOT circuit 24 and a source connected to the power supply V _CC .

According to this structure, when both the reference clock and the mode control signal are "high", the output of the NAND circuit 23 is "low" and the output of the NOT circuit 24 is "high". Activate.
On the contrary, when at least one of the reference clock and the sense amplifier control signal is "low", the sense amplifier is inactivated.

The sense amplifier circuit 15 includes pMOS transistors 26 and 27 and nMOS transistors 28 to 32.
It is composed by. pMOS transistor 26,
27, the power source V _CC is connected to the source, and the drain of the pMOS transistor 25 (that is,
N _D ) is connected. The drains of the nMOS transistors 28 and 29 are connected to the drains of the pMOS transistors 26 and 27, respectively, and the gates thereof are connected to the output (that is, N _C ) of the NOT circuit 24. Furthermore, the drain of the pMOS transistor 26 and nM
The drain of the pMOS transistor 25 (that is, N _D ) is also connected to the drain of the OS transistor 28. The drains of the nMOS transistors 30 and 31 are connected to the sources of the nMOS transistors 28 and 29, respectively, and the sources thereof are both connected to the drain of the nMOS transistor 32. Also, the gates are
It is connected to the outputs D and / D of the memory cell array 14. The nMOS transistor 32 has a gate held at a predetermined potential and a source grounded.

According to such a configuration, N _C is "high", N
_{When D} is "low" (that is, when both the reference clock and the mode control signal are "high"), the sense amplifier amplifying circuit 15 is activated and amplifies the outputs D and / D of the memory cell array 14. On the other hand, when N _C is “low” and N _D is “high” (that is, when at least one of the reference clock and the mode control signal is “low”), the pMOS transistors 26 and 27 and the nMOS are
The transistors 28 and 29 are turned off, the sense amplifier circuit 15 is deactivated, and no output is performed.

The output data latch circuit 19 is composed of NOT circuits 33 and 34. NOT circuit 33
Outputs the inverted signal input from the sense amplifier circuit 15 described above. In addition, the NOT circuit 34 has an input terminal connected to the output terminal of the NOT circuit 33, and an output terminal connected to the input terminal of the NOT circuit 33. According to such a configuration, the signal input from the sense amplifier circuit 15 can be latched and the inverted value thereof can be output. That is, the output value of the output data latch circuit 19 becomes the same value as the output data D of the memory cell array 14 at that time.

Next, a method of performing speed selection using such a reading system 10 will be described with reference to FIG. FIG. 3 is a timing chart for explaining the operation of the read system 10.

The information "0" or "1" is stored in advance in each memory cell in the memory cell array 14.
In this embodiment, a case will be described in which speed selection is performed using a memory cell in which "1" is stored in advance in the memory cell. The output data latch circuit 19 is assumed to latch "0" in advance.

When an address signal is input from the address input terminal 11 (see FIG. 3A), the address circuit 12 takes in this address signal and converts it into an address signal of a predetermined code, and this address signal is decoded by the address decoder. 1
Output to 3.

The address decoder 13 outputs a control signal according to the input address signal, and the memory cell array 1
Stored information is output from the memory cell 14 corresponding to this address signal in 4 (see FIG. 3B). As described above, the value of this stored information is "1".

This stored information is sent to the sense amplifier circuit 15. Here, the delay time from the input of the address signal at the address input terminal 11 to the output of the stored information by the sense amplifier circuit 15 is T _S (see FIG. 3C).

On the other hand, the evaluation device (not shown) changes the reference clock output to the test input terminal 16 from high to low by delaying it from the output timing of the address signal by a predetermined time T _C (FIG. 3 (a)). This reference clock is taken into the control circuit 18 via the input buffer 17.

When the reference clock becomes low, the control circuit 18 further delays by a predetermined time to change the data output control signal sent to the sense amplifier circuit 15 from high to low (that is, from on to off). Here, the delay time (reading reference time) from the input of the address signal from the address input terminal 11 to the turning off of the data output control signal input to the sense amplifier circuit 16 is T _C1 (see FIG. 3).
(See (b)).

The sense amplifier circuit 15 fetches stored information from the memory cell array 14 as described above, but if the control signal input from the control circuit 18 at this time is ON (that is, when T _S ≤T _C1 ), this The stored information is output to the output data latch circuit 19. The stored information output from the output data latch circuit 19 is output to the output circuit 20.
Is output from the data output terminal 21 via
(See (D) and (E)). If the control signal is off at this time (that is, when T _S > T _C1 ), the stored information is not output. As described above, since the value of this stored information is "1", "1" is output from the sense amplifier circuit 15 if T _S ≤T _C1 . When T _S > T _C1 , the output value of the output data latch circuit 19 remains “0” (previous output data), so the output value of the data output terminal 21 also becomes “0”. Will remain as is.

Here, when T _S ≦ T _C1 , the access time T ₀ satisfies the specifications. That is, the above-mentioned predetermined time T _C is set in advance so that T _S ≦ T _C1 when the access time T ₀ satisfies the specifications. on the other hand,
When T _S > T _C1 , the access time T ₀ does not meet the specifications.

Therefore, the evaluation device (not shown) inputs the stored information output from the data output terminal 21, and if this value is "1", the speed selection is determined to be "good", and the stored information is stored. If the value of is "0", the speed selection is "defective"
And

As described above, according to the semiconductor memory device of the present embodiment, the speed selection can be performed depending on whether the storage information is output from the latch circuit. That is, it is not necessary for the evaluation device to measure the access time using a timer as in the conventional case. Therefore, the evaluation device only needs to determine the value of the data output from the data output terminal 21, and the contact between the wiring between the data output terminal 21 and the evaluation device and the needle abutment of the pad portion. Even if a data transfer delay or the like occurs due to the above, it does not cause a measurement error, so that speed selection can be performed with high accuracy even in the wafer state.

[0037] In the present embodiment, as described above, it was decided to set the specified value of the access time T ₀ by a predetermined time T _C, as zero the predetermined time T _C, all of the delay time T _C1 May be generated by the control circuit 18.

In this embodiment, the case where the first invention is applied to the speed selection for the access time after the input of the address signal has been described, but the access time after the input of the enable signal is described. It can also be applied to speed sorting.

(Embodiment 2) Next, an embodiment of the second invention will be described.

FIG. 4 is a block diagram conceptually showing the structure of the read system 40 in the semiconductor memory device according to the present embodiment. In the figure, the components denoted by the same reference numerals as those in FIG. 1 are the same as those in the case of FIG.

The address transition detection circuit 41 inputs an address signal from the address circuit 12 and detects a change in this address signal. Then, as shown in FIG. _6A , when the address signal changes, the address transition signal φ _ATD is output. In this embodiment, this address transition signal φ _ATD is used as a reference clock generation signal (hereinafter,
Reference clock generation signal φ _ATD ).

A chip enable signal (/ CE signal) is input from the / CE input terminal 42. And FIG.
As shown in (b), the / CE transition detection circuit 43 detects the falling edge of the / CE signal and outputs the reference clock generation signal φ _CE .

The reference clock generation circuit 44 inputs the reference clock generation signals φ _CE and φ _ATD and outputs the reference clock φ ₁
Generate ~ φ _n . FIG. 5 shows an example of an electric circuit configuration of the reference clock generation circuit 44. As shown in the figure,
The reference clock generation signals φ _CE and φ _ATD are input to the two input terminals of the NOR circuit 47, respectively.

Of the two input terminals of the NAND circuit N ₁ , one output terminal of the NOR circuit 47 is directly connected to one input terminal A, and the other input terminal B is connected to the output terminal of the NOR circuit 47. They are connected via 48-1 and 48-1 '. Here, the NOT circuits 48-1, 48-
1'is used as a delay element.

One of the two input terminals of the NAND circuit N ₂ is directly connected to the output terminal of the NOR circuit 47, and the other input terminal B is connected to the NAND circuit N ₁ via the NOT circuit 48-2. Is connected to the output terminal of. Here, the NAND circuit N ₁ and the NOT circuit 48-2
Acts as a delay circuit.

Similarly, the NAND circuits N _{1 to} N _n will be described below.
Is connected directly to the output terminal of the NOR circuit 47, and the input terminal B is connected to the NAN of the preceding stage via the NOT circuit.
The output terminal of the D circuit is connected.

It should be noted that the reference clock generation circuit 44 is preferably configured by using a transistor having a long channel length in order to reduce variations in delay time of each component due to manufacturing variations.

According to this structure, the reference clocks φ _{1 to} φ _n can be obtained as the outputs of the NAND circuits N _{1 to} N _n as follows. As shown in FIG. _6A, when the address signal input to the address transition detection circuit 41 changes, the reference clock generation signal φ _ATD becomes high. As a result, the output of the NOR circuit 47 becomes low, so that the input of the input terminal A of each NAND circuit N _{1 to} N _n becomes low, and therefore the output (that is, the reference clocks φ _{1 to} φ _n ) becomes high. After that, the inputs of the input terminals B of the NAND circuits N _{1 to} N _n also become low sequentially with a delay of a predetermined time, but at this time, the outputs of the NAND circuits N _{1 to} N _n do not change.

Next, the reference clock generation signal φ _ATD goes low. As a result, the output of the NOR circuit 47 (that is, the input of the input terminal A of each of the NAND circuits N _{1 to} N _n ) becomes high, but the input of the input terminal B remains low, so that each N
The output of the AND circuit N ₁ ~N _n remains high. Then, the input of the input terminal B of the NAND circuit N ₁ goes high after a delay predetermined time, whereby the output of the NAND circuit N ₁ (ie, the reference clock phi ₁₎ becomes low. Thus, further by a predetermined time delay, the input of the input terminal B of the NAND circuit N ₂ becomes high, the output of the NAND circuit N ₂ (or reference clock phi ₂₎ it becomes low.

Similarly, the outputs of the NAND circuits N _{3 to} N _n are delayed by a predetermined time and sequentially become low, as shown in FIG.
The reference clocks φ _{1 to} φ _n as shown in (a) are obtained.
By using the reference clocks φ _{1 to} φ _n generated in this way, it is possible to perform speed selection for the access time after the address signal is input.

When the / CE transition detection circuit 43 detects the falling edge of the / CE signal, the reference clock generation signal φ _CE becomes high as shown in FIG. 6 (b) and becomes low after a lapse of a predetermined time. In this case as well, the reference clock φ _{1 is} generated by the same operation as in the case of the reference clock generation signal φ _ATD.
~ Φ _n can be obtained. By using the reference clocks φ _{1 to} φ _n generated in this way, it is possible to perform speed selection for the access time after the enable signal is input.

The reference clock switching circuit 45 is adapted to enter these reference clocks phi ₁ to [phi] _n, selection signals S ₁ to S _n through the selection signal input terminal 46-1 to 46-n
Enter. Then, according to the selection signals S _{1 to} S _n , only one type of reference clock among the reference clocks φ _{1 to} φ _n is output to the control circuit 18.

FIG. 7 shows an example of the electric circuit configuration of the reference clock switching circuit 45. As shown in the figure, each of the switching circuits C _{1 to} C _n includes an nMOS transistor 4 respectively.
9, a pMOS transistor 50 and a NOT circuit 51. The nMOS transistor 5
Reference numeral 2 is a pull-down transistor.

In each switching circuit C ₁ -C _n
Source of transistor 49 and pMOS transistor 50
, And the drain of the nMOS transistor 49 and the source of the pMOS transistor 50 are connected. Then, the nMOS transistor 49
A corresponding reference clock is input to the drain of each of the above and the source of the pMOS transistor 50. Also, nMO
The corresponding selection signal is directly input to the gate of the S transistor 49, and the signal is input to the gate of the pMOS transistor 50 via the NOT circuit 51.

According to this structure, when the input selection signal is high, the nMOS transistor 49 and pMO are formed.
Since both S transistors 50 are turned on, the input reference clock is output as it is. On the other hand, when the input selection signal is low, both the nMOS transistor 49 and the pMOS transistor 50 are turned off and the reference clock is not output. Therefore, the selection signals S ₁ ~
By turning on one of the signals of S _n and turning off the other signals, a desired reference clock is supplied to the control circuit 18
Can be supplied to.

Next, a method of performing speed selection using such a reading system 40 will be described with reference to FIG. FIG. 8 is a timing chart for explaining the operation of the read system 40.

Information "0" or "1" is stored in advance in the memory cells in the memory cell array 14.
Also in the present embodiment, it is assumed that "1" is stored in the memory cell in advance and the output data latch circuit 19 latches "0" in advance, as in the first embodiment.

As in the case of the above-described first embodiment, the address signal input from the address input terminal 11 (see FIG. 8A) is converted into an address signal of a predetermined code by the address circuit 12, and further the address decoder. It is converted into a control signal in 13 and input to the memory cell array 14. As a result, the storage information is output from the memory cell corresponding to this address signal in the memory cell array 14 (see (b) of the same).

This stored information is sent to the sense amplifier circuit 15. Here, the delay time from the input of the address signal from the address input terminal 11 to the output of the stored information by the sense amplifier circuit 15 is T _S (see the same (C)).

On the other hand, in the control circuit 18, among the reference clocks φ _{1 to} φ _n (see FIGS. 5 and 6) generated by the reference clock generation circuit 44 as described above, the selection signals S ₁ to S _n are selected.
The one selected by the reference clock switching circuit (see FIG. 7) is taken in by S _n . When the control circuit 18 receives the reference clock, it delays the reference clock by a predetermined time to change the data output control signal sent to the sense amplifier circuit 15. Here, the delay time (read-out reference time) from when the address input terminal 11 inputs the address signal to when the data output control signal input to the sense amplifier circuit 16 turns from ON to OFF is T _C1 . (Fig. 8
(See (a)).

The sense amplifier circuit 15 fetches the stored information from the memory cell array 14 as described above, but if the control signal input from the control circuit 18 at this time is ON (that is, when T _S ≤T _C1 ), this The stored information is output to the output data latch circuit 19. If the control signal is off at this time (that is, when T _S > T _C1 ), the stored information is not output. As described above, since the value of this stored information is "1", if T _S <T _C1 , the sense amplifier circuit 15 outputs "1". The stored information output from the output data latch circuit 19 is output to the output circuit 20.
Is output from the data output terminal 21 via
(See (D) and (E)). When T _S ≧ T _C1 , the output value of the output data latch circuit 19 remains “0” (previous output data), so the output value of the data output terminal 21 also becomes “0”. Will remain as is.

The evaluation device (not shown) is the same as that of the first embodiment.
As in the case of, the memory information output from the data output terminal 21 is input. If this value is "1", the speed selection is "good", and if the value of this memory information is "0". Speed selection is "defective".

As described above, according to the semiconductor memory device of this embodiment, since the reference clock is generated using the address signal, it is not necessary to send the reference clock from the evaluation device to the semiconductor memory device. Here, the reference clock generation circuit 4
Since 4 is built in the semiconductor memory device, even if a delay occurs in the transfer of the address signal to the semiconductor memory device, the timing of the reference clock is also shifted by that amount. Don't

Further, as in the case of the above-mentioned first embodiment, since the evaluation device only needs to judge the value of the data output from the data output terminal 21, the evaluation device outputs data from the data output terminal 21. Even if a delay occurs in the transfer of output data, it does not cause an error in access time measurement.

Therefore, according to the semiconductor memory device of this embodiment, even if a delay in data transfer with the evaluation device occurs, it does not cause a measurement error. Speed sorting can be performed.

Further, in the present embodiment, since a plurality of reference clocks φ _{1 to} φ _n are generated and a desired reference clock is selected from among them, the allowable range of the access time when performing speed selection is set. The set value can be changed freely. As a result, it is possible to easily and accurately change the specification of the access time when using it for a plurality of types of screening tests. Further, when the manufacturing variability of the semiconductor memory device is large, the precision of speed selection can be improved by selecting and using the reference clock closest to the set value from the reference clocks φ _{1 to} φ _n .

[0067]

As described in detail above, according to the present invention, it is possible to provide a semiconductor memory device capable of performing high-accuracy speed selection in a wafer state.

[Brief description of drawings]

FIG. 1 is a block diagram conceptually showing the structure of a read system in a semiconductor memory device according to an embodiment of the first invention.

FIG. 2 is an electric circuit diagram showing a main part of the reading system shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the reading system shown in FIG.

FIG. 4 is a block diagram conceptually showing the structure of a read system in a semiconductor memory device according to an embodiment of the second invention.

5 is an electric circuit diagram showing a configuration example of the reference clock generation circuit shown in FIG.

6A and 6B are timing charts for explaining the operation of the reference clock generation circuit shown in FIG.

7 is an electric circuit diagram showing a configuration example of the reference clock switching circuit shown in FIG.

FIG. 8 is a timing chart for explaining the operation of the reading system shown in FIG.

FIG. 9 is a block diagram conceptually showing the structure of a read system in a conventional semiconductor memory device.

FIG. 10 is a timing chart for explaining the operation of the read system shown in FIG.

[Explanation of symbols]

 10, 40 Read system 11 Address input terminal 12 Address circuit 13 Address decoder 14 Memory cell array 15 Sense amplifier circuit 16 Test input terminal 17 Input buffer 18 Control circuit 19 Output data latch circuit 20 Output circuit 21 Data output terminal 22 Mode Input terminal 41 Address transition detection circuit 42 / CE Input terminal 43 / CE transition detection circuit 44 Reference clock generation circuit 45 Reference clock switching circuit

Claims (3)

[Claims] 1. A storage unit for storing information, a control circuit for switching a data output control signal from ON to OFF after a read reference time has elapsed, based on a reference clock input from the outside, and an input from this control circuit. A sense amplifier circuit that outputs the stored information read from the storage unit only when the data output control signal is on; and a latch circuit that latches the stored information input from the sense amplifier circuit. Semiconductor memory device. 2. A storage unit for storing information, and at least one of a predetermined read control signal and an enable signal for reading the stored information from the storage unit are input, and based on the timing of the read control signal or the enable signal. A reference clock generation circuit for generating a reference clock, a control circuit for switching a data output control signal from ON to OFF after a read reference time has elapsed based on the input reference clock, and the data input from the control circuit. A semiconductor memory including: a sense amplifier circuit that outputs the storage information read from the storage section only when the output control signal is on; and a latch circuit that latches the storage information input from the sense amplification circuit. apparatus. 3. The reference clock generation circuit is configured to generate a plurality of types of reference clocks for designating different read reference times, and the plurality of types of reference clocks are generated according to an input selection signal. 3. A reference clock switching circuit for selecting one of the reference clocks and outputting it to the control circuit.
The semiconductor memory device described.