JPH0652015A - Computer system - Google Patents

Abstract

PURPOSE:To automatically recognize the component and the constituting state of a system by arranging a bus register which does not depend on an electronic circuit board packaged on a node in each node in order to detect the state of each node on a system bus. CONSTITUTION:Bus registers 12a-12h which do not depend on an electronic circuit board packaged on a node are arranged in each node. To these bus registers 12a-12h, a fixed address in the computer system is imparted and bit patterns of the bus registers 12a-12h correspond to each other to one-to-one. In order to identifying the kind of the electronic circuit board connected to each node, the register allocated onto the bus is prepared at every electronic circuit board. The register identification register) for setting separate information at every electronic circuit board can be referred from other node. In order to arrange automatically shared resources on the bus, a number which does not overlap is imparted to each node.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a plurality of electronic circuit boards such as memories and I / O ports, which are shared resources, are interconnected by a system bus, and more particularly, it is connected to the system bus. The present invention relates to a component or electronic circuit board recognition means.

[0002]

2. Description of the Related Art Conventionally, in a computer system adopting a system bus system, an electronic circuit board such as a memory or an I / O port is connected to the system bus and becomes a shared resource used by a CPU or the like. In this type of system bus system, there is no function to identify the state of each node, that is, the connection point between the external system bus and the electronic circuit board, and the electronic circuit board mounted on each node.

Conventionally, the address of the electronic circuit board connected to the system bus is fixed for each electronic circuit board. To set this address: a. A method in which the user individually sets the DIP switches on the board, etc. b. There is a method to write an address to the non-volatile memory on the board by special software when the system is started. In any of these methods, the address is fixed for each electronic circuit board. Therefore,
When the configuration of the computer system is changed, the address of the electronic circuit board that is the shared resource may be duplicated. Therefore, it is necessary to reset the address of the electronic circuit board that is the shared resource each time the configuration of the computer system is changed. was there.

[0004]

In the conventional computer system, since there is no consideration regarding means for recognizing the configuration of the computer system, each electronic circuit board which is a component of the computer system is not considered. To check for the presence of c. If certain data can be written to the target electronic circuit board, the electronic circuit board exists. If no certain data can be written, the electronic circuit board does not exist. D. A method has been adopted in which an electronic circuit board is accessed when the target electronic circuit board is accessed and there is a response within a fixed time, and when there is no response within a fixed time, the electronic circuit board is absent.

However, in the method c, the read-only shared resource cannot be recognized because the write condition is used as the judgment condition. On the other hand, in the method of d, an error occurs each time an electronic circuit board that is not mounted is accessed, which is not desirable in system construction. Especially, in a system that does not manage time, a permanent system down will occur.

An object of the present invention is to provide a computer system having means for confirming the system configuration and recognizing the system state whenever necessary, and for allocating shared resources so as not to overlap.

[0007]

In order to achieve the above object, the present invention interconnects a plurality of electronic circuit boards, such as memories and I / O ports, which are arranged in each node and are shared resources, by a system bus. In the configured computer system, node information setting means installed in each node and having identification information unique to the node, and the identification information of the node and the state of the node are detected through an electronic circuit board connected to each node. The present invention proposes a computer system including means and means for recognizing identification information and status information of an electronic circuit board connected to each node.

The states of the respective nodes to be detected include valid / invalid of each node, that is, whether or not the electronic circuit board is connected to the node, a hardware operation state of the electronic circuit board,
At least one of the software operation status of the electronic circuit board (watchdog timer) and the error of the electronic circuit board is included.

The identification information and status information of the electronic circuit board connected to each node includes the identification number and version number of the electronic circuit board, the identification number and version number of software operating on the electronic circuit board, and an error occurrence. It contains at least one of the time error information.

[0010]

In the present invention, in order to detect the state of each node on the system bus, a register (bus register) independent of the electronic circuit board mounted on that node is arranged at each node. A fixed address in the computer system is given to these bus registers, and the bit pattern of the bus registers has a one-to-one correspondence with each node. When a node requests to read the bus register, each electronic circuit board on the bus must respond to the request. With this method, the state of each node can be recognized.

To identify the type of electronic circuit board connected to each node, a register allocated on the bus is prepared for each electronic circuit board. This register (identification register), which sets individual information for each electronic circuit board, can be referenced from other nodes.

A unique number is assigned to each node in order to automatically allocate the shared resources on the bus. The numbered numbers can be used whenever needed by the electronic circuit board mounted in each node. When this number is used for decoding the address on the bus, it becomes possible to automatically arrange the shared resources so that they do not overlap each other.

By reading the contents of the bus register and examining the data, the state of the node having the number corresponding to the data bit can be known. The invalid node is not accessed thereafter. For a valid node, the identification register assigned to that node can be read to obtain more detailed identification information. Which node is assigned the shared resource can be determined by the identification information of each node. Therefore, an electronic circuit board that requires a shared resource installed in a certain node can access the shared resource installed in the node by specifying a specific node number when accessing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of means for recognizing components in a computer system according to the present invention will be described below with reference to FIG. ◆ First, the CPU on the electronic circuit board connected to the m-th node
Assume that 1 accesses the bus register. The bus register is E on the system bus, for example in hexadecimal notation.
It is assumed that they are allocated from 0000000 to E00001BF. CPU1 uses the bus register E00000
When a read request is issued to 00, the address output by the CPU 1 passes through the local address bus 2 and the address buffer 4 and is output to the system address bus 6. Also,
The system lead wire or system read wire 16
It is driven via the local control bus 19 and the bus control circuit 20. The bus register 12 constantly monitors the system address bus 6 and the system lead wire 16 via the address buffer 8 and the command buffer 9.

E00000 on the system address bus 6
When an address from 00 to E00001BF appears, the output 10a of the decoder 10 becomes valid. Output 10
When the system lead wire 16 is driven in a state in which a is valid, the output 21a of the AND gate 21 is valid and the operation of the decoder 11 is valid. At this time, the decoder 11
Validates one of the eight outputs depending on the value of address 2 to address 4. The request of the CPU 1 is to detect whether the node is valid or invalid, that is, whether the electronic circuit board is connected to the node, and the output address at that time is E0000.
When set to 000, the output 11a of the decoder 11 becomes valid and the bus register 12a outputs the signal 13.

The bus registers 12a to 12h have tri-state outputs, all outputs are connected on the electronic circuit board and are connected to the data bus 7 corresponding to the node number on the system bus. For example, the bus register of the 0th node is connected to D0, and the bus register of the 4th node is connected to D4. Therefore, the output of bus register 12a appears on Dn corresponding to the node number n of system data bus 7. Since the input of the bus register 12 is fixed to the low level, the output also becomes the low level. On the other hand, since the system data bus 7 is fixed to a high level through the resistor 15 on the bus, the value of the bus register of the node not mounted with the electronic circuit board becomes a high level.

When the system data bus 7 is driven, the bus register 12 enables the response completion line 18 by the response completion circuit 14 after a fixed time. When the CPU 1 detects the completion of the response through the bus control circuit 20 and the local control bus 19, the CPU 1 takes in the signal of the system data bus 7 through the data buffer 5 and the local data bus 3 and completes the take-in operation. After that, the value of the fetched data is checked to determine whether each node is valid or invalid.

By assigning other node information to other addresses of the bus register, various node information can be obtained in the same manner. Further, since the electronic circuit board itself that accesses the bus register is provided with the bus register,
The response completion signal is always driven.

Next, the operation in which the CPU 1 at the m-th node reads the RAM 26 which is a shared resource at the n-th node will be described. The node number setting means 27 is set to a fixed value that differs for each node on the external system bus. Here, for convenience of illustration, the node number setting means 27 is shown only for the nth node, but the node number setting means 27 is also set on the motherboards of other nodes such as the mth node. . Therefore, when the electronic circuit board is mounted on one node, the node number is fixed as the number of the electronic circuit board. The shared area on the system bus is equally divided based on the value of the maximum value of the node number + 1. For example, the shared area is 80000
If there are 1 Gbytes from 000 to BFFFFFFF and the node number is 4 bits, 64 per node
M bytes are allocated. Therefore, when n = 8, the eighth node is from A0000000 to A3FFFFFF.
Will be the address of. In the following description, a system having such a condition will be taken as an example.

Shared RAM 2 with CPU 1 in the 8th node
When the address 80000000 is output to read the data of No. 6, the target address appears on the system address bus 6 via the local address bus 2 and the address buffer 4. The comparator 22 on the eighth node receives the value of the upper 6 bits on the system address bus 6 and the value obtained by adding 2 bits to the node number set in the node number setting means 27 via the address buffer 8. Are constantly compared and monitored. The comparator 22 validates the output 22a when a matching address appears.

At this time, since the CPU 1 drives the system lead wire 16 via the local control bus 19 and the bus control circuit 20, the output 24a of the OR gate 24 becomes effective, and then the output of the AND gate 25. Two
5a is effective. When the output 25a becomes valid, one of the outputs of the decoder 23 becomes valid and the shared RAM 26 to which the output is connected is selected.

The output control terminal of the shared RAM 26 is connected to the system lead wire 1 via the command buffer 9.
Since the signal 6 is input, the output data of the shared RAM 26 appears on the local data bus 3 through the buffer 28, the system data bus 7 and the data buffer 5. Further, the response completion circuit 14 drives the response completion line 18 after a certain time since the output 25a of the AND gate 25 becomes valid. When the CPU 1 detects the response completion signal via the bus control circuit 20 and the local control bus 19, it takes in the output data of the shared RAM 26 on the local data bus 3 internally. With that, a series of operations is completed. In the case of writing operation, writing is performed by the same method.

[0023]

According to the present invention, it becomes possible to automatically discriminate and automatically recognize the constituent elements and constituent states of the system. In addition, the state of the component can be recognized in real time. Further, since the address of the shared resource is provided not for the electronic circuit board but for each node, duplicate allocation will never occur.
Therefore, when changing the components of the system, it is not necessary for the operator to reset the address of the electronic circuit board, which is a shared resource, each time, and a more flexible system can be assembled quickly and reliably. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a computer system including a component recognition device according to the present invention.

[Explanation of symbols]

 1 CPU 2 local address bus 3 local data bus 4 address buffer 5 data buffer 6 system address bus 7 data bus 8 address buffer 9 command buffer 10 address decoder 11 decoder 12 bus register 13 output signal 14 response completion circuit 15 resistor 16 system read ( Read line 17 System write (write) line 18 Response completion line 19 Local control bus 20 Bus control circuit 21 AND circuit 22 Comparison circuit 23 Decoder 24 OR circuit 25 AND circuit 26 Shared RAM

Claims (3)

[Claims] 1. A computer system in which a plurality of electronic circuit boards, such as memories and I / O ports, which are arranged in each node and serve as shared resources, are interconnected by a system bus, and which are installed in each node and are unique to the node. Node information setting means having identification information, means for detecting identification information unique to the node and the state of the node via an electronic circuit board connected to each node, and the electronic circuit board connected to each node Computer system having means for recognizing identification information and status information of the computer 2. The computer system according to claim 1, wherein the state of each of the nodes to be detected is valid / invalid of each node (whether or not the electronic circuit board is connected to the node). Hardware operating state Software operating state of the electronic circuit board (watchdog timer) A computer system characterized by at least one of the errors of the electronic circuit board. 3. The computer system according to claim 1, wherein the identification information and the status information of the electronic circuit board connected to each of the nodes are an identification number and a version number of the electronic circuit board. A computer system characterized by at least one of identification number and version number of software running on the board and error information when an error occurs.