JPH0652064A - Data rewrite system and its circuit in memory circuit - Google Patents

Abstract

PURPOSE:To save the usage of memory space when an EEPROM and a ROM exist on the memory space. CONSTITUTION:The memory space 4 allocated to an EEPROM 13 for parity data storage use is arranged on the write plane of the memory space 3 allocated to the ROM 12. Thereby, the rewrite of the EEPROM 13 for parity data storage use can be performed by writing parity data on the address of the ROM 12 from a microprocessor when the parity data is changed according to the rewrite of the data in the EEPROM 11. Therefore, the memory space provided for the EEPROM 13 for parity data storage can be saved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit with memory parity, and in particular, using an EEPROM and a ROM,
The present invention relates to a memory circuit for a microprocessor peripheral circuit that stores parity data of an EEPROM and a ROM in the same EEPROM for storing parity data, and a data rewriting method.

[0002]

2. Description of the Related Art Conventionally, in a memory circuit for a microprocessor peripheral circuit, an EEPROM is used as a memory element.
(Electrically Rewritable Read-Only Memory) and ROM (Read-Only Memory)
When the storage content of M is changed, the parity data must be changed accordingly. At this time, rewriting of the EEPROM for accommodating parity data has been performed by the following two methods.

First, although there is a margin in the memory space of the microprocessor, a method of allocating an EEPROM for accommodating parity data in the memory space is the first. According to this method, an EEP for accommodating parity data
By writing new parity data in the memory space assigned to the ROM, the EEPROM for storing the parity data can be rewritten.

Second, unlike the first method, there is no space in the memory space, but a plurality of memory space planes are formed by switching banks, and parity data that is not normally connected to a microprocessor is used. EEP for accommodation
This is a method in which the ROM is connected to the microprocessor by bank switching only when the parity data is rewritten and the parity data is rewritten. According to this method, the microprocessor can rewrite the parity data accommodating EEPROM by writing new parity data to the plane and the memory space allocated to the parity data accommodating EEPROM.

[0005]

In these conventional memory circuits with memory parity, the EE for accommodating parity data is used.
When rewriting the PROM data, it is possible to rewrite when the EEPROM for storing parity data can be allocated in the memory space as in the method of the first paragraph above, but rewriting when there is no room in the memory space. Is impossible.

Further, when the EEPROM for accommodating the parity data is allocated to another surface by the bank switching as in the second method in the preceding paragraph, the bank switching operation is required before and after the parity data rewriting. If there is no margin in the number of banks to be switched, it is impossible to allocate the memory space of the EEPROM for accommodating the parity data by the second method described in the preceding paragraph.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data rewriting method in a memory circuit that saves the use of memory space, and a circuit therefor.

[0008]

In order to achieve the above object, a data rewriting method in a memory circuit according to the present invention is an EEPROM having an equal memory capacity.
(Electrically rewritable read-only memory) and RO
M (read-only memory) and these EEPRO
A data rewriting method in a memory circuit in which the same memory parity check method is used for M and ROM, and the same EEPROM for accommodating parity data is separately provided for storing these parity data, and the parity data is rewritten by a program of a microprocessor. By allocating the EEPROM for storing parity data to the writing surface of the memory space having the same address as the ROM, the memory space is switched to ROM for reading and EEPROM for storing parity data for writing, and is normally read. By writing data in the ROM space which is used only only, the storage contents of the parity data accommodation EEPROM are rewritten.

A memory circuit for implementing the data rewriting method according to the present invention is a memory circuit having a memory element and a control section, and the memory element includes a ROM (read only memory) and an EEPROM (electrical). Rewritable read-only memory) and parity data accommodation EE for accommodating parity data of ROM and EEPROM
The control unit is composed of a PROM, and receives the EEPROM selection signal and the ROM selection signal, and the memory read signal and the memory write signal from the microprocessor, and controls the reading and writing of the memory element.

[0010]

The memory space allocated to the EEPROM for storing parity data is arranged on the writing surface of the memory space allocated to the ROM.

Thus, when the parity data is changed by rewriting the data in the EEPROM, the parity data can be rewritten in the EEPROM by writing the parity data into the address of the ROM from the microprocessor. Therefore, EEPR for accommodating parity data
The memory space provided for the OM can be saved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1A is a memory space diagram of an embodiment of the present invention. The memory space 1 is a general-purpose memory space allocated to RAM (random access memory) or the like.
The allocation of the memory space 1 is not directly related to the present invention. The memory space 2 is allocated to the EEPROM. It is used for accommodating a program that will be rewritten by downloading to the microprocessor circuit from the outside, or for storing failure history data using non-volatility that allows recorded data to remain even when the power is turned off.

The memory space 3 is allocated to the ROM.
The memory space 3 has the same size as the memory space 2. Further, data is connected from the ROM of the memory space 3 to the microprocessor only when the microprocessor reads the memory. It is used for accommodating programs or data that will not be rewritten in the future.

The memory space 4 is the EEPR of the memory space 2.
It is allocated to the parity data accommodation EEPROM for accommodating the parity data of the ROM of the OM and the memory space 3. The memory space 4 has the same size as the memory space 3. The data from the microprocessor is connected to the EEPROM for storing parity data in the memory space 4 only when the microprocessor writes the memory, that is, when the parity data is rewritten. It is the memory circuit of FIG. 1B that realizes the memory space allocation of FIG.

The structure of the circuit shown in FIG. 1B is as follows. In the figure, 11 is an EEPR used for data storage.
OM, which is a memory element corresponding to the memory space 2 in FIG. 1A in the memory space of the microprocessor.
Reference numeral 12 is a ROM used for storing only read data, and is shown in FIG. 1 (A) in the memory space of the microprocessor.
The memory element corresponds to the memory space 3 of FIG. 13 is
This is an EEPROM for accommodating parity data, and in the memory space of the microprocessor, the memory space 4 of FIG.
It corresponds to the memory element. E for storing parity data
The EPROM 13 stores the parity data of the EEPROM 11 and the ROM 12. Reference numeral 14 is an OR gate element. Reference numeral 15 is an AND gate element. Reference numeral 16 denotes a memory read signal line output from the microprocessor, which has a negative logic and represents a memory read operation at the low level. 1
Reference numeral 7 denotes a memory write signal line output by the microprocessor, which has a negative logic and represents a memory write operation at a low level.

Reference numeral 18 denotes an EEPROM chip select signal output from a decoder connected to an address line from the microprocessor, which has a negative logic and is at a low level.
The operation of data-connected to the microprocessor of the EEPROM of the memory space 2 in (A) is shown. Reference numeral 19 denotes a ROM chip select signal output from the same decoder as that described above, which is a negative logic, and at a low level, ROM of the memory space 3 in FIG. 1 (A) or E of the memory space 4 in FIG. 1 (A).
EPROM represents the operation of data connection to the microprocessor. Here, in the EEPROM 11, the ROM 12 and the EEPROM 13, the three symbols CE, OE and WEN indicate the functional terminals of these memory elements shown below. CE is a chip enable terminal that activates the memory element and has a negative logic. OE is an output enable terminal that opens the gate of the data signal of the memory element, and has a negative logic. WEN is a write enable terminal that gives a holding timing when storing an address input and a data input to the memory element, and has a negative logic.

FIG. 2 is a detailed diagram of the EEPROM 13 for accommodating the parity data shown in FIG. 1 (B). Here, as an example, the EEPROM 1 for storing parity data
3, the memory capacity is 1 megabit, and the memory configuration 13
An EEPROM element of 1 kilo × 8 bits is used. In the figure, a1 to a17 are address lines from the microprocessor,
d0 to d7 are data lines from the microprocessor.

The operation of rewriting the EEPROM 13 for accommodating the parity data is as follows. When the parity data storage EEPROM 13 is rewritten by the microprocessor, the data d0 to d7 from the microprocessor are stored in the memory addresses in the parity data storage EEPROM designated by the address lines a1 to a17. However, the data d0 to d7 are added to the EEPROM 13 as data d01 to d71 via the bus drivers 21 and 22.

At the time of writing, the signal 14a connected to the gate terminals of the bus drivers 21 and 22.
Is the output of the OR gate 14 in FIG.
It is at a low level. The gates of the bus drivers 21 and 22 are open and in a signal passing state. The NAND gate elements 31 and 32 are inserted in order to obtain a delay time required as compared with the signal 14a when performing gate control of the bus drivers 21 and 22.

The operation of reading the EEPROM and ROM by the microprocessor is as follows. When the microprocessor reads the EEPROM and the ROM, the parity data storing EEPROM 13 outputs the parity data. Parity data is output from the EEPROM and the address of the EEPROM 13 corresponding to the addresses of the ROM read by the microprocessor.

In the EEPROM 13 of the present embodiment, 8-bit data can be stored for each address in terms of capacity, but the 0th bit (terminal D0) of the stored data is used for accommodating the parity data for ROM, and the 1st bit (terminal D1). Are used for accommodating parity data for the EEPROM, and only 2 bits in total out of 8 bits are used. The output of these data bits is the parity data ROM PTY and E for ROM.
The parity data EPEPTY for EPROM is output from this circuit to the parity check circuit.

In the bus drivers 21 and 22, the terminal G is at a high level and the gate is closed when reading the EEPROM and ROM by the microprocessor, so that the data lines d0 and d01 and d1 and d11 which are in the input / output relation. Are isolated and data from the microprocessor is never output as parity data ROMPTY and EEPPTY. Further, the connection of the data line to the EEPROM for accommodating the parity data is connected to 8 bits for 8 bits of d01 to d71 despite the fact that the output is 2 bits. This is because instructions such as erasing, erasing stop, and reset are performed as data line 8-bit data.

FIG. 3 shows bit allocation in each memory element in the case of the example of FIG. As an example,
8000 of the memory space of the microprocessor
0 from the _H to BFFFF _H to EEPROM11, C0
Read-out surface from 000 _H to FFFFF _H is ROM1
2. The writing surfaces from C0000 _H to FFFFF _H are allocated to the parity data accommodation EEPROM 13 respectively. At this time, the method of accommodating the parity data is as follows.

The parity data of the EEPROM 11 is stored in the first bit of the parity data storing EEPROM 13.

As shown in FIG. 3, the parity data X _0P corresponding to the 8-bit data X _{0 at} the address 80000 _H of the EEPROM 11 is the parity data accommodation EEPROM.
It is stored in the first bit of the address C0000 _H of 13. Similarly, 8-bit data X at address 80001 _H
The parity data X _1P for 1 is stored in the first bit of the address C0001 _H of the EEPROM ₁₃ for storing parity data. Similarly, the address BFFFF _H
Parity data X _LP for 8-bit data X _L of
Address FF of EEPROM 13 for storing parity data
It is stored in the first bit of FFF _H.

Regarding the parity data of the ROM 12,
It is stored in the 0th bit of the EEPROM 13 for storing parity data. As shown in FIG. 3, the parity data Y _0P for the 8-bit data Y _{0 at} the address C0000 _H of the ROM 12 is stored in the 0th bit of the address C0000 _H of the EEPROM 13 for storing parity data.
Similarly, the parity data Y _1P for the 8-bit data Y ₁ of the address C0001 _H is the EE for accommodating the parity data.
It is stored in the 0th bit of the address C0001 _H of the PROM 13.

The parity data Y _LP for 8-bit data Y _L follows similarly address FFFFF _H, the address of the parity data containment EEPROM 13 FFFFF _H
Stored in the first bit of.

An example of using this memory circuit is shown in the functional block diagrams of FIGS. 4 and 5. FIG. 4 shows an example of use of the present memory circuit and shows a data flow when the microprocessor rewrites data in the EEPROM.

When rewriting the data in the EEPROM, first, as shown in FIG. 4A, the data 41a from the microprocessor 41 is input to the EEPROM 11 to
The data in the ROM 11 is changed. Next, this EEPR
Since it is necessary to change the parity data when the data in the OM 11 is rewritten, as shown in FIG.
By inputting the data 41a to 3, the change of the parity data due to the main rewriting is executed.

The memory space to be rewritten is the same address space as the ROM as shown in FIG. 1A, but it is not automatically the ROM but the parity data storage E.
Data is input to the EPROM 13 to realize rewriting of parity data. The generation of the parity data at this time is provided by a calculation by a microprocessor or a parity data generation device connected to the outside of the microprocessor 41. Since the ROM 12 is a memory element that can only output stored data, the data in the ROM 12 cannot be rewritten, and the parity data need not be rewritten as in the case of rewriting the EEPROM 11.

FIG. 5 shows an example of use of this memory circuit and shows a data flow when data is read from the EEPROM and the ROM by the microprocessor. EEP
At the time of reading data from the ROM, the output of the read data 11a from the EEPROM 11 is added to the microprocessor 51, as shown in FIG. Further, the parity data 13 corresponding to the read data 11a
a is simultaneously output from the EEPROM 13 for accommodating the parity data and added to the parity check circuit 52.

In the parity check circuit 52, the read data 11a is calculated and compared with the parity data 13a to check whether or not a memory parity error has occurred. When it is detected that a memory parity error has occurred, the microprocessor 51 is generally notified using the interrupt notification line 8.

When reading the data from the ROM, FIG.
As shown in (B), the output of the read data 12a from the ROM 12 is added to the microprocessor 51. Further, the parity data 13a corresponding to the read data 12a is the EEPROM 1 for accommodating the parity data.
3 are simultaneously output and added to the parity check circuit 52 and the microprocessor 51.

In the parity check circuit 52, the read data 12a is calculated and compared with the parity data 13a to check whether or not a memory parity error has occurred. When it is detected that a memory parity error has occurred, the microprocessor 51 is generally notified using the interrupt notification line 8.

[0035]

As described above, according to the present invention, an EEPROM for storing parity data can be allocated in the memory space regardless of the lack of the surface and the memory space.
In addition, the bank switching operation is not necessary before and after the parity data rewriting.

[Brief description of drawings]

FIG. 1A is a memory space diagram in one embodiment of the present invention, and FIG. 1B is a circuit diagram for realizing the memory space allocation shown in FIG.

FIG. 2 is a detailed diagram of an EEPROM peripheral circuit for parity.

FIG. 3 is a diagram showing an example of bit allocation in each memory element.

FIG. 4 is an embodiment of memory rewriting in the case of the present invention, (A) is a block diagram showing a connection when rewriting EEPROM data which is a first step, and (B) is parity data which is a second step. It is a block diagram showing the connection at the time of rewriting.

5A and 5B are embodiments of memory reading according to the present invention, FIG. 5A is a block diagram showing a connection at the time of reading EEPROM data, and FIG. 5B is a block diagram showing a connection at the time of reading ROM data. .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 General-purpose memory space 2 EEPROM memory space 3 ROM memory space 4 Parity data accommodation EEPROM memory space 11 EEPROM 12 ROM 13 Parity data accommodation EEPROM 14 OR gate element 15 AND gate element 16, 17 Memory read signal 18, 19 chips Select signal 21,22 Bus driver 31,32 NAND gate element 41,51 Microprocessor 52 Parity check circuit

Claims (2)

[Claims] 1. An EEP having an equal memory capacity.
ROM (electrically rewritable read-only memory)
And a ROM (read-only memory)
A data rewriting method in a memory circuit in which the same memory parity check method is used for PROM and ROM, and the same parity data accommodating EEPROM is separately provided for storing these parity data, and the parity data is rewritten by a program of a microprocessor. By allocating the EEPROM for storing the parity data to the writing surface of the memory space having the same address as the ROM, the memory space is switched to the ROM for reading and the EEPROM for storing the parity data during writing, and is normally read. A data rewriting method in a memory circuit, characterized in that the data stored in the EEPROM for storing parity data is rewritten by writing data in a ROM space that is used only for this purpose. 2. A memory circuit having a memory element and a controller, wherein the memory element is a ROM (read only memory) and an EE.
A PROM (electrically rewritable read-only memory) and an EEPROM for storing parity data of ROM and EEPROM are provided. The control unit has an EEPROM selection signal and a ROM selection signal, and a microprocessor A memory circuit, which receives a memory read signal and a memory write signal and controls reading and writing of a memory element.