JPH0481954A - Memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory device with an improved parity check function.

(Prior Art) A system using an MPU (microprocessor) has a main memory that stores programs and data to be executed by the MPU.

A semiconductor memory is generally used as this main memory.

Generally, a parity check is performed by adding a parity bit so that it can be checked whether there are any errors in the information stored in the memory.

Therefore, a memory for parity bits is provided.

Normally, one bit is used for the parity bit, and the parity bit is set for each address so that the sum of the contents of all bits in the data stored at that address and the value of the parity bit is an even or odd number. When loading or saving data, add the data bit values including the parity bit for each address, and determine whether there is an error in the data by determining whether the result is an even or odd number. Make sure to check.

A parity check circuit performs such a parity check, and a memory circuit that stores programs, data, etc. in a read-only memory (ROM) also stores the parity bit data of this memory. The parity memory for this purpose will be constituted by ROM.

However, since ROM is composed of multiple bits per address, such as in bytes, parity memory composed of ROM uses only one bit per address, so the usage efficiency per address is low. It's bad and extremely uneconomical.

(Problem to be solved by the invention: s problem> In a memory circuit using a ROM that includes a parity bit, a ROM for storing programs and data and a ROM for storing the parity bit are used. However, the ROM Since each address is made up of multiple bits, such as byte units, parity memory made up of ROM has poor utilization efficiency per address, considering that only one bit is used for each address. It is uneconomical.

In this way, the parity ROM has a configuration of multiple bits per address, but since only one bit of the multiple bits is used, not only does the ROM usage efficiency become low, but the parity ROM has a low usage efficiency. must be mounted, which is inefficient from the standpoint of board mounting and increases costs.

Therefore, the purpose of this invention is to
In a memory device using OM, parity ROM
It is an object of the present invention to provide a memory device which is capable of increasing usage efficiency of memory devices, thereby improving mounting efficiency on a board, and reducing costs.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention is configured as follows. That is, first, a memory composed of multiple bits per address is used as a memory for parity bits, and is used in conjunction with a data memory for storing programs, data, etc., when accessing the data memory. In a memory device capable of performing a parity check on the stored information contents of an accessed memory address, the parity bit memory includes a bit position determined according to the accessed memory address in the memory address to be accessed. and a selection means for selectively outputting data at a bit position determined according to address information for accessing the data memory from the parity bit memory. At the same time, a parity check is performed from the output data of this selection means and the read data of the data memory.

Second, a memory composed of multiple bits per address is used as a parity bit memory, and is used in conjunction with a data memory for storing programs, data, etc. when accessing this data memory. A memory device capable of performing a parity check on stored information contents of an accessed memory address, comprising: a parity generating means for generating a parity bit from read data of the data memory; a selection means for selectively outputting data at a bit position determined according to address information from the parity bit memory; and a selection means for comparing the output data of the selection means with the data generated by the parity generation means to determine coincidence/mismatch. and determining means for outputting a parity check determination result, and the parity bit memory stores parity information for the storage information content of the accessed memory address at a bit position determined according to the accessed memory address. It is characterized by being stored.

(Function) In the first configuration, this device with such a configuration uses a memory composed of multiple bits per address as a parity bit memory, and a data memory for storing programs, data, etc. When this data memory is accessed, a parity check is performed on the stored information content of the accessed memory address, and the parity bit memory contains a bit determined according to the accessed memory address. parity information for the storage information content of the memory address to be accessed is stored in the position, and the selection means selects the data at the bit position determined according to the address information for accessing the data memory to the parity. Select and output from bit memory. Then, a parity check is performed from the output data of this selection means and the read data of the data memory.

Therefore, when using a parity memory that consists of multiple bits per address, the parity bit for the data memory that is larger than the address space of the parity memory must be assigned to the address using the bit assignment of the parity memory. To reduce the amount of parity memory, that is, when a memory in which one address consists of multiple bits is used as parity memory, a different address is assigned to each data bit of that memory, and a selection means is used to correspond to the access address. It is possible to select and extract data at a bit position, obtain the parity bit of the corresponding address, and perform a parity check, and each different bit of one address can be used to store the parity bit of a memory for different data. In addition to improving the usage efficiency of parity bit memory, the memory for parity bits has a much smaller capacity than the address space occupied by data memory. Therefore, since the parity bit memory can occupy less space when mounted on a board, costs can be reduced.

Furthermore, in the second configuration, a memory composed of multiple bits per address is used as a memory for parity bits, and the information stored in this memory for parity bits is as follows:
When this data memory is accessed in conjunction with a data memory that stores programs, data, etc., it is used to check the parity of the information stored at the accessed memory address.In this system, memory access is When this is done, the parity generating means generates a parity bit from the read data of the data memory.

At the same time, the selection means selects and outputs data at a bit position determined according to the address information for accessing the data memory from the parity bit memory, and combines the output data of the selection means with the parity generation. The data generated by the means is input to the determining means, where the two are compared and a match/mismatch is determined. Then, the determining means outputs a parity check determination result according to the result.

Since the selection means has a function of selecting and outputting data at a bit position determined according to address information for accessing the data memory from the parity bit memory, the parity bit memory includes: By storing parity information for the storage information content of the memory address to be accessed in a bit position determined according to the memory address to be accessed, the selection bit position at that address can be made different for different memory addresses. Therefore, the parity bit memory can be filled with a memory whose address space is smaller than the address space of the data memory.

For example, an 8-bit memory can handle the parity data of a data memory that has eight times the address space, and a 4-bit memory can handle the parity data of a data memory that has four times the address space. Can handle parity data. Therefore, it is only necessary to have a memory for parity bits that has a much smaller address space than memory for data, which reduces the mounting space on the board. Especially in memory devices that have increased in capacity,
Significant cost reductions can be achieved.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In the figure, 12.
13 is tiAl and a second data ROM, the former having an address space from address 0 to (s-1),
Programs and data are stored, and the latter is the address layer ~ (
It has an address space up to n-1), and programs and data are stored therein. Here, to make the story easier to understand, 0
The address space size of ~(s-1) and -~(n-1
) are assumed to have the same absolute value. For example, both are hexadecimal numbers such as FFFF.

21 is a parity bit ROM (PB-ROM), and for the sake of clarity, this also has an address space similar to that of the first and second data ROMs 12. Use one that can ensure at least the same size as 1B.

Therefore, the first and second data ROMs 12. 1
If the address space of No. 3 is FPFP, then the parity bit ROM 21 should similarly be one that can secure the address space of FFFF.

Parity bits 126 and 217 correspond to the first and second data ROMs 12 and 13, respectively, and are stored in one parity bit ROM 21. Here, as shown in the figure, the parity bit of the data ROM 12 is set to the seventh bit of the parity bit ROM 21.
The parity bit of the data ROM 13 is placed at the 6th bit of the parity bit ROM 21, and the parity bit of the data ROM 12 is placed at the 6th bit of the parity bit ROM 21, thereby using different bits among the constituent bits of one address. In order to make effective use of the data, a parity bit is placed in the memory, and unused bits are eliminated as much as possible.

Then, to use the parity bit, R for data
When OM12 is the selected address area, the 7th bit parity bit 126 of parity bit ROM 21 is selected and used, and when data ROM 13 is the selected address area, the parity bit R is selected and used.
The sixth parity bit 127 of OM21 is selected and used.

Conventionally, data ROMs 12 and 13 have different address spaces.
parity bit 1 shown in Figure 1.
26, 217, one parity bit RO
Although it was not possible to store the parity bits in the M21, the present invention improves the usage efficiency of the parity bit ROM 21 by using different bits of one address to store parity bits of different data ROMs. .

The principle of the present invention has been described above, and a specific example of the circuit when actually used as hardware will be described next.

Here, the first and second data ROMs 12°13
An example will be explained in which the parity bit ROM 21 has the same capacity as 8 buttes/addresses.

FIG. 2 shows an embodiment of the present invention, in which reference numeral 31 is a parity generation section, which generates parity bits from data read from the data ROMs 12 and 13. 32 is a selector for parity bits, and the selector 32 selects the bit to be referenced based on the upper address information from among the address information supplied by the address bus 41, and selects the selected bit from among the output data of the ROM 21 for parity bits. Extract and output the information of the bits.

33 is a comparator which compares the generated parity data 45 outputted by the parity generation unit 31 and the selected extracted parity bit data 44 outputted by the selector 32, and if they match, there is no error, and if they do not match, there is no error. It outputs the parity check result 4B.

The address bus 41 is used to input address information, and the address information is supplied by a CPU (not shown). 42 is a data bus, 43 is ROM2 for parity bit
1, 44 is the parity bit data selected and extracted by the selector 32, 45 is the generated parity bit data generated by the parity generator 31, and 46 is the parity check result by the comparator 33. The following data is shown.

In such a configuration, data ROM 12°13
As shown in FIG. 1, the parity bit corresponding to the parity bit is written and mounted in the parity bit ROM 21.

The address information supplied by the address bus 41 is sent to data ROMs 12 and 18 and parity bit ROMs 12 and 18.
21 and selector 32, the one assigned to the address corresponding to the address information is selected, and the data in the assigned address is read out.

Here, of the address information supplied by the address bus 41, the selector 32 selects the bit to be referenced based on the upper address information, and selects the bit to be referenced from the parity bit ROM 21.
Out of the output data, the information of the selected bit is extracted and output.

For example, if the upper address information corresponds to the allocated address of the data ROM 12, the data ROM 12
The 7th bit data in which 12 parity bits are stored is selected and output to the comparator 33, and if the upper address information corresponds to the allocated address of the data ROM 13, the data ROM 13 is selected and outputted to the comparator 33. The data of the sixth bit in which the parity bit of is stored is selected and outputted to the comparator 33.

Therefore, even if the output of the parity bit ROM 21 corresponds to the lower address, which is the common address of the data ROMs 12 and 13, the selector 32
Now, the parity bit corresponding to the address actually designated is selected and input to the comparator 33.

On the other hand, the data ROM 12 or device 3 specified by the address information supplied by the address bus 41 is connected to the data bus 41.
Based on the data output above, the parity generation unit 31 generates a parity bit, and sends this to the comparator 33 as generated parity data 45. The comparator 33 compares this generated parity data 45 with the parity bit data 44 of 21, and if they match, there is no error, and
If they do not match, an erroneous parity check result 46 is output.

This allows the ROM parity to be checked.

In this way, this device uses a memory composed of multiple bits per address as a memory for parity bits, and uses it in conjunction with a data memory for storing programs, data, etc. when accessing this data memory. A memory device capable of performing a parity check on information stored in a memory address stored in the data memory, comprising: a parity generating means for generating a parity check from read data of the data memory; and an address for accessing the data memory. a selection means for selectively outputting data at a bit position determined according to the information from the parity bit memory; and comparing the output data of the selection means and the data generated by the parity generation means to determine whether they match or do not match; and determining means for outputting a parity check determination result, and the parity bit memory stores parity information corresponding to the storage information content of the accessed memory address at a bit position determined according to the accessed memory address. This is how it was done.

This device with such a configuration uses a memory composed of multiple bits per address as a memory for parity bits, and the storage information of this memory for parity bits is data that stores programs, data, etc. When this data memory is accessed, it is used in conjunction with the data memory to check the parity of the information stored at the accessed memory address.In this system, when the memory is accessed, the parity generation means A parity bit is generated from read data of the data memory, and the selection means selects data at a bit position determined according to address information for accessing the data memory from the parity bit memory. The output data of the selection means and the data generated by the parity generation means are input to a determination means and compared, and a parity check is performed by determining whether they match or do not match.

In this way, the selection means has a function of selecting and outputting data at a bit position determined according to address information for accessing the data memory from the parity bit memory. When parity information for the storage information content of the memory address to be accessed is stored in a bit position determined according to the memory address to be accessed, the selected bit position at that address is stored in the memory for a different memory address. Since the parity bit memory can be made different, a memory with an address space smaller than that of the data memory can serve as the parity bit memory. For example, 8
If it is a bit-structured memory, it can handle parity data of a data memory that has eight times the address space.
A memory with a 4-bit configuration can handle parity data in a data memory that has four times the address space.

Therefore, according to this method, it is only necessary to have a memory for parity bits that has a much smaller address space than memory for data, which can reduce the mounting space on the board, and the memory for parity bits can improve memory usage efficiency. It can be made more expensive and there is no waste, especially in memory devices with increased capacity.
Significant cost reductions can be achieved.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with appropriate modifications within the scope of the gist thereof.For example, in the above embodiments, the data memory Although a parity generation means for generating parity from read data is provided, it is also possible to obtain parity by adding the read data of the data memory and the extracted output from the selection means (selector) without providing the parity generation means. It is also possible to use a method that performs a parity check.

Further, although the explanation has been given using a ROM as an example, the concept of the present invention can be applied as is to SRAM (static RAM), DRAM, etc., if only a memory element having a plurality of bits can be used.

[Effects of the Invention] As described in detail above, according to the present invention, when using a parity bit memory having a plurality of bits, each different bit of one address is connected to the parity bit of each different data memory element. Q used for storage can improve the usage efficiency of the parity bit memory element, and by increasing the usage efficiency of the parity bit memory element, the capacity is much smaller than the address space occupied by the data memory element. Therefore, the parity bit memory element can occupy less space when mounted on a board, so it is possible to provide a memory device with excellent features such as cost reduction. can.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the present invention in detail, and FIG. 2 is a block diagram showing an embodiment of the present invention. 12.13... ROM for data. 21...ROM for parity bit. 31... Parity generation unit, 32... Selector, 33
···comparator. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) A memory composed of multiple bits per address is used as a memory for parity bits, and when this data memory is accessed in conjunction with a data memory that stores programs, data, etc., the accessed memory address In a memory device capable of performing a parity check of the stored information contents, the parity bit memory stores the stored information of the memory address to be accessed at a bit position determined according to the memory address to be accessed. It is configured to store parity information for the content, and further includes a selection means for selectively outputting data at a bit position determined according to address information for accessing the data memory from the parity bit memory, A memory device characterized in that a parity check is performed from the output data of the selection means and the read data of the data memory. (2) A memory composed of multiple bits per address is used as a memory for parity bits, and when this data memory is accessed, the accessed memory address is used in conjunction with a data memory that stores programs, data, etc. A memory device capable of performing a parity check on stored information contents, comprising: parity generation means for generating a parity bit from read data of the data memory; and address information for accessing the data memory. a selection means for selectively outputting data at a bit position determined according to the parity bit memory from the parity bit memory; and determining means for outputting a check check result, and the parity bit memory stores parity information for the storage information content of the accessed memory address at a bit position determined according to the accessed memory address. A memory device characterized by: