JPH0652127A - Identification system for processor function type - Google Patents

Identification system for processor function type

Info

Publication number
JPH0652127A
JPH0652127A JP20766392A JP20766392A JPH0652127A JP H0652127 A JPH0652127 A JP H0652127A JP 20766392 A JP20766392 A JP 20766392A JP 20766392 A JP20766392 A JP 20766392A JP H0652127 A JPH0652127 A JP H0652127A
Authority
JP
Japan
Prior art keywords
processor
function module
identification value
processors
bus interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20766392A
Other languages
Japanese (ja)
Inventor
Yoshio Suzuki
義夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20766392A priority Critical patent/JPH0652127A/en
Publication of JPH0652127A publication Critical patent/JPH0652127A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To reduce generation manhours at the time of developing a program and maintenance manhours after development with only one file for a whole system by selecting a corresponding function module-only table in accordance with an identification value showing a function module so as to obtain a device access address concerned. CONSTITUTION:Processors Pa and Pb are connected by an inter-processor bus Ba and the processor Pa and respective devices Da-Db are connected by an intra-processor bus Bb1 via a common bus interface device B1. The processor PB and respective devices Dc-Dd are connected by an intra-processor bus Bb2 via the common bus interface device B1. The respective processors Pa and Pb transmit a request signal for reading a function module type to the common bus interface device B1 by an initialization processing at start time and obtains the identification value showing the function module by the response signal. The device access addresses of the respective devices in the processors are extracted by using the function module identification value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はシステムをマルチプロセ
ッサで構成し、各々のプロセッサを複数の機能に分割す
るファンクションシェア型システムにおいて、その機能
種別を識別するプロセッサ機能種別識別方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor function type identification system for identifying the function type in a function share type system in which the system is composed of multiprocessors and each processor is divided into a plurality of functions.

【0002】[0002]

【従来の技術】従来、この種の識別では、各機能単位で
ロードモジュール(以下LMと称す)と呼ばれるファイ
ルを別々に作成し、その中の局データの内容に機能を示
す識別値を変える事により識別していた。
2. Description of the Related Art Conventionally, in this type of identification, a file called a load module (hereinafter referred to as LM) is separately created for each functional unit, and the identification value indicating the function is changed in the contents of the station data in the file. Was identified by.

【0003】[0003]

【発明が解決しようとする課題】従来の方式では、LM
の作成数が機能種別数分必要となり、プログラムを開発
する時の作業工数を増大させるばかりでなく、開発後の
保守を行う時にもLM種別数に応じたファイル版数管理
が必要になり、保守工数も増大させる要因となってい
る。
In the conventional method, the LM
The number of created files is the same as the number of function types, which not only increases the work man-hours when developing a program, but also requires the file version number management according to the number of LM types when performing maintenance after development. This is also a factor that increases man-hours.

【0004】[0004]

【課題を解決するための手段】本発明のプロセッサ機能
種別式別方式は、機能分割されたマルチプロセッサによ
り構成されるシステムにおいて、前記マルチプロセッサ
のうちの各々のプロセッサは、自プロセッサが起動開始
したときの初期設定処理で、機能モジュール種別を読み
出すための要求信号を前記プロセッサと各装置間を接続
する共通バスインタフェースへ送信し、この要求信号に
対する応答信号により機能モジュールを示す識別値を得
る構成であり、前記機能モジュールを示す識別値に従
い、対応する機能モジュール専用のテーブルを選択し、
該当の装置アクセスアドレスを得る構成である。
According to the processor function type-based method of the present invention, in a system composed of function-divided multiprocessors, each of the multiprocessors is started by its own processor. In the initial setting process, the request signal for reading the functional module type is transmitted to the common bus interface connecting the processor and each device, and the identification value indicating the functional module is obtained by the response signal to the request signal. Yes, according to the identification value indicating the functional module, select the table dedicated to the corresponding functional module,
The configuration is such that the corresponding device access address is obtained.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0006】図1aは本発明の一実施例を説明するため
のマルチプロセッサで構成される局用交換機の構成図で
ある。プロセッサPa,Pbがプロセッサ間バスBaで
接続されており、プロセッサPaと各装置(例えば、汎
用IO装置,専用SP系装置)Da〜Db間は共通バス
インタフェース装置BI経由でのプロセッサ内バスBb
1で接続されている。同じようにプロセッサPbも各装
置Dc〜Dd間は共通バスインタフェース装置BI経由
でのプロセッサ内バスBb2で接続されている。
FIG. 1a is a block diagram of a central office switch composed of a multiprocessor for explaining an embodiment of the present invention. The processors Pa and Pb are connected by an inter-processor bus Ba, and the processor Pa and each device (for example, general-purpose IO device, dedicated SP system device) Da to Db are connected to the in-processor bus Bb via the common bus interface device BI.
1 is connected. Similarly, in the processor Pb, the devices Dc to Dd are also connected by the in-processor bus Bb2 via the common bus interface device BI.

【0007】各装置は各機能モジュール別に異なってい
る点に着目し、プロセッサPa,Pbに、全ての機能モ
ジュールにおいて共通な読みだし方法により、各装置か
ら機能モジュールを識別する値を読み出せる機能を新設
する。
Paying attention to the fact that each device is different for each functional module, the processor Pa, Pb has a function capable of reading a value for identifying the functional module from each device by a reading method common to all the functional modules. Build a new one.

【0008】図1(b)は(a)におけるプロセッサと
プロセッサ内共通バスインタフェース間での機能モジュ
ール識別値を読み出すときの信号のシーケンス図であ
る。各プロセッサPa,Pbは自分自身が起動開始した
時の初期設定処理で、機能モジュール種別を読み出すた
めの要求信号を共通バスインタフェース装置BIへ送信
し、その応答信号により機能モジュールを示す識別値X
を得る。
FIG. 1B is a sequence diagram of signals for reading the functional module identification value between the processor and the common bus interface in the processor in FIG. Each of the processors Pa and Pb sends a request signal for reading the functional module type to the common bus interface device BI in the initialization process when the processor itself starts to start, and an identification value X indicating the functional module is sent by the response signal.
To get

【0009】図2は全機能モジュールを統合した局デー
タの一実施例を示す図であり、図1(b)で得た機能モ
ジュール識別値Xを利用してプロセッサ内の各装置の装
置アクセスアドレスを抽出する。例えば、図1(a)の
装置Daと装置Dcは共に磁気テープ(MT)装置であ
るが、プロセッサPa内での装置アクセスアドレスはI
OA1,プロセッサPbの時にはIOA3といった違っ
た値でアクセスしなければならないケースの時に使用す
る。
FIG. 2 is a diagram showing an embodiment of station data in which all functional modules are integrated. The functional module identification value X obtained in FIG. 1B is used to access the device access address of each device in the processor. To extract. For example, both the device Da and the device Dc in FIG. 1A are magnetic tape (MT) devices, but the device access address in the processor Pa is I.
It is used when OA1 and processor Pb need to be accessed with different values such as IOA3.

【0010】MT装置アクセスプログラムでは、MT装
置へアクセスする場合に先頭テーブルを識別値Xで索引
し、自機能モジュール専用の子テーブルを選択し、この
選択したテーブルにおいて、MT装置を示す装置名値で
索引することによりプロセッサPaの時にはIOA1、
プロセッサPbの時にはIOA3を得ることが出来る。
In the MT device access program, when the MT device is accessed, the head table is indexed by the identification value X, the child table dedicated to the own function module is selected, and the device name value indicating the MT device is selected in the selected table. By indexing with IOA1 for processor Pa,
When the processor is Pb, IOA3 can be obtained.

【0011】[0011]

【発明の効果】以上説明したように本発明は、各機能単
位でロードモジュールのファイルを別々に作成する必要
がなくなり、システム全体で1本のファイルでよく、プ
ログラムを開発する時の作成工数及び開発後の保守工数
を削減することができるという効果を有する。
As described above, according to the present invention, it is not necessary to separately create a load module file for each function unit, and only one file is required for the entire system. This has the effect of reducing maintenance man-hours after development.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明一実施例を説明するためのマル
チプロセッサ構成による局用交換機の構成図である。
(b)は(a)におけるプロセッサとプロセッサ内共通
バスインタフェース間での機能モジュール識別値を読み
出すときの信号のシーケンス図である。
FIG. 1A is a configuration diagram of a central office switching system having a multiprocessor configuration for explaining an embodiment of the present invention.
(B) is a sequence diagram of signals when reading the functional module identification value between the processor and the common bus interface in the processor in (a).

【図2】全機能モジュールを統合した局データの一実施
例を示す図である。
FIG. 2 is a diagram showing an example of station data in which all functional modules are integrated.

【符号の説明】[Explanation of symbols]

Ba プロセッサ間バス Bb1,Bb2 プロセッサ内バス BI 共通バスインタフェース装置 Da〜Dd 装置 IOA1〜IOA4 装置アクセスアドレス値 Pa,Pb プロセッサ X 識別値 Ba inter-processor bus Bb1, Bb2 intra-processor bus BI common bus interface device Da to Dd device IOA1 to IOA4 device access address value Pa, Pb processor X identification value

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 機能分割されたマルチプロセッサにより
構成されるシステムにおいて、前記マルチプロセッサの
うちの各々のプロセッサは、自プロセッサが起動開始し
たときの初期設定処理で、機能モジュール種別を読み出
すための要求信号を前記プロセッサと各装置間を接続す
る共通バスインタフェースへ送信し、この要求信号に対
する応答信号により機能モジュールを示す識別値を得る
ことを特徴とするプロセッサ機能種別識別方式。
1. In a system composed of multi-processors divided into functions, each processor of the multi-processors is a request for reading out a functional module type in an initialization process when its own processor is started. A processor function type identification method characterized in that a signal is transmitted to a common bus interface connecting the processor and each device, and an identification value indicating a functional module is obtained by a response signal to the request signal.
【請求項2】 前記機能モジュールを示す識別値に従
い、対応する機能モジュール専用のテーブルを選択し、
該当の装置アクセスアドレスを得ることを特徴とする請
求項1記載のプロセッサ機能種別識別方式。
2. A table dedicated to the corresponding function module is selected according to the identification value indicating the function module,
2. The processor function type identification method according to claim 1, wherein a corresponding device access address is obtained.
JP20766392A 1992-08-04 1992-08-04 Identification system for processor function type Pending JPH0652127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20766392A JPH0652127A (en) 1992-08-04 1992-08-04 Identification system for processor function type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20766392A JPH0652127A (en) 1992-08-04 1992-08-04 Identification system for processor function type

Publications (1)

Publication Number Publication Date
JPH0652127A true JPH0652127A (en) 1994-02-25

Family

ID=16543500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20766392A Pending JPH0652127A (en) 1992-08-04 1992-08-04 Identification system for processor function type

Country Status (1)

Country Link
JP (1) JPH0652127A (en)

Similar Documents

Publication Publication Date Title
US3716837A (en) Interrupt handling
JPH0652127A (en) Identification system for processor function type
JPS6325384B2 (en)
KR920008602A (en) Computer system with multiple input / output devices sharing address space and communication management method between input / output device and processor
JPH03265945A (en) Data sharing system for operating systems of different types
JPH08272754A (en) Multiprocessor system
JP2576934B2 (en) Memory-mapped interrupt method
JPS6146552A (en) Information processor
JPS58200363A (en) Input and output control system of virtual system
JPS61269545A (en) computer system
JPH03100853A (en) Inter-processor communication system
JP2785855B2 (en) Information processing device
JPS61273653A (en) Electronic computer
JPH05257831A (en) Input/output processor
JPS6221139B2 (en)
JPS59106060A (en) Data logging system
JPS6152768A (en) Interrupt control mechanism for multiprocessor systems
JPS605541U (en) multiprocessor calculator
JPS63284652A (en) Patrol diagnosis system for shared memory
JPS638501B2 (en)
JPS63296161A (en) System for controlling virtual common memory device
JPS61260345A (en) Bus control system among multiprocessors
JPS5815815B2 (en) Common information management method
JPH07210466A (en) Virtual computer system
JPH052505A (en) Computer system test support method

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19990406