JPH0653236A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0653236A JPH0653236A JP20281692A JP20281692A JPH0653236A JP H0653236 A JPH0653236 A JP H0653236A JP 20281692 A JP20281692 A JP 20281692A JP 20281692 A JP20281692 A JP 20281692A JP H0653236 A JPH0653236 A JP H0653236A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- type
- gate electrode
- layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract 2
- 239000002184 metal Substances 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims description 7
- 239000003870 refractory metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010936 titanium Substances 0.000 abstract description 9
- 229910052719 titanium Inorganic materials 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000000137 annealing Methods 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にサリサイド（ｓｅｌｆ−ａｌｉｇｎｅｄ ｓ
ｉｌｉｃｉｄｅ）構造のゲート電極を有するＭＯＳＦＥ
Ｔの製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to salicide (self-aligned s).
MOSFE having a gate electrode having a structure
The present invention relates to a method of manufacturing T.
【０００２】[0002]
【従来の技術】従来のサリサイド構造のゲート電極を有
するＭＯＳＦＥＴの製造方法について、図３（ａ）〜
（ｃ）を参照して説明する。2. Description of the Related Art A conventional method of manufacturing a MOSFET having a salicide structure gate electrode will be described with reference to FIGS.
This will be described with reference to (c).
【０００３】はじめに図３（ａ）に示すように、Ｐ型シ
リコン基板１にＬＯＣＯＳ法によりフィールド酸化膜２
を形成したのちゲート酸化膜３を形成する。つぎに厚さ
４００ｎｍのポリシリコンを堆積したのち、燐を拡散し
てからパターニングして濃度１×１０19ｃｍ-3のＮ型ポ
リシリコン４を形成する。つぎに燐を加速エネルギー３
０ｋｅＶで注入量（ドース）３×１０13ｃｍ-2イオン注
入して、Ｎ型ＬＤＤ層６を形成する。つぎにＣＶＤ法に
より厚さ２００ｎｍの酸化シリコン膜を堆積したのち、
エッチバックしてゲート電極４側面に側壁（サイドウォ
ール）８を形成する。つぎにスパッタ法により厚さ１０
０ｎｍのチタン９を堆積する。First, as shown in FIG. 3A, a field oxide film 2 is formed on a P-type silicon substrate 1 by the LOCOS method.
Then, the gate oxide film 3 is formed. Next, after depositing polysilicon having a thickness of 400 nm, phosphorus is diffused and then patterned to form N-type polysilicon 4 having a concentration of 1 × 10 19 cm −3 . Next, phosphorus is accelerated energy 3
An implantation amount (dose) of 3 × 10 13 cm −2 ions is implanted at 0 keV to form the N-type LDD layer 6. Next, after depositing a 200 nm-thick silicon oxide film by the CVD method,
Etch back is performed to form a side wall 8 on the side surface of the gate electrode 4. Next, a thickness of 10 is obtained by the sputtering method.
Deposit 0 nm of titanium 9.
【０００４】つぎに図３（ｂ）に示すように、６５０℃
の窒素雰囲気でアニール（熱処理）してＮ型ポリシリコ
ン４上面およびＮ型ＬＤＤ層６上面にチタンシリサイド
１０ａ，１０ｂ，１０ｃを形成して、Ｎ型ポリシリコン
４およびチタンシリサイド１０ａからなるゲート電極を
形成する。つぎに未反応のチタン９を除去する。Next, as shown in FIG. 3 (b), 650 ° C.
By annealing (heat treatment) in the nitrogen atmosphere to form titanium silicides 10a, 10b and 10c on the upper surface of the N-type polysilicon 4 and the upper surface of the N-type LDD layer 6 to form a gate electrode composed of the N-type polysilicon 4 and the titanium silicide 10a. Form. Next, the unreacted titanium 9 is removed.
【０００５】つぎに図３（ｃ）に示すように、砒素を加
速エネルギー７０ｋｅＶで注入量（ドース）５×１０15
ｃｍ-2イオン注入してＮ+ 型ソース・ドレイン１１を形
成する。つぎに層間絶縁膜１２を堆積したのち、コンタ
クトを開口してからアルミニウム配線１３を形成してＭ
ＯＳＦＥＴの素子部が完成する。Next, as shown in FIG. 3 (c), arsenic is implanted at an acceleration energy of 70 keV (dose) 5 × 10 15.
cm −2 ions are implanted to form N + type source / drain 11. Next, after depositing the interlayer insulating film 12, the contact is opened and then the aluminum wiring 13 is formed to form M.
The element part of the OSFET is completed.
【０００６】[0006]
【発明が解決しようとする課題】従来のサリサイドプロ
セスにおいて、図３（ａ）に示すように側壁８を形成す
るとき、Ｎ型ポリシリコン４の全表面が露出するまで十
分にエッチバックする必要がある。あとでシリサイドを
形成するためである。In the conventional salicide process, when forming the sidewall 8 as shown in FIG. 3A, it is necessary to sufficiently etch back until the entire surface of the N-type polysilicon 4 is exposed. is there. This is to form a silicide later.
【０００７】このときＮ型ポリシリコン４側面の一部が
露出する。そのためチタン９とＮ型ポリシリコン４との
反応が側面からも進んで側壁８上面までチタンシリサイ
ド１０ａが形成される。図３（ｃ）に示すように、ゲー
ト電極の側面で層間絶縁膜１２が薄くなったり、ゲート
電極とコンタクトとの距離が短かくなって、ゲート電極
とソース・ドレインとがショートする不良が発生する。At this time, a part of the side surface of the N-type polysilicon 4 is exposed. Therefore, the reaction between the titanium 9 and the N-type polysilicon 4 proceeds also from the side surface to form the titanium silicide 10a up to the upper surface of the side wall 8. As shown in FIG. 3C, the interlayer insulating film 12 becomes thin on the side surface of the gate electrode, or the distance between the gate electrode and the contact becomes short, which causes a short circuit between the gate electrode and the source / drain. To do.
【０００８】[0008]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、一導電型半導体基板の一主面上にゲート酸化
膜を形成する工程と、全面にポリシリコンを堆積してか
ら逆導電型不純物を拡散したのち、第１の絶縁膜を形成
する工程と、前記第１の絶縁膜および前記ポリシリコン
をパターニングして、前記ポリシリコンからなるゲート
電極を形成する工程と、前記ゲート電極をマスクとして
逆導電型不純物をイオン注入して前記一導電型半導体基
板表面に逆導電型層を形成する工程と、全面に第２の絶
縁膜を堆積したのち、エッチバックして前記ゲート電極
の側面に前記第２の絶縁膜からなる側壁を形成する工程
と、前記第１の絶縁膜をエッチングして前記ポリシリコ
ン表面を露出させたのち、全面に高融点金属を堆積する
工程と、窒素雰囲気で熱処理して前記ポリシリコンおよ
び前記逆導電型層の表面に前記高融点金属のシリサイド
層を形成する工程と、未反応の前記高融点金属をエッチ
ングしたのち、前記ゲート電極および前記側壁をマスク
として逆導電型不純物をイオン注入して前記一導電型半
導体基板表面に逆導電型高濃度層を形成する工程とを含
むものである。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate oxide film on one main surface of a one-conductivity type semiconductor substrate, and a step of forming a gate oxide film on the entire surface and then performing reverse conductivity. A step of forming a first insulating film after diffusing the type impurities, a step of patterning the first insulating film and the polysilicon to form a gate electrode made of the polysilicon, and the step of forming the gate electrode. A step of ion-implanting an impurity of opposite conductivity type as a mask to form a layer of opposite conductivity type on the surface of the semiconductor substrate of one conductivity type, and a second insulating film is deposited on the entire surface, and then etched back to form a side surface of the gate electrode. Forming a side wall of the second insulating film, exposing the polysilicon surface by etching the first insulating film, and then depositing a refractory metal on the entire surface, and a nitrogen atmosphere. Forming a silicide layer of the refractory metal on the surfaces of the polysilicon and the opposite conductivity type layer by heat treatment, and after etching the unreacted refractory metal, the gate electrode and the sidewall are used as a mask. And ion-implanting an impurity of opposite conductivity type to form a high concentration layer of opposite conductivity type on the surface of the semiconductor substrate of one conductivity type.
【０００９】[0009]
【実施例】本発明の第１の実施例について、図１（ａ）
〜（ｃ）を参照して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (c).
【００１０】はじめに図１（ａ）に示すように、Ｐ型シ
リコン基板１にＬＯＣＯＳ法により厚さ５００ｎｍのフ
ィールド酸化膜２を形成したのち厚さ２０ｎｍのゲート
酸化膜３を形成する。つぎにＣＶＤ法により厚さ３００
ｎｍのポリシリコンを堆積したのち、燐を拡散して濃度
１×１０19ｃｍ-3のＮ型ポリシリコン４を形成する。つ
ぎにＣＶＤ法により厚さ２００ｎｍの窒化シリコン膜５
を堆積する。つぎにレジスト（図示せず）をマスクとし
て窒化シリコン膜５およびＮ型ポリシリコン４をエッチ
ングしたのちレジストを除去する。つぎに燐を加速エネ
ルギー３０ｋｅＶで注入量（ドース）３×１０13ｃｍ-2
イオン注入して、Ｎ型ＬＤＤ層６を形成する。つぎにＣ
ＶＤ法により厚さ２００ｎｍの酸化シリコン膜７を堆積
する。First, as shown in FIG. 1A, a field oxide film 2 having a thickness of 500 nm is formed on a P-type silicon substrate 1 by a LOCOS method, and then a gate oxide film 3 having a thickness of 20 nm is formed. Next, a thickness of 300 is obtained by the CVD method.
nm of polysilicon is deposited and then phosphorus is diffused to form N-type polysilicon 4 having a concentration of 1 × 10 19 cm −3 . Next, the silicon nitride film 5 having a thickness of 200 nm is formed by the CVD method.
Deposit. Next, the silicon nitride film 5 and the N-type polysilicon 4 are etched using a resist (not shown) as a mask, and then the resist is removed. Next, phosphorus is injected with an acceleration energy of 30 keV (dose) 3 × 10 13 cm -2
Ions are implanted to form the N-type LDD layer 6. Then C
A silicon oxide film 7 having a thickness of 200 nm is deposited by the VD method.
【００１１】つぎに図１（ｂ）に示すように、異方性エ
ッチングにより酸化シリコン膜７をエッチバックしてＮ
型ポリシリコン４および窒化シリコン膜５の側面に酸化
シリコン膜７からなる側壁８を形成する。ここでＮ型Ｌ
ＤＤ層６上の酸化シリコン膜７も除去される。Next, as shown in FIG. 1B, the silicon oxide film 7 is etched back by anisotropic etching to remove N.
Sidewalls 8 made of a silicon oxide film 7 are formed on the side surfaces of the type polysilicon 4 and the silicon nitride film 5. N type L here
The silicon oxide film 7 on the DD layer 6 is also removed.
【００１２】つぎにＮ型ポリシリコン４上の窒化シリコ
ン膜５をエッチングする。このとき窒化シリコン膜５の
膜厚の分だけ、Ｎ型ポリシリコン４上面から側壁８が突
出している。つぎにスパッタ法により厚さ１００ｎｍの
チタン９を堆積する。Next, the silicon nitride film 5 on the N-type polysilicon 4 is etched. At this time, the side wall 8 projects from the upper surface of the N-type polysilicon 4 by the thickness of the silicon nitride film 5. Next, titanium 9 having a thickness of 100 nm is deposited by the sputtering method.
【００１３】つぎに図１（ｃ）に示すように、６５０℃
の窒素雰囲気でアニール（熱処理）してＮ型ポリシリコ
ン４上面およびＮ型ＬＤＤ層６上面にチタンシリサイド
１０ａ，１０ｂ，１０ｃを形成してＮ型ポリシリコン４
およびチタンシリサイド１０ａからなるゲート電極を形
成する。そのあと未反応のチタン９を除去する。Next, as shown in FIG. 1 (c), 650 ° C.
By annealing (heat treatment) in the nitrogen atmosphere to form titanium silicides 10a, 10b and 10c on the upper surface of the N-type polysilicon 4 and the upper surface of the N-type LDD layer 6, respectively.
A gate electrode made of titanium silicide 10a is formed. Then, the unreacted titanium 9 is removed.
【００１４】つぎにフィールド酸化膜２、ゲート電極
４，１０ａおよび側壁８をマスクとして砒素を加速エネ
ルギー７０ｋｅＶで注入量（ドース）５×１０15ｃｍ-2
イオン注入したのち、８５０℃の窒素雰囲気で２０分間
アニールしてＮ+ 型ソース・ドレイン１１を形成する。
つぎに層間絶縁膜１２を堆積したのち、コンタクトを開
口してからアルミニウム配線１３を形成してＭＯＳＦＥ
Ｔの素子部が完成する。Next, using the field oxide film 2, the gate electrodes 4, 10a and the side walls 8 as a mask, arsenic is implanted at an acceleration energy of 70 keV (dose) 5 × 10 15 cm -2.
After ion implantation, annealing is performed in a nitrogen atmosphere at 850 ° C. for 20 minutes to form N + type source / drain 11.
Next, after depositing an interlayer insulating film 12, a contact is opened and then an aluminum wiring 13 is formed to form a MOSFE.
The element part of T is completed.
【００１５】本実施例ではＰ型シリコン基板にＮチャネ
ルＭＯＳＦＥＴを形成した。Ｐ型シリコン基板にＮウェ
ルを形成すればＰチャネルＭＯＳＦＥＴを形成すること
ができる。In this embodiment, an N channel MOSFET is formed on a P type silicon substrate. If an N well is formed on a P type silicon substrate, a P channel MOSFET can be formed.
【００１６】さらにＮ型シリコン基板にＰチャネルＭＯ
ＳＦＥＴを形成し、Ｎ型シリコン基板に形成したＰウェ
ルにＮチャネルＭＯＳＦＥＴを形成することもできる。
つぎに本発明の第２の実施例について、図２（ａ）お
よび（ｂ）を参照して説明する。Further, a P channel MO is formed on the N type silicon substrate.
It is also possible to form the SFET and form the N-channel MOSFET in the P-well formed on the N-type silicon substrate.
Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).
【００１７】本実施例では図２（ａ）に示すように、Ｎ
型ポリシリコン４の上にノンドープポリシリコン４ａを
形成する。In this embodiment, as shown in FIG.
Non-doped polysilicon 4 a is formed on the mold polysilicon 4.
【００１８】そのため図２（ｂ）に示すように、アニー
ル工程でＮ型ポリシリコン４よりもノンドープポリシリ
コン４ａとチタン９の方がシリサイド化し易く、均一な
チタンシリサイド１０ａが形成されて、ゲート電極の抵
抗を低減することができる。Therefore, as shown in FIG. 2B, in the annealing process, the non-doped polysilicon 4a and the titanium 9 are more easily silicidized than the N-type polysilicon 4, and a uniform titanium silicide 10a is formed to form the gate electrode. The resistance of can be reduced.
【００１９】このあと第１の実施例と同様にしてＭＯＳ
ＦＥＴの素子部が完成する。After that, as in the first embodiment, the MOS is formed.
The element part of the FET is completed.
【００２０】[0020]
【発明の効果】ポリシリコンの上に絶縁膜を重ねた２層
膜をパターニングしたのち、その側面に側壁を形成して
からポリシリコン上の絶縁膜を除去する。その結果、ポ
リシリコンの側面が完全に側壁で覆われているので、そ
のあと高融点金属を堆積してからアニールしたとき、ポ
リシリコンの側面からシリサイド化が進む恐れがなくな
った。EFFECTS OF THE INVENTION After patterning a two-layer film in which an insulating film is overlaid on polysilicon, side walls are formed on the side surfaces thereof, and then the insulating film on the polysilicon is removed. As a result, since the side surface of the polysilicon is completely covered with the side wall, when the refractory metal is subsequently deposited and then annealed, there is no possibility that the silicidation proceeds from the side surface of the polysilicon.
【００２１】ゲート電極の形状が改善され、ソース・ド
レインとのショート不良を解消することができた。The shape of the gate electrode was improved, and the short circuit between the source and drain could be eliminated.
【図１】本発明の第１の実施例を工程順に示す断面図で
ある。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.
【図２】本発明の第２の実施例を工程順に示す断面図で
ある。FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.
【図３】従来のサリサイド構造のゲート電極を有するＭ
ＯＳＦＥＴの製造方法を示す断である。FIG. 3 is an M having a conventional salicide structure gate electrode.
9 is a diagram showing a method of manufacturing an OSFET.
１ Ｐ型シリコン基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ Ｎ型ポリシリコン ４ａ ノンドープポリシリコン ５ 窒化シリコン膜 ６ Ｎ型ＬＤＤ層 ７ 酸化シリコン膜 ８ 側壁（サイドウォール） ９ チタン １０ａ，１０ｂ，１０ｃ チタンシリサイド １１ Ｎ+ 型ソース・ドレイン １２ 層間絶縁膜 １３ アルミニウム配線1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 N-type polysilicon 4a Non-doped polysilicon 5 Silicon nitride film 6 N-type LDD layer 7 Silicon oxide film 8 Side wall (sidewall) 9 Titanium 10a, 10b, 10c Titanium silicide 11 N + type source / drain 12 Interlayer insulating film 13 Aluminum wiring
Claims (1)
酸化膜を形成する工程と、全面にポリシリコンを堆積し
てから逆導電型不純物を拡散したのち、第１の絶縁膜を
形成する工程と、前記第１の絶縁膜および前記ポリシリ
コンをパターニングして、前記ポリシリコンからなるゲ
ート電極を形成する工程と、前記ゲート電極をマスクと
して逆導電型不純物をイオン注入して前記一導電型半導
体基板表面に逆導電型層を形成する工程と、全面に第２
の絶縁膜を堆積したのち、エッチバックして前記ゲート
電極の側面に前記第２の絶縁膜からなる側壁を形成する
工程と、前記第１の絶縁膜をエッチングして前記ポリシ
リコン表面を露出させたのち、全面に高融点金属を堆積
する工程と、窒素雰囲気で熱処理して前記ポリシリコン
および前記逆導電型層の表面に前記高融点金属のシリサ
イド層を形成する工程と、未反応の前記高融点金属をエ
ッチングしたのち、前記ゲート電極および前記側壁をマ
スクとして逆導電型不純物をイオン注入して前記一導電
型半導体基板表面に逆導電型高濃度層を形成する工程と
を含む半導体装置の製造方法。1. A step of forming a gate oxide film on one main surface of a one-conductivity-type semiconductor substrate, and a step of depositing polysilicon on the entire surface and diffusing impurities of the opposite conductivity-type, and then forming a first insulating film. And a step of patterning the first insulating film and the polysilicon to form a gate electrode made of the polysilicon, and using the gate electrode as a mask, ions of the opposite conductivity type are ion-implanted to perform the one conductivity. Forming a reverse conductivity type layer on the surface of the semiconductor substrate and forming a second
And then etching back to form a side wall made of the second insulating film on the side surface of the gate electrode; and etching the first insulating film to expose the polysilicon surface. After that, a step of depositing a refractory metal on the entire surface, a step of heat-treating in a nitrogen atmosphere to form a silicide layer of the refractory metal on the surfaces of the polysilicon and the opposite conductivity type layer, and the unreacted refractory metal A step of etching the melting point metal and then ion-implanting an impurity of opposite conductivity type using the gate electrode and the sidewall as a mask to form a high concentration layer of opposite conductivity type on the surface of the one conductivity type semiconductor substrate. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20281692A JPH0653236A (en) | 1992-07-30 | 1992-07-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20281692A JPH0653236A (en) | 1992-07-30 | 1992-07-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0653236A true JPH0653236A (en) | 1994-02-25 |
Family
ID=16463679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20281692A Withdrawn JPH0653236A (en) | 1992-07-30 | 1992-07-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0653236A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100272276B1 (en) * | 1997-11-19 | 2000-12-01 | 김영환 | Manufacturing method of semiconductor device |
| KR100504192B1 (en) * | 2000-08-28 | 2005-07-28 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor device |
-
1992
- 1992-07-30 JP JP20281692A patent/JPH0653236A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100272276B1 (en) * | 1997-11-19 | 2000-12-01 | 김영환 | Manufacturing method of semiconductor device |
| KR100504192B1 (en) * | 2000-08-28 | 2005-07-28 | 매그나칩 반도체 유한회사 | Method for manufacturing semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |