JPH0654457B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device having a clock control circuit suitable for use in a large scale integrated circuit (LSI) with low power consumption. .

[Conventional technology]

In recent years, there have been significant advances in semiconductor technology, especially M
The miniaturization of OS (Metal Oxide Semiconductor) is remarkable. Along with this, many functions have come to be integrated on a millimeter square silicon. However, the higher the integration and the higher speed, the more the power consumption increases, and the heat dissipation of the package is becoming difficult. Therefore, CMOS (Complementary MO) that consumes power only when the signal changes
S) is in the spotlight as a powerful device. Because of low power consumption, in many CMOS devices, power is supplied by battery, backup, or battery itself. Therefore, lower power consumption has been required.

Conventionally, in some LSIs such as microprocessors, clocks are stopped to eliminate signal changes inside the LSIs to reduce power consumption. An example thereof is shown in FIG. This clock control circuit is provided with flip-flops 11 to 13 for synchronizing the signal 1c requesting the clock supply stop with the two-phase clocks 1a and 1b, and AN for prohibiting the clock supply.
It is composed of D gates 14 and 15 and a data processing unit 16. The operation of this circuit will be described with reference to the time chart of FIG. Now, assuming that the clock supply stop request signal 1c is asynchronously dropped from "H" to "L", the flip-flop 11 first synchronizes with the clock 1b, and the signal 1d
To get However, since there is a possibility that chattering has occurred in the signal 1d at the time of synchronization, the flip-flop 12 synchronizes with the clock 1a to obtain the signal 1e. In addition, the flip 1
The signal 1f synchronized in b is also obtained. The signals 1f and 1e are clocked by the AND gates 14 and 15, respectively.
Clocks 1g and 1h to be supplied to the data processing unit 16 are fixed to "L" by prohibiting a and 1b. here,
The signal change in the data processing unit 16 disappears, and the CMOS device stops power consumption. However, since the clock supply stop request signal described above is given from the outside of the LSI or given at a constant cycle, there is also a lack of flexibility depending on the application system.

[Problems to be Solved by the Invention]

An object of the present invention is to provide a data processing device that can flexibly reduce power consumption by including a software-controlled clock control circuit.

[Means for Solving the Problems]

The present invention provides a means for stopping a plurality of clock signals in a mixed state of a low potential level or a high potential level by executing a clock supply stop instruction stored in advance together with the data processing instruction, and means for canceling the clock stop. It is provided with a means for releasing the stop of the clock signal by an interrupt, and a mask logic means for deciding whether to perform the processing by the interrupt after the stop is released or to execute the instruction next to the clock supply stop instruction. is there.

〔Example〕

Next, an example for suitably implementing the present invention will be described in detail.
FIG. 3 shows a clock control circuit of the data processing apparatus according to the present invention. This circuit detects a specific command of the data processing device and synchronizes it with a flip-flop 30.
0, 301, flip-flops 302, 303 for controlling the stop of the clocks, clock gates 304 to 306 for inhibiting the supply of the clock groups 3a, 3b, 3c, and a flip-flop group for synchronizing and storing four level interrupts. 310 to 317, an OR gate 318 that detects the arrival of at least one interrupt, flip-flop groups 319 to 321 that obtain the release timing of the clock stop, clock gates 322 and 323 that determine the synchronization and storage timing of the interrupts, It consists of an interrupt mask gate 324. The operation of this circuit will be described separately for two cases, that is, when the clock is stopped and when the clock is released.

(1) Operation when clock is stopped For convenience of explanation, the data processing device is under microprogram control. When a microinstruction for a clock stop request is read in the microprogram that executes a specific instruction, that is, an instruction to enter the low power consumption mode by stopping the clock, the signal 3d becomes "H". This is stored in the flip-flop 300 by the clock 3b, and the timing of the signal 3e obtained thereby is adjusted to the flip-flop 301 by the clock 3a. Black 3
The signal 3f synchronized with a is flipped by the clock 3b.
Flop 302 is set to instruct to stop the clock.
The clock stop signal 3g is synchronized with the clock 3a by the flip-flop 303, and then the pair of signals 3h, 3
Clock gates 304-306 by i (▲ ▼)
The clock 3x corresponding to the clock 3a is stopped in the "H" state by the gate 305, and the clocks 3y and 3z corresponding to the clocks 3b and 3c are stopped in the "L" state. The reason for this is that the clock 3x is used for pre-charging the dynamic logic in one micro operation of the data processing device, and therefore the pre-charge state is maintained when the clock is stopped, thereby playing the role of smoothing the operation when the stop is released. As a result, no power is consumed during the clock stop period. Clock 3 that can be stopped and controlled as described above
Since x, 3y, and 3z are supplied to the data processing device, there is no signal change in the device, and the CMOS circuit consumes no power. FIG. 4 shows a time sequence until the clock is stopped.

(2) Operation when the clock stop is released The clock stop control is programmable by an instruction as described above. On the other hand, the stop release is performed by an interrupt to the data processing device. The interrupt here refers to a service request from the input / output device, an error, a reset, or the like. The four-level interrupts shown in FIG. 3 are signals 3l, 3m, 3
The first flip-flop group 310-3 by n, 3o
It is received at 13 by a synchronous clock 3t provided by a clock gate 322. Next, in order to prevent chattering, another synchronous clock 3s supplied by the clock gate 323 to the second flip-flop groups 314 to 317 is received again. For example, flip-flop 317 output 3p, one of those synchronization interrupt signals, is NOR
It is input to the gate 318 and stored in the flip-flop 319 at the clock 3a. When any of the four level interrupts enters, the NOR gate 318 detects that there is an interrupt, and reflects this on the flip-flop 319. The output 3q of the flip-flop 319 is further synchronized by flip-flops 320 and 321 to obtain the signal 3r, and the flip-flop 302 for clock stop control is reset. And flip-flop 3
Reference numeral 03 designates signals 3h and 3i (▲ ▼) for releasing the clock stop in synchronization with the clock 3a, and the clock gates 304 to 3
06. The time chart for releasing the clock stop is shown in FIG. 5, and the start of the clock operation is smoothly achieved.

Next, the operation after releasing the clock stop will be described. After at least one of the interrupt signals 3l, 3m, 3n and 3o is input to the clock control circuit to release the clock stop state, the data processing device sets the mask gate 324.
The process is continued by deciding whether or not to enter the interrupt process by observing the result of the above, and this situation will be described by the microinstruction flow chart shown in FIG. In this flow chart, one block indicates one micro instruction. A description will be given below in relation to the time chart shown in FIGS. The instruction execution for stopping the clock starts from the PC (Program Counter) decrement of block 1.
This is pipeline controlled at the instruction fetch stage,
Since the PC is incremented by one and is not directly related to the present invention, detailed description thereof will be omitted. next,
Issue a micro-command to stop the block on Block 2,
Enter the clock stop state. Block 3 NO-O
P (No. Operation) is a margin because the clock is completely stopped, and NO-OP of the block 4 is a microinstruction for waiting an interrupt when the clock is stopped.

When an interrupt is accepted in the NO-OP state of block 4 described above, control is transferred to the microinstruction at the head of the instruction fetch of block 5 after a certain synchronization cycle. Here, the PC is sent to the MAR (Memory Address Register) and the PC is incremented. In block 6, the main memory is read, and the instruction read in block 7 is fetched into an instruction register IR (Instruction Register).
In this way, after the micro instruction of block 8 is executed, the interrupt check is performed, and when an interrupt signal is present at the output of the mask gate 324, the interrupt is branched to the micro program (blocks 9 and 10) for interrupt processing. When there is no signal, it branches to one of the execution microprograms corresponding to the instruction fetched by block 7. As described above, after the clock stop is released, the mask gate 3
Depending on the state of 24, the macro program is controlled to the interrupt processing or the next instruction.

As described above, according to the illustrated embodiment, the user-programmable clock stop can be performed by the special instruction, whereby the low power consumption mode can be entered. Further, it becomes possible to flexibly control the interrupt processing or the next instruction according to the mask state of the interrupt.

〔The invention's effect〕

As described above in detail, according to the present invention, the clock control circuit in the data processing device is stopped by the software, and is canceled by the interrupt, so that the low power consumption can be flexibly controlled. Play.

[Brief description of drawings]

1 is a diagram showing a conventional clock control circuit, FIG. 2 is a diagram showing its time chart, FIG. 3 is a diagram showing a clock control circuit of a data processing apparatus according to the present invention, and FIG.
The figure shows the time chart when the clock is stopped, Fig. 5 shows the time chart when the clock is released, and Fig. 6 is the flow of the microprogram for controlling a series of clock inhibition / release. It is the figure which showed the chart. 300, 302 ... Flip Flop, 304, 30
5, 306 ... Clock gate, 318 ... NOR gate, 319 ... Flip flop.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasushi Akao 1450, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (56) References JP-A-55-47549 (JP, A) JP-A-53 -68051 (JP, A) JP-B-55-18931 (JP, B2)

Claims (1)

[Claims] 1. A data processing apparatus comprising a clock control circuit for sequentially reading and executing a program including a data processing instruction stored in advance, wherein said clock control circuit stores a clock stored in advance together with said data processing instruction. Means for stopping a plurality of clock signals in a mixed state of low potential level or high potential level by executing the supply stop instruction, and means for canceling the stop of the clock signal by an interrupt for releasing the clock stop, And a mask logic means for determining whether to execute the processing by the interrupt or execute the next instruction of the clock supply stop instruction after the stop is released.