JPH0654785B2 - Modulation doping transistor - Google Patents
Modulation doping transistorInfo
- Publication number
- JPH0654785B2 JPH0654785B2 JP59279277A JP27927784A JPH0654785B2 JP H0654785 B2 JPH0654785 B2 JP H0654785B2 JP 59279277 A JP59279277 A JP 59279277A JP 27927784 A JP27927784 A JP 27927784A JP H0654785 B2 JPH0654785 B2 JP H0654785B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- modulation doping
- lattice
- transistor
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
- H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
- H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
- H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials
Landscapes
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、変調ドーピングトランジスタに関し、特にIn
xGa1-xAs/Al1-yInyAs歪み超格子を用いたトランジスタ
に関する。TECHNICAL FIELD The present invention relates to a modulation doping transistor, and in particular to In
x Ga 1-x As / Al 1-y In y As A transistor using a strained superlattice.
〔背景技術および発明が解決しようとする問題点〕 ２つの異種半導体の接合（ヘテロ接合）は、導電帯の底
の不連続性によりヘテロ界面の低い導電帯側に電子蓄積
層を形成したり、キヤリヤを閉じ込める作用があり、変
調ドーピングトランジスタに利用されている。[Background Art and Problems to be Solved by the Invention] In a junction (heterojunction) of two different semiconductors, an electron storage layer is formed on the side of a conduction band having a low hetero interface due to discontinuity at the bottom of the conduction band, It has the function of confining carriers and is used in modulation doping transistors.
従来、用いられてきた代表的な変調ドーピング用のヘテ
ロ接合はGaAs／AlGaAs系であつた。このGaAs／AlGaAs系
より、より高速を期待してInP基板上のIn0.53Ga0.47As
／Al0.48In0.52As系の変調ドーピングトランジスタが試
作されているが、合金散乱のため当初予想したほどの移
動度が得られていないのが実状である。A typical heterojunction for modulation doping that has been conventionally used is the GaAs / AlGaAs system. In 0.53 Ga 0.47 As on InP substrate, expecting higher speed than this GaAs / AlGaAs system.
/ Al 0.48 In 0.52 As type modulation doping transistor has been prototyped, but in reality it is not as high as originally expected due to alloy scattering.
したがつて、本発明の目的は、GaAs／AlGaAs系、In0.53
Ga0.47As／Al0.48In0.52As系変調ドーピングトランジス
タの問題点を解決した高速デバイスを提供することにあ
り、この目的は、本発明によつてInxGa1-xAs／Al1-yIny
As（0.53＜ｘ≦１，０≦ｙ＜0.52）系歪み超格子を用い
ることで解決される。Therefore, the object of the present invention is to provide a GaAs / AlGaAs system, In 0.53
It is an object of the present invention to provide a high-speed device that solves the problems of Ga 0.47 As / Al 0.48 In 0.52 As-based modulation-doped transistors, and an object of the present invention is to provide In x Ga 1-x As / Al 1-y In. y
This can be solved by using an As (0.53 <x≤1, 0≤y <0.52) strained superlattice.
種々のIII−Ｖ族化合物半導体および３元混晶のエネル
ギー・ギヤツプと格子定数の関係を第２図に示す。前述
したGaAs／AlGaAs系、In0.53Ga0.47As／Al0.48In0.52As
系は図中Ａ−Ｂ、Ｃ−Ｄに示すように同一格子定数のヘ
テロ接合である。本発明によるヘテロ接合は、図中Ｅ−
Ｆにその１例を示すようにInxGa1-xAsはInPに格子整合
したIn0.53Ga0.47AsよりInAsに近寄つた組成、またAl
1-yInyAsは、InPに格子整合したAl0.48In0.52AsよりAlA
sに近寄つた組成を用いている。一般にヘテロ界面に格
子不整があると、結晶層厚が厚い場合はミスフイツト転
位が発生するが、層厚が薄い場合は、格子不整が歪みの
形で各層内に蓄えられ転位は発生しない。転位が発生し
始める層厚は格子不整の大きさに依存するが、本発明に
よる多層構造では、転位が発生し始めるより薄い層を用
いている。第３図にInxGa1-xAsの電子移動度の組成依存
性を示す。本発明では、In0.53Ga0.47AsよりInAsよりの
組成を動作層として用いているためIn0.53Ga0.47Asを動
作層としたものに比べてより高い電子移動度が期待でき
る。FIG. 2 shows the relationship between the energy constant and the lattice constant of various III-V group compound semiconductors and ternary mixed crystals. GaAs / AlGaAs system mentioned above, In 0.53 Ga 0.47 As / Al 0.48 In 0.52 As
The system is a heterojunction having the same lattice constant as shown by AB and CD in the figure. The heterojunction according to the present invention is represented by E- in the figure.
As an example is shown in F, In x Ga 1-x As has a composition closer to InAs than In 0.53 Ga 0.47 As lattice matched to InP, and Al
1-y In y As is AlA from lattice-matched Al 0.48 In 0.52 As
It uses a composition that approaches s. In general, when the hetero interface has a lattice mismatch, misfit dislocations occur when the crystal layer thickness is large, but when the layer thickness is thin, the lattice mismatch is stored in each layer in the form of strain and no dislocation occurs. The layer thickness at which dislocations start to occur depends on the size of the lattice mismatch, but the multilayer structure according to the present invention uses a thinner layer than the onset of dislocations. Figure 3 shows the composition dependence of the electron mobility of In x Ga 1-x As. In the present invention, an In 0.53 Ga expected higher electron mobility as compared with those of In 0.53 Ga 0.47 As and the active layer because of the use of the composition of from InAs as the active layer than 0.47 As.
以下、添加図面を参照して、本発明の具体的な実施例を
述べる。Specific examples of the present invention will be described below with reference to the accompanying drawings.
第１図に本発明によるInxGa1-xAs／Al1-yInyAs歪み超格
子変調ドーピングトランジスタの実施例の断面構造を示
す。第１図において、半絶縁性InP基板１１上にアンド
ープのAl0.48In0.52Asバツフア層１２、続いて厚さ100
ÅアンドープのIn0.80Ga0.20As層１３、１４、１５、厚
さ100Åのｎ型（キヤリヤ密度８×10171/cm3）のAl0.76
In0.24As１６、１７、１８を交互に積層させる。（最上
層はAl0.76In0.24Asである）さらにAuGeNiのオーミツク
電極１９、２０、Ａｌのシヨツトキゲート電極２１を形
成する。In0.80Ga0.20As／Al0.76In0.24As歪み超格子中
のエネルギーバンド構造は第４図に示すようになり、ヘ
テロ界面のInxGa1-xAs側に２次元電子が蓄積し、この電
子がトランジスタの電気伝導に寄与する。In0.80Ga0.20
Asの電子移動度が高いので高速動作を期待できる。また
シヨツトキー電極下のAl0.76In0.24AsはAl0.48In0.52As
よりエネルギー・ギヤツプが大きく良好なシヨツトキ特
性が期待できる。さらにIn0.60Ga0.20As／Al0.76In0.24
Asヘテロ界面の伝導帯の底のエネルギー差は、InPに格
子整合したIn0.53Ga0.47As／Al0.48In0.52Asヘテロ界面
のそれより大きくとれるため界面でのキヤリヤ密度を高
くすることができる。FIG. 1 shows a cross-sectional structure of an embodiment of an In x Ga 1-x As / Al 1-y In y As strained superlattice modulation doping transistor according to the present invention. In FIG. 1, an undoped Al 0.48 In 0.52 As buffer layer 12 is formed on a semi-insulating InP substrate 11, and a thickness of 100 is then applied.
Å Undoped In 0.80 Ga 0.20 As layers 13, 14, 15 and 100 Å n-type (carrier density 8 × 10 17 1 / cm 3 ) Al 0.76
In 0.24 As 16, 17, 18 are laminated alternately. (The uppermost layer is Al 0.76 In 0.24 As) Further, AuGeNi ohmic electrodes 19 and 20 and an Al Schottky gate electrode 21 are formed. In 0.80 Ga 0.20 As / Al 0.76 In 0.24 As The energy band structure in the strained superlattice is as shown in Fig. 4, and two-dimensional electrons are accumulated on the In x Ga 1-x As side of the hetero interface. Contribute to the electrical conduction of the transistor. In 0.80 Ga 0.20
As electron mobility of As is high, high-speed operation can be expected. Al 0.76 In 0.24 As below the Schottky electrode is Al 0.48 In 0.52 As
Greater energy / gap and good shock characteristics can be expected. In 0.60 Ga 0.20 As / Al 0.76 In 0.24
The energy difference at the bottom of the conduction band at the As hetero interface can be made larger than that at the In 0.53 Ga 0.47 As / Al 0.48 In 0.52 As hetero interface lattice-matched to InP, so that the carrier density at the interface can be increased.
なおInxGa1-xAs，Al1-yInyAsの組成に関しては、前記実
施例の組成に限らず、InxGa1-xAsについては0.53＜ｘ≦
１、Al1-yInyAsについては０≦ｙ＜0.52であれば良い。The composition of In x Ga 1-x As and Al 1-y In y As is not limited to the composition of the above-mentioned embodiment, and 0.53 <x ≦ for In x Ga 1-x As.
1 and Al 1-y In y As may be 0 ≦ y <0.52.
また、第１図の実施例ではInxGa1-xAs３層、Al1-yInyAs
３層であるが、この層数はこれに限らない。Further, in the embodiment of FIG. 1, In x Ga 1-x As 3 layers, Al 1-y In y As
Although there are three layers, the number of layers is not limited to this.
以上のように、本発明によるInxGa1-xAs(0.53＜ｘ≦
１）／Al1-yInyAs（０≦ｙ＜0.52）歪み超格子を用いた
変調ドープトランジスタは、従来のデバイスに比べて動
作速度が高いため、現在FET,IC等が用いられているあら
ゆる分野に用いることができ、その産業上の利用価値は
極めて大きく、特に高速処理が必要な分野、例えば計算
機のCPU，メモリ、画像処理等での利用が期待できる。As described above, In x Ga 1-x As (0.53 <x ≦
1) / Al 1-y In y As (0 ≦ y <0.52) Modulation-doped transistors using strained superlattices have higher operating speed than conventional devices, so FETs, ICs, etc. are currently used. It can be used in all fields, and its industrial utility value is extremely large, and it can be expected to be used particularly in fields requiring high-speed processing, such as CPUs of computers, memories, and image processing.
第１図は、本発明によるInxGa1-xAs／Al1-yInyAs歪み超
格子を用いた変調ドープトランジスタの断面図である。 第２図は、種々のIII−Ｖ族半導体および３元混晶のエ
ネルギー・ギヤツプと格子定数との関係を示す図であ
る。 第３図は、InxGa1-xAsの電子移動度の組成依存性を示す
図である。 第４図は、InxGa1-xAs／Al1-yInyAs歪み超格子のエネル
ギー・バンド図である。 １１は半絶縁性InP基板、１２はアンドープAl0.48In
0.52Asバツフア層、１３、１４、１５はアンドープIn
0.80Ga0.20As層、１６、１７、１８はｎ型Al0.76In0.24
As層、１９、２０はAuGeNiのオーミツク電極、２１はＡ
ｌのシヨツトキ電極。FIG. 1 is a cross-sectional view of a modulation-doped transistor using an In x Ga 1-x As / Al 1-y In y As strained superlattice according to the present invention. FIG. 2 is a diagram showing the relationship between energy constants and lattice constants of various III-V group semiconductors and ternary mixed crystals. FIG. 3 is a diagram showing the composition dependence of the electron mobility of In x Ga 1-x As. FIG. 4 is an energy band diagram of an In x Ga 1-x As / Al 1-y In y As strained superlattice. 11 is a semi-insulating InP substrate, 12 is undoped Al 0.48 In
0.52 As buffer layer, 13, 14 and 15 are undoped In
0.80 Ga 0.20 As layer, 16, 17, 18 are n-type Al 0.76 In 0.24
As layer, 19 and 20 are AuGeNi ohmic electrodes, 21 is A
1-shot electrode.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭56−76581（ＪＰ，Ａ) 特開 昭58−158912（ＪＰ，Ａ) 特開 昭59−74618（ＪＰ，Ａ) 特開 昭59−100576（ＪＰ，Ａ) ─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-56-76581 (JP, A) JP-A-58-158912 (JP, A) JP-A-59-74618 (JP, A) JP-A-59- 100576 (JP, A)
Claims (1)
したIn0.53Ga0.47AsよりＩｎを多く含むアンドープInxG
a1-xAs(0.53＜ｘ≦１）層と、ＩｎＰに格子整合したAl
0.48In0.52AsよりＡｌを多く含みｎ型にドーピングされ
たAl1-yInyAs(0≦ｙ＜0.52)層の薄膜を互いに積層した
構造を備え、該多層構造上のショットキ電極と該電極に
対して互いに反対側にある２つのオーミック性電極とを
備えた事を特徴とする変調ドーピングトランジスタ。1. An undoped In x G containing more In than In 0.53 Ga 0.47 As lattice-matched to InP on a semi-insulating InP substrate.
a 1-x As (0.53 <x ≦ 1) layer and Al lattice-matched to InP
The Schottky electrode and the electrode on the multi-layer structure have a structure in which thin films of Al 1-y In y As (0 ≦ y <0.52) layers containing more Al than 0.48 In 0.52 As and doped in an n-type are stacked. A modulation doping transistor characterized in that it is provided with two ohmic electrodes on opposite sides to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59279277A JPH0654785B2 (en) | 1984-12-25 | 1984-12-25 | Modulation doping transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59279277A JPH0654785B2 (en) | 1984-12-25 | 1984-12-25 | Modulation doping transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61152081A JPS61152081A (en) | 1986-07-10 |
| JPH0654785B2 true JPH0654785B2 (en) | 1994-07-20 |
Family
ID=17608920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59279277A Expired - Lifetime JPH0654785B2 (en) | 1984-12-25 | 1984-12-25 | Modulation doping transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0654785B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02125434A (en) * | 1988-07-19 | 1990-05-14 | Sharp Corp | Field effect semiconductor device |
| JPH06125141A (en) * | 1992-08-25 | 1994-05-06 | Olympus Optical Co Ltd | Semiconductor quantum well optical element |
| EP0627771B1 (en) * | 1992-12-21 | 1999-07-21 | The Furukawa Electric Co., Ltd. | Distorted superlattice semiconductor photodetecting element with side-contact structure |
| WO2000065663A1 (en) * | 1999-04-26 | 2000-11-02 | Kansai Research Institute | Heterostructure field-effect transistor |
| US20160005849A1 (en) * | 2014-07-01 | 2016-01-07 | Qualcomm Incorporated | Method and apparatus for 3d concurrent multiple parallel 2d quantum wells |
-
1984
- 1984-12-25 JP JP59279277A patent/JPH0654785B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61152081A (en) | 1986-07-10 |
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