JPH0657004B2 - Data communication control system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data communication control system, and more particularly to a data communication control system suitable for realizing high throughput in workstations, personal computers, bank terminals and the like.

[Background of the Invention]

Conventionally, for example, a local area network (LAN)
Cost reduction is required for the communication control board used in such cases. Therefore, reduce the memory capacity on the board,
Efforts are being made to realize a communication control function with a small amount of hardware, such as simplifying the interface between the station that incorporates it and the board. Especially broadband LAN
In this case, an RF (high frequency) modem is required, and if this is mounted on the control board, it occupies a large area on the board. Therefore, it is necessary to reduce the amount of hardware in other circuit parts, and special measures are required to realize the high throughput required by high-performance workstations, various servers, and the like.

[Object of the Invention]

An object of the present invention is to optionally increase the throughput of the above-mentioned communication control board.

[Outline of Invention]

Broadband LAN requires an RF modem for converting between high frequency signals and digital signals.
The F modem is large in size, and occupies about 1/3 of the IE ³ 796 bus board, for example. Therefore, in order to realize the communication control function including the RF board on one board, it is necessary to reduce the hardware amount of the circuit section other than the modem, and the throughput must be sacrificed to some extent. Although the expected throughput is sufficient for personal computers and the like, it is insufficient for stations where traffic is concentrated, such as various servers and distributed processing devices.
The present invention is characterized in that an accelerating board for compensating for these throughput shortages is prepared, and the accelerating board has an interface with a host computer and a buffer capacity expansion function.

Example of Invention

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of a broadband LAN (local area network). The coaxial cable 2 is installed in a layered manner from the frequency converter 1. Reference numeral 3 is a branching device for branching a signal, in which a down signal (a signal from the frequency converter to each station) is branched and only an up signal (a signal from each station to the frequency converter) is passed in the direct communication direction. It has a sex-coupling function. The LAN control boards 6a and 6b are connected to the cables output from the branching device, and are incorporated in the stations 5a and 5b, respectively. Each station is 2 Mbps (bit / sec) and CSMA / CD (Carr
ier Sense Multiple Access with Collision Detectio
n: ISO DIS 8802/3) type LAN
Connected by. The data is modulated to the upstream signal frequency and transmitted to the frequency converter 1. Here, the data is converted to the downlink signal frequency and the data is transmitted to all stations.

FIG. 2 is a hardware block configuration diagram of the LAN control board 6 built in the station 5. The RF modem 15 converts between a 2 Mbps digital signal and a 6 MHZ band analog signal. For example, the 6 HMz band (uplink signal: 21 to 27 MH shown in the high-speed data section of FIG.
Z, downlink signal: 240-246 MHZ) is used.

LAN controller 14 is a well-known CAMA / D
A device for performing C protocol processing, which is a local bus 1
A bus 3 connects the above hardware.

The data flow when transmitting and receiving data will be described below.

At the time of transmission: The data to be transmitted is transferred from the host memory 8 to the local memory 12 in the board 6 via the host interface control unit 11. LAN controller 14
The data in the LM is transmitted by CSMA / CD, and the transmission result is notified to the host processor 7. The local processor 10 is a processing device that executes data processing in these boards.

Upon reception: The LAN controller 14 selects a frame addressed to itself (the own station address is equal to the destination address 22 of the frame 21) from the frames 21 flowing on the transmission path, stores it in the local memory 12, and needs it for the received data. After performing various protocol processes, the data is transferred to the host memory 8 via the host interface control unit 11. still,
The source station address of the frame is set in the source address (SA) field.

Now, how to perform the data transfer between the host memory 8 and the local memory 12 at the time of transmitting and receiving the above data,
This is a major issue for the interface between the LAN control board and the host.

The host interface is roughly classified into the following three types.

(1) Shared memory system: A system in which a memory that can be accessed by both the host processor 7 and the local processor 10 is prepared in the LAN control board.
Data transfer between the local memory 12 and the local memory 12 is controlled by the host processor 7.

(2) Host memory sharing method: This is a method of accessing the host memory 8 from both the host processor 7 and the local processor 10. The local processor 10 controls data transfer between the host memory 8 and the local memory 12.

(3) I / O port system: A system in which the host side and the LAN control board have an interface via the I / O port, and data transfer between the host memory 8 and the local memory 12 is performed by the host processor 7 through the I / O. The local processor 10 reads (writes) the information written (read) from the port from the I / O port in synchronization with the information. I / O port is host interface 11
It is inside. As shown in FIG. 5, the feature of this system is that the data transfer between the host memory and the local memory has two phases, namely, the transfer 24 between the host memory 8 and the I / O port, and the I / O port. The point is that the transfer 25 between the local memories 12 is performed separately. In this case, since the respective transfer control is performed by the host processor 7 and the local processor 10, the throughput becomes worse as compared with the other two methods (1) and (2). However, this method has an advantage that the amount of hardware can be reduced as compared with the methods (1) and (2).

Now, provided that the LAN control board 6 including the RF modem 15 is realized by one board, the RF modem occupies an area of about 1/3 to 2/5 of the board, and therefore other hardware parts By adopting the above-mentioned I / O port system that can reduce the size of the data and reducing the data buffer area, it is advantageous to reduce the capacity of the local memory 12 as a whole. On the one hand, from the viewpoint of throughput, according to the calculation, each of the above methods is (1) :( 2):
There is a relationship of (3) = 1: 0.8: 05, and method (3) is the worst.

The present invention adopts the I / O port method described above, and connects the acceleration board 17 to the LAN control board 6 in order to compensate for the decrease in throughput.

Specifically, both local buses 13 and 16 are connected.
The peripheral interface 20 controls the interface between both boards. The memory on the acceleration board is commonly accessible by the host processor 7 and the local processor 10. That is, the acceleration board has the host interface of (2) above. The 2-boat control unit 18 controls memory access competition between processors.

By using the acceleration board, the data flow is
The conversion is performed as shown in FIG. That is, the frame 21 received from the transmission path 2 is directly transferred to the shared memory 19
28 (controlled by the LAN controller 14), and from there to the host memory 8, the host processor 7 controls.

As described above, adding an acceleration board, LAN
The transmission / reception buffer capacity in the control board can be increased, and
Since it has an interface of the shared memory system with the host, the system has the highest throughput as the LAN control board.

In the present embodiment, the interface between the acceleration board and the host is described in the local memory sharing method of the first proposal, but it may be the host memory sharing method of the second proposal.

It is obvious that the present invention can be applied to the fields of baseband LAN and general data communication in addition to broadband LAN.

〔The invention's effect〕

According to the present invention, the throughput is improved by adding the acceleration board to the LAN control board which does not have sufficient throughput, so that the cost is low for the station such as a personal computer which does not require high throughput. It is possible to provide a LAN control board, and for various servers that require high throughput, there is an advantage that a high throughput LAN control board can be provided by adding an acceleration board.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the system configuration, and FIG. 2 is a LAN.
Hardware block diagram of control board, FIG. 3 is a diagram showing an example of frequency allocation, FIG. 4 is a diagram for explaining a frame format flowing through a transmission line, and FIG. 5 is an interface between a LAN control board and a host. FIG. 6 is a schematic diagram of a host interface when an acceleration board is added. 1 ... Frequency converter, 2 ... Coaxial cable, 3 ... Divider, 4
... host, 5a, 5b ... station, 6a, 6b ... L
AN control board, 7 ... Host processor (HP), 8 ...
Host memory (HM), 9 ... System bus, 10 ... Local processor (LP), 11 ... Host interface control unit (HI), 12 ... Local memory (LM), 13
… Local bus, 14… LAN controller (LAN
C), 15 ... RF modem, 16 ... Local bus, 17 ...
Acceleration board, 18 ... 2-port control unit, 19 ... Shared memory, 20 ... Peripheral interface, 21 ... Frame, 22 ... Target address field (DA), 23 ... Source address field (SA), 24 ... HM-HI data transfer , 25 ... HI-LM data transfer, 26 ... L
M-transmission line data transfer, 27 ... HM-shared memory data transfer, 28 ... Shared memory-transmission line data transfer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuhiko Hirata 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi Ltd. System Development Laboratory (72) Inventor Takahiko Nishizawa 1406 Hasunuma, Omiya-shi, Saitama Yagi Antenna Co., Ltd. Omiya Factory (56) Reference JP-A-61-236242 (JP, A) JP-A-62-89149 (JP, A)

Claims (1)

[Claims] 1. A host processor (7) and a host memory (8) are connected by a system bus (9), and a communication control device is connected between the system bus and a transmission line (2), and the communication control is performed. In a data communication control system in which data transmission / reception between the host processor and a transmission line is controlled by the device, the data communication control device is a protocol connected to the transmission line via a line interface (15). A control device (14), a host interface device (11) connected to the system bus, a local processor (10) connected to the protocol control device and the host interface device via a local bus (13), The two-port shared memory (19) is connected between the local bus and the host memory, Comprising controlling access to memory 2 port control unit (18), and is the host processor transferring the data transmitted and received between the host memory (8) and the shared memory (19) (7)
A data communication control method, wherein transmission and reception of data between the shared memory and the transmission path (2) are performed by the protocol control device (14).