JPH065710A - Semiconductor memory device and defective memory cell relief circuit - Google Patents

Abstract

PURPOSE:To prevent a malfunction caused by a resistance value after a fuse has been blown by a method wherein a redundant memory is started by selecting the fuse, to be blown, which corresponds to either 1 or 0 inside an address. CONSTITUTION:A P-channel transistor PCH-1 is energized by a starting signal START UP 68 and generates a REN-signal. Low-active address signals AF-0 to AF-11 and a REN signal are logical-operated by NOR gates 70, and output signals are obtained. The signals are output, via programmable fuses F0 to F11, to N1, N2 and N3 which have been connected to a wired OR. In addition, they are logical-operated by a NAND gate 65, and an address fuse coincidence signal is obtained. Thereby, it is judged that a device uses not a defective memory but a redundant memory. It is possible to prevent a malfunction due to the parallel combined low-resistance value of a resistance value with which an ordinary blown fuse is provided, the time to discharge a common contact is not required, and an extremely-high-speed address coincidence signal can be generated.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to integrated circuits, and more particularly to integrated circuit devices formed in semiconductor substrates, such as memory devices such as dynamic random access memories.

[0002]

2. Description of the Related Art The development of dynamic random access memory (DRAM) type large scale integrated circuit semiconductor devices is well known. For example, Lao US Pat. No. 4,05
It has evolved over the years from the 16K DRAMs shown in US Pat. No. 5,444 to the 1MDRAMs shown in US Pat. No. 4,658,377 to McElroy and further to 4M and 16MDRAMs. 6 on a single memory chip
64M DRAM in which more than 14 million memory cells and their peripheral circuits are integrated is currently in the prototype stage and next-generation D
Mass production is planned for RAM. Currently 64 MDRA
Designers face various problems in designing M-type ultra large scale integrated circuit (ULSI) semiconductor memory devices. For example, one concern is to eliminate memory cell defects. Development of very large DRAMs, such as the planar capacitor cell disclosed in Kuo U.S. Pat. No. 4,240,092 and the trench capacitor cell disclosed in U.S. Pat. No. 4,721,987 to Bagri et al. This has been promoted by the reduction of memory cell geometries, but in order to achieve high integration of 64M DRAM or more, extremely small geometries are specifically manufactured by using sub-micron (less than one millionth of a meter) technology. In addition, the reduced size in the future has caused particles, which have not been a problem in the conventional manufacturing process, to increase the number of defective circuits and defective devices.

Referring to FIG. 1, known lithographic techniques can be used to form electronic circuits on a semiconductor silicon chip. The surface of the chip 10 is US Pat. No. 5,015, granted to Texas Instruments Incorporated on May 21, 1991.
There is a DRAM (Dynamic Random Access Memory) array 12 manufactured by CMOS submicron technology as described in US Pat. No. 7,506. This DRAM circuit includes, for example, a 16-megabit dynamic random access memory. The memory array 12
There are four memory quadrants 12a to 12 each having 4 megabits on the effective surface of the semiconductor chip 10 formed of silicon.
It is divided into d. Each memory quadrant 12a-12
16 memory blocks 1 each having 256K bits
Have six. Each memory block 16 has 1,024 bit lines 17 (or columns), 1,024 sense amplifiers and 256 word lines 19 (or rows). The column (COLUMN) decoder (column decoder) 18 is
It is provided adjacent to each memory array quadrant along an axis 23 extending in the lateral direction of the chip. Row (ROW) decoders (row decoders) 20 are provided adjacent to each memory array quadrant along an axis 25 extending in the vertical direction of the chip. Peripheral circuits 22, including input and output buffers and devices such as timing and control circuits, are formed around the periphery of the substrate and are centrally located along an axis extending laterally of the chip, to which bond pads 24 are attached. Are arranged centrally along an axis 25 extending in the longitudinal direction of the chip.

FIG. 2 is a plan view of a portion of the memory array 12. The memory cells of memory array 12 are of the improved trench capacitor type obtained by submicron technology. The memory cells are about 4.8 square micrometers (μm 2) and are provided at intervals of 2 word lines. The bit line 17 is formed of three-layer polycide in order to improve noise tolerance. The word lines 19 are made of polysilicon and are connected every 64 bits. Redundant circuits have traditionally been introduced to repair defective memory arrays. A redundant circuit effective when a defective memory array exists in rows and columns of memory cells arranged in a matrix in the memory array is composed of spare memory cells that replace the defective memory array in row or column units. There is.

FIG. 3 is a perspective view of a part of the memory array 12, and FIG. 4 is a sectional view thereof. The interconnect metal layer 41 is arranged in a strip. Oxide layer 47 separates upper metal layer 42 from lower metal layer 49. Metal layer 49
Is a multilevel interconnect metal 49 that provides a connection for the bit lines. An oxide layer 51 underlies the interconnect metal 49 and isolates the silicided bit line 17 and the metal layer 49. Interlayer insulating oxide layer 53 is below bit line 17 and above word line 19a. Word line 19
a forms the gate of the pass transistor 43. The word lines 194 and 196 are the upper trench capacitors 44 and 45.
And is connected to another trench capacitor not shown in the drawing. They are separated from the polysilicon field plate 48 by an oxide layer 55. N + type diffusion part 5
9 is provided below the bit line contact 15 in the P-tank 60 between the word line 19a and the trench capacitor 44. Under the electric field plate 48, the trench capacitor 4
In the spatial region between the trenches that separates 4, 45, there is a nitride layer 61. There is an oxide layer 62 between the nitride layer 61 and the P-tank 60. The trench capacitors 44 and 45 are P-
It passes through the tank 60 and is located on the P-type substrate of the silicon wafer 10. The implanted arsenic layer 50 outside the walls of the trench capacitor forms the N + storage node of the capacitor. The walls of the trench capacitor contain oxide and nitride layers 52 that act as a dielectric layer between the arsenic trench wall implant and the polysilicon field plate 48. Pass transistor 43 and trench capacitor 44
Form a memory cell 46. This memory cell 46
Bit lines, word lines, and gate oxide films of passing transistors associated with the above have had large dust particles and defects in memory cells due to crystal defects, but small dust particles that did not become a problem when miniaturization further progresses in 64M DRAM and the like. Alternatively, a crystal defect may cause a defect such as a defective memory cell or a short circuit between adjacent word lines or a leak of interconnection lines of the first and second levels.

FIG. 5 is a three-dimensional view of the state in which the chip 10 is resin-sealed, and the resin sealant 26 is shown as transparent for understanding the structure. In addition, the assembly method of this structure is shown in FIG.
Shown in. The chip 10 has two strips of polyimide tape 32 underneath the leadframe 30.
Is attached to the lead frame 30. The dimensions of the resin-sealed package are approximately 400 x 725 mils. Further, FIG. 7 shows a sectional view of a state in which the chip is mounted.

FIG. 8 is a diagram showing the names of bond pads. Both procedures for the x1 and x4 options are also shown. The EXT BLR is a pad for so-called in-house, which is used only in the manufacturing stage. FIG. 9 shows a pin arrangement diagram of these x1 and x4 type devices. High-speed access such as CBR, CAR, static column mode, etc. is controlled by the relationship between the RAS_ and CAS_ signals. It is a 28-pin small outline J lead type package (SOJ). It is ideal that the bond pads of the address signal are arranged adjacent to each other from the requirement of the decoder function. However, in reality, since the bond pads of the address signals A3 and A9 are widely separated, the signal arrival time may be delayed by about 0.8 ns between the address signals. This affects timing adjustments that are critical to decoder function.

Regarding the matching circuit of the redundant memory address,
When a part of the memory cells has a defect, even if most of the memory cells function normally, it is judged that the device as a whole has no value. A chip determined as a defective product as a result of the multi-probe in a semiconductor slice state before a plurality of chips are cut is discriminated from other non-defective chips and then discarded. Further, if it is judged to be defective during the electrical inspection after the device assembling process, it is similarly discarded.
Therefore, it is necessary to replace the memory containing the defect or the memory related to the defect with another memory cell called a redundant circuit. When a defective memory is detected as a result of the multi-probe test, the address corresponding to the defective memory is recorded, and a mechanism that complements the redundant memory cell before the memory including the defective cell is used is determined by blowing the fuse. Will be realized. The use of redundant memory or the generation of match signals for defective memory addresses is extremely important in determining the performance of the overall device. That is,
This is because the performance of the device is determined by the deteriorated specifications when the replaced redundant memory is deteriorated in terms of speed when compared to the case of accessing the normal memory. In addition, the performance of the device will be deteriorated even when extra power consumption occurs by using the redundant memory. Thus, the configuration of the redundant circuit, and in particular the address match signal generation circuit, can form an integral part of the DRAM and provide substantial specifications for those devices and systems in which it is used.

FIG. 10 shows a conventional address matching circuit. It exists in the path between the transistor selected from the plurality of transistors and the common node between the transistors. It is a known technique to blow a laser or apply a high voltage so that the fuse of a portion corresponding to a predetermined address bit is blown. The output of the inverter 8 is used to signal the activation of the redundant memory row. The gate of the pull-up P-channel transistor 3 is connected to the output of the inverter 5, and the input of this inverter 5 is connected to the inputs of the fuse 4 and the inverter 8, respectively. The logic circuit shown in the left half of FIG. 10 shows address factors F0 to F23. These address factors are input to the inverter surrounded by the broken line 6. The circuit shown here can be generally configured in a small scale in terms of circuit area, but on the other hand, in order to adjust the variation in the arrival time of the address signal, a match signal is generated at the timing when the farthest address signal is fetched from the decoder circuit. Must be generated. Therefore, the operation speed is relatively slow.

FIG. 11 shows an address matching circuit which can be used in a conventional 16MDRAM. The circuit that adjusts the address signal in the previous stage is a field effect transistor 166.
Is connected to the field effect transistors 168, 170 and 172. Further, these fuse circuits include an inverter 162 connected to the fuse 164. Transistor 172 receives the address unit signal on one terminal, while transistor 170 receives the complement of its address signal on the one terminal. Transistors 170 and 17
2 generally operates at a lower threshold voltage than the other transistors shown in FIG. The fuse is blown when the selected address bit corresponding to the signal sent to transistor 172 is at a logic "1" or high logic level to activate the redundant memory cell corresponding to the selected address. However, when the address bit corresponding to the signal sent to transistor 172 is at a logic "0" or low logic level, the fuse remains unblown. When the fuse 164 is not blown, the gate of the transistor 170 is energized and the transistor 170 is
It should be noted that the A_ signal on the terminal of is transferred to the address factor. On the other hand, when the fuse 164 is blown, the gate of the transistor 172 is energized,
The A signal is transferred to the address factor. After the gate of the transistor 166 receives the start pulse, signals are generated as address factors RA0 to RA11, which are respectively input to one inverter of the plurality of inverters 6. In order to activate the redundant memory cell, the address factors RA0 to RA11 are all logic "0".
It is necessary to generate a low logic level signal at the output of the inverter 8 which is at the level. Although the fuse 4 is shown here, this is not always necessary, and the program can be performed by fusing the fuse 164 in the address signal adjusting circuit in the preceding stage. Therefore, the circuit can operate by providing either one of the fuse 4 and the fuse 164. Further, this circuit is generally large in scale because the circuit for pre-adjusting the address signal requires a number corresponding to the number of address bits.
Since the address can be input by gating the transistors 170 and 172, there is no need to adjust the timing. Therefore, it is suitable for high-speed operation.

FIG. 12 shows the configuration of another address matching circuit used in the 16 mega DRAM. This is similar to the structure of the address coincidence circuit in FIG. 11, but the connection structure of the P-channel transistor driving the common node is different. That is, in order to stabilize the match signal, the address match detection signal is fed back by the inverter to gate the P-channel transistor. If the redundant memory activation signal PC is applied intermittently, it is possible to precharge the nodes that commonly connect the fuses. By applying an address bit signal to the gate of the N-channel transistor, this common node can be discharged depending on whether the fuse is blown. However, in a large-scale memory integrated circuit having a large number of address bits, the electrical resistance after the fuse is blown becomes a problem with respect to the mechanism for decoding all addresses. Even when it is not intended to discharge the common node by the combined resistance of the fuses connected in parallel, the common node is discharged,
It causes malfunction. Also, when starting the device, P
The driving capability of the channel transistor must be increased, which also increases the area of the device.

Other objects, advantages and features of the invention will be apparent to the person skilled in the art from the following detailed description with reference to the drawings of an embodiment of the invention taken by way of example.

[0013]

The main problem in the construction of the above address redundancy matching circuit is that the resistance value after the fuse is blown is about 80 to 100 kilo ohms (KΩ) as in the conventional case. Is to stably operate and generate a coincidence signal at high speed. Therefore, there is required a configuration of a redundant address matching circuit that prevents malfunction caused by a resistance value after fusing of a large number of fuses or a resistance value lower than a predetermined resistance value due to insufficient fusing.

[0014]

The structure of the redundant address matching circuit of the present invention is such that the redundant memory is activated by selecting the fuse to be blown corresponding to either 1 or 0 in the address. And a means for applying an address signal to the fuse through a logic gate in response to the redundancy mechanism activation signal, and an AND or NAND logical operation of the output logic values of the fuses connected to the common node and corresponding to the input address bits. This has the function of generating a redundant address match signal.

[0015]

When the address matching circuit configured as described above is activated, the logical operation value by the "NOR" gate of the output logic of the P-channel transistor and the logical value of the input address bit is further passed through each fuse to "NAND". "Since the logical operation is performed by the gate, it prevents the malfunction due to the parallel combined low resistance value of the resistance value of the normal blown fuse, and it generates the extremely high-speed address match signal because the time to discharge the common contact is not required conventionally. it can.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment according to the present invention, a memory device has a plurality of memory arrays having memory cells arranged in rows and columns and having redundant row groups of memory cells replacing defective row groups, and memory cells. A support circuit for reading information from the memory cell and writing information to the memory cell is provided, and the support circuit responds to a defective row group address of the memory cell to generate a redundant row of memory cells only in the memory array having the defective row group of the memory cell. It includes a row redundancy circuit to select. Preferably, the row redundancy circuit includes a two stage row redundancy decoder programmable by holding the fuse to be programmed to hold the defective row address and programmable to hold information identifying the memory array containing the defective row of memory cells. I'm out.

According to another embodiment of the present invention, a memory device integrated on a single semiconductor substrate has a plurality of memory cells arranged in rows and columns and redundant column groups of memory cells replaced with defective column groups. And a column redundancy circuit for selecting a redundant column group of memory cells only in a memory array having a defective column of memory cells in response to an address of the defective column group of memory cells. .
Preferably, the column redundancy circuit is programmable to hold a defective address and is programmable to hold information identifying a redundant column (COLUMN) that identifies the memory array containing the defective column of memory cells. Includes a possible column redundancy decoder. Memory device
A first redundant decoder programmable to hold the address of the defective row and receive the row address to generate a redundant row decode signal and a redundant row factor signal, and to retain the location of the array containing the defective row and provide redundancy. A second redundant decoder programmable to receive a row decode signal and generate an array select signal, a redundant row factor energizing signal for the second redundant decoder, an array select signal for the second redundant decoder and a memory cell. Advantageously, a redundant activation circuit is included that is connected to the redundant row and activates the selected redundant row of memory cells in the memory array having a defective row of memory cells.

A memory device according to the present invention includes a row redundancy circuit and a column redundancy circuit and may include a memory device as claimed in any of the claims.

In another embodiment of the present invention, a method of repairing a defective memory cell in a semiconductor memory device having a plurality of memory arrays includes programming a first circuit with an address of the defective memory cell to provide the defective memory cell. Programming the second circuit according to the location of the memory array having the memory array and selecting a redundant memory cell in the memory array having the defective memory cell to receive the address of the defective memory cell. It is preferably a redundant row memory cell. Alternatively, the defective memory cell is a defective column cell and the redundant memory cell is a redundant column cell.

As part of the present invention, a typical two-stage decoding circuit for a semiconductor memory device is disclosed. The redundant row decoder is a two-stage decoder that is programmable to hold the address of the defective row and has a first redundant decoder that receives the row address and generates a redundant row decode signal and a redundant row factor activation signal. is there. The second redundant decoder is connected to a redundant row of memory cells which receives the redundant row decode signal and outputs a signal for selecting a memory array, and adds a third permission stage responsive to the redundant row factor energizing signal and the array select signal. By doing so, the selected redundant row of memory cells of the memory array including the defective row of memory cells can be activated. The redundant column decoder can be programmed to hold the address of the defective column. They receive the column address and generate a redundant column decode signal and a redundant column factor activation signal. The second redundant column decoder can be programmed to hold the position of the array containing the defective column. It activates a selected redundant column of memory cells including a defective column of memory cells by receiving a redundant column decode signal and adding a third permissive stage responsive to the column factor activation signal and the array select signal. be able to. The decoding circuit identifies the memory portion in need of repair and uses the available memory cells more efficiently. Here, a memory chip will be described as one embodiment of the present invention.

FIG. 13 shows a 64-megabit dynamic random access memory chip called 64MDRAM. The chip is divided into memory quadrants divided into 8 equal 8 megabits. Each of the eight memory quadrants contains eight 1M bit memory blocks. Each memory block is divided into 512K bits. A column decoder (C.dec) is arranged in the center of each memory quadrant along an axis extending vertically when the chip is viewed from above. Row decoders (R.dec) are arranged along the laterally extending axes of the chips adjacent to their corresponding memory quadrants. Input / output buffer (A.buffer
r, I / O buffer) and timing (SRt)
imager, Row. clock,) and control circuit (Ro
Peripheral circuits including devices such as w red) are centrally located along both the horizontal and vertical axes of the chip. In addition, the bond pad is centrally located along the vertical axis of the chip.

14 to 16 show the general characteristics of a 64M DRAM as follows, the device being supplied by an external power supply VDD, which is typically 3.3 volts. Internal power supply voltage regulator (VPPge) on the same chip
n) supplies the memory array with one half of VPP, 1.65 volts, to reduce the power consuming tunnel hot carrier effect. It also supplies 4.0 volts to the peripheral circuits. The substrate is reverse biased to minus 1.5 volts. This configuration is programmable by bonding with x1, x4, x8 and x16 bit configurations. This option can be selected by connecting a predetermined bond pad to VSS at the manufacturing process stage as in the prior art by connecting a bonding wire. However, since the memory capacity is larger than that of the conventional memory, the memory capacity of 3 in FIGS.
4-pin packages can be provided in x1, x4 and x8 bit configurations. For the 54-pin package shown in FIG. 16, a device having a × 16 bit configuration can be provided. These enable the enhancement page mode to be optimally selected, with a combination of the metal mask programmable option for the write (data mask) operation for each bit and the bonding option. Furthermore, an option suitable for the refresh method is 4096 cycles (4K) refresh or 819 in 64 ms.
It is to select a 2-cycle (8K) refresh. This DRAM can be programmed for 4K or 8K refresh with bonding options. Choice of options is x1, x4, x8 and x
It can be achieved in a similar manner to that used for the 16-configuration option selection. DRAM has many test design features. Test mode entry 1
Performed through WCBR without key address for 16x internal parallel test with modal data comparison. Test mode entry 2 is a WCBR with a key address and overvoltage after that (8 volts on A11). To exit test mode, refresh cycle (C
BR or RAS only). Test mode entry 1 is an industry standard x16 parallel test. This test is similar to that used in 1 MB, 4 MB and 16 MB DRAMs, except that 16 bits are compared simultaneously instead of 8 bits. Test mode entry 2 contains a number of tests. Includes 32x parallel test with data comparison and x16 parallel test with data comparison. The stress test and the VDD margin test of the storage cell are performed from the external VDD to the internal VAR through the P-channel transistor device.
Allows connection to Y and VPERI equipment power lines. Other tests include redundant signature test, row redundant row call test, column redundant row call test, word line leak detection test, simultaneous clear test, reset to normal mode. This DRAM includes a test valid method to indicate if it remains in test mode.

FIG. 17 illustrates a redundancy mechanism for compensating for a defective memory cell 202 in a 64 MDRAM. This is the redundant memory 2 that normally operates the defective memory related to the row address.
It is carried out by substituting 04. The 32 fuse decoders 208 commonly connected to the address bus 206 arranged in the center of the chip are arranged in the center of the chip. This does not involve the routing of extra address bus lines. That is, when the all-any (ANY TO ANY) redundancy mechanism is used, the redundant activating lines and the redundant selection lines are used when the memory quadrants at the farthest positions, for example, the redundant memories of the first and fifth quadrants are used mutually. The shortest line is enough. Therefore, since the chip area can be effectively used and the shortest redundant energizing line and the redundant selecting line are sufficient, the timing delay can be shortened and the device access time can be shortened. On the other hand, if the fuse decoder 208 is placed around the periphery of the chip instead of the center of the chip, it is difficult to route the redundant energizing line, the redundant select line and the address bus that are commonly used, and wasteful area is consumed. Will be done. 512 Kbit memory block 3
For 04, there are four redundant rows 306 (omitted to two in the drawing). These four row lines can be used simultaneously. 32 decoders per redundant row can be programmed arbitrarily, with a row address of 13 bits per redundant row decoder. Fuses F0 to F11 (see FIG. 36) are used for row redundancy programming, up to 1 for a single repair.
Two fuses are blown. Row redundancy uses an ANY TO ANY programmable scheme for efficient yield. By using all of the redundancy functions, 64 redundant rows existing in one quadrant can be selectively assigned to all quadrants including the quadrant. Therefore, a fixed method or a semi-fixed method (FLEXIBLE F) in which a redundant memory is provided for a specific memory block is provided.
The redundancy can be increased to about 6 times that of the USE DECODER method. In addition, the predecoder 308 for the memory quadrant is used for the memory block in each quadrant.
The number of fuses F0 to F11 and the number of decoders 208 can be optimized by programming the fuse decoder 208 for each of the memory 312 row addresses. Although FIG. 17 discloses the redundancy function for the row address, it is also possible to program the redundancy function for the column address with the same configuration. In addition, a two-stage programmable pre-decoder 308 and fuse decoder 208 perform two-stage decoding so that it can be quickly determined whether or not to use a redundant row. A comparison of the row redundancy functions is shown in Table 1 below.

[0024]

[Table 1] FIG. 18 shows a model relationship from A to E in which the horizontal axis represents the number of defective memories in the same area and the vertical axis represents the redundancy. A shown by a broken line is a model of 64M DRAM, solid line B
And E show other models of 64M DRAM. Although the memory cells have the same area, the redundancy is different depending on the quadrant, the word configuration, and the arrangement of bit lines. Also, C and D are 1
This is a redundant configuration that can be used for 6MDRAM and the like. It should be noted that all the redundancy calculations are performed based on the number of defects per unit area. Here, the all-arbitrary method is a yield 80 which is a standard for the maturity period based on the learning curve of the semiconductor device.
It should be noted that more than% steps can tolerate about four times as many defective memories as before. That is, for defective devices including defective memory cells that are four times as many as the number of defects that cannot be redundant in the past, 20% of the chips are discarded by using the all-arbitrary method. The finished product can be obtained through.

FIG. 19 shows a CBR detector. CBR
In addition to checking the (CAS BEFORE RAS) state, an external TTL logic level CAS_ signal (CAS bar signal) is converted to a CMOS logic level to generate an internal CAS clock CL1_. Redundant address match signal is C
It can be started by receiving the redundancy mechanism activation signal after BR detection, so it will not decode the wrong address. The first part of the circuit is TTL to CMOS
To the converter, XTTLCLK. It is an internal RAS
Controlled by the clock, RL1, signal conversion only begins when RL1_ is brought high. The feedback of the internal CAS clock CL1_ allows XTTLCLK to remain active even when RL1 changes state from active high to low. This configuration allows the device to operate in extended CAS (extended CAS) mode, ie CAS_ remains active low after RAS_ goes high. However,
The CL1_ period loop is gated by the power-up signal RID before entering the converter. This avoids unnecessary switching of the converter during power up. The second part of the circuit samples the CAS_ signal when RL1 goes high. If CAS_ is low at this point, ie, CAS_ falls before RAS, CB
REN_ goes active low, indicating a CBR cycle. RBCEN_ remains high, but if CAS_ is high, there is an inverse logic signal value at the output and the normal RB
The C (RASBEFORE CAS) cycle is shown. It should be noted here that latching is not performed and sampling continues as long as RL1 is at a high level. If the CAS_ signal changes state during this cycle,
The outputs CBREN_ and RBCEN_ change together. However, these subsequent outputs are invalid (DON'T
CARES), the initial output is latched in the RBC circuit and a programmable delay is used to control the start of this sampling.

20 and 21 show RBC_RESET.
(RAS BEFORE CASRESET) circuit is shown. As discussed in the CL1 circuit, CBREN_ and R
With the initial output of BCEN_, the type of operating cycle of the device, namely RAS before CAS (RAS BEF).
ORE CAS or CAS Before RAS (CA
S BEFORE RAS). Therefore, it is necessary to capture and hold (latch) the initial output over the entire cycle. This latching is done in the RBC circuit. The RBC_RESET circuit resets the latch at the end of the cycle to make the device ready for the next cycle. Besides latching CBREN_ and RBCEN_, RBC is RA for gating the row address.
Generate an N signal. By activating the redundant address coincidence signal generating circuit in synchronization with the RAN signal, it is possible to specify at an early stage whether to select a normal memory cell or a redundant memory. RBCEN_ and CBR
The latching of the EN_ signal is performed by the two interlocking latches XRS1 and XRS_3. In the precharged state, one of the two latches is excited by an active low signal from RBCEN_ or CBREN_. The excited latch then locks the excitation of the second latch. In FIG. 12, the lock goes low at the end of the RAS_active cycle, resetting the latch and locking the RBC RE.
Generate a SET pulse. RLRST_ is a precharge signal generated at the rising edge of RL1_ after a predetermined delay. In the normal (STANDARD) operation, the RBC for the RAS before CAS (RAS BEFORE CAS) cycle or the CAS before RAS (CAS B) is used.
The CBR for the EFORE RAS) cycle is set to the high level. The CBR_DFT signal follows the CBR logic, but is not used in normal operation so there is no delay in the normal cycle. A similar signal is generated from CBR with a falling edge delayed. This is the CBRD signal and is used as the incremental clock signal for the internal counter of the CAS before RAS. The falling edge of this signal causes the increment. Thus, by delaying the internal counter, the device is provided sufficient time to turn off its row address buffer before changing the internal counter address, thus avoiding introducing an incorrect address into the memory array. . In the refresh mode in which the CBR is continuous, the redundant memory address decoder can determine the coincidence signal whether to fetch the incremented address and switch to the redundant memory without fetching the output of the row address buffer. However, the preparation of the match signal is limited to the selection of the row address line at the start of the next cycle. When the device is in DFT ROW COPY mode, the XRS_3 latch acts as an inverter at node N2 to output CBR_ and CBR is de-energized to a low logic level. This is normal unless both node N2 and RBC_RESET are high logic at the same time. Since this state does not occur in a normal sequence, a long refresh interval can be guaranteed. 64M DRAM has a remaining refresh interval longer than the CBR refresh period after individually performing CBR refresh including delay for memory cells for all row addresses. It is advantageous to access the memory in normal cycles with no delay.
With this setting RBC is still latched and CBREN
Although the _ signal is unlocked (locked off), it is necessary to have the output CBR_DFT because CBREN_ is valid during the entire cycle in CAS before RAS operation.
Therefore, CAS_ is kept low as long as RAS_ is low. Both CBR and CBRD release their energization when they go high in this test mode. When a CAS Before RAS cycle is performed in this test mode, they are de-energized to prevent the internal CBR counter from being used as a row address. The reset in this test mode is done by RBC_RESET within the normal RAS before CAS cycle at the end of the active cycle. During the CAS-before-RAS cycle, C at the end of the active cycle
The logic value of BREN_ is set to a high level and reset is performed.
The other part of the circuit is ROW ADDRESS ENABL
Generate E signals, RAN and RAN_. These signals are generated during any active cycle. Representative R
For BC type cycles, these signals need to be generated as fast as possible. To that end, the falling edge of RBC_EN is used to trigger the transition of the RAN signal. To keep the RAN signal active during the RAS_precharge period, the RBC_ signal is used to keep the RAN signal active. For CAS-before-RAS operation, it is necessary to delay execution of the RAN signal to ensure that the address buffer functions properly. In these two circuits, the power-up signal RID is used to preset the initial state of the latch. Delay stage, XSD
EL1 delays RAN claim from CBR_ and RAN
Gives sufficient time for the CBR internal address to reach the row address buffer before activating the buffer.
Therefore, it is possible to prevent erroneous address data from being fetched from the row address buffer, and also to prevent a malfunction of switching the redundant memory. RAN_ is RBC_RESE
Also used to reset T.

FIG. 22 shows PADABUF (PAD AD
3 shows a DRES BUFFER circuit. This is because the data from the address signal pin is multiplexed to obtain the row address RA.
It is for latching as P_X and column address CAP_X. This signal can be treated as an input to the redundant address decoder. In the first stage of the circuit, the TTL level signal of the address is converted into a CMOS level signal when the internal RAS signal, RL1_, goes low.
The delayed RAS signal, RL2, is then latched at the row address. It also has an address non-latching delay by RL2. This gives the device time to override the precharge before the address is activated. When invalidated, the address RAP_X is always "1" and R
L1_ is high when not valid. On the other hand, CL
NA_ is set to low level and the address is propagated as CAP_X, and the column address can be used even before CL1_ is set to low level. As a result, the device will operate in the enhanced page mode (ENHANCE PAGE MO
DE) and AS CL1_ goes low, latching the column address into CAP_X. Finally, RL
During the precharge cycle in which 1_ goes high, XT
The TLADD converter is suppressed and is not affected by the external change address, but CAP_X is maintained.

FIG. 23 shows RADR (ROW ADDRE).
SS DRIVER) circuit. This is a row address driver. The control signal, RAN, starts driving the address signal. Not only a driver, but also an external latch row address and CB before driving
R Plays a role of multiplexing the internal counter address.

FIG. 24 shows BITCOUNT (CBR I
Fig. 3 shows an NTERNAL BITCOUNT circuit. 12
A set of this circuit is connected in series inside the device.
It acts as a 12-bit internal address during the CBR cycle. The circuit is a flip-flop that is excited on the falling edge of its input signal. For the least significant bit, the input is the CRBD signal and the output is the LS of the CBR row address.
B, and is also the input to the next set of BIT COUNT circuits. It is connected in series until it forms 12 CBR address lines. Such a circuit provides an incremental binary count based on the pulse of CBRD.

FIG. 25 shows RF & RF (CODE ROW).
FACTOR) circuit. The row factor is for encoding the row address into a format used in a later row circuit, where the ROW addresses 2 through 7 and their complements are encoded by an "AND" operation to produce a 12 bit row factor. Occur.

FIG. 26 shows RLEN (ROW LOGIC).
ENABLE) circuit. The purpose of the RLEN signal is R
LXH, that is, timing the rising edge of the main word line driver with respect to the row factor. In addition, R
The LEN circuit notifies the precharge RLRST_ signal and the SED that notifies the BL to BL_ equalization process.
Generate IS. RLEN is commonly referred to as ROW FACTOR DETECTOR. It uses row factors RF4 to RF7 to detect the completion of row factor encoding. When the encoding completion is detected, the “NAND” gate ND1
And ND2 to activate addresses RA11 and RA_11
To generate RLEN_R and RLEN_L, respectively. These are signals that excite the main word line driver, RLXH_R or RLXH_L. Only one of the two drivers is activated in one quadrant during normal operation. However, in DFT mode, where all eight partitioned quadrants of the array need to be accessed simultaneously, the TL8BS is highly active. This causes both RLEN_R and RLEN_L to be active at the same time. Therefore, the main word line driver, RLXH_R
And RLXH_L will be activated together. When row factor encoding is complete, the RLRST_state is reset from low to high logic level. On the other hand, at the end of the active cycle, the falling edge of RL1_ causes RLRST_ high logic level to go low after a programmable delay. In this way, the start of another precharge cycle will be notified. The last element of the circuit is SENDING EQUALI
ZATION DISABLE, SEDS. RL
Like RST_, they are used to signal the stop and start of the BL to BL_ equalization process. However, only the row factor encoding that triggers the stopping of the BL and BL_equalization processes is used. This is because a large current is generated in the fuse decoder in the redundant address match signal generator that decodes the row factor signal together with the redundant address, which adversely affects the reliability of the device. Therefore, the process will stop 4 nS after the row factor encoding is complete. Note that FIG.
Such a fault cannot occur only in the redundant address coincidence signal generating circuit of. Next, when RLRST_ becomes low active and the precharge cycle is started, SED
The S signal is reset to logic "0" with a delay of 4nS.
Thus the equalization process is started. Device is ROW
In the COPY DFT mode, SEDIS transitions from a low logic level to a high logic level in the first cycle like any normal cycle. However, when the active cycle is complete, RLRST_ goes to a low logic level and SEID continues to inhibit high logic states throughout the inactive cycle and subsequent cycles. This is due to the active TLRCOPY that nullifies the reset signal from RLRST_. Without the equalization process, the voltages on BL and BL_ will remain split, allowing the data on BL or BL_ to be dumped to another row during the DFT row copy operation.

FIG. 27 shows RLXH (ROW LOGIC).
X WORD HIGT) circuit. Output RLXH
RLXH, which is a boosted line of low logic that drives the word lines and redundant word lines, is also called the main word line driver. The circuit operates as follows.

AT PRECHARGE: Node N4
Is (Vperi) due to the invalid logic of RL1_ and RLB.
-Vt) is idled. Next, the boosting capacitor MN11 is connected via MN7 and MN8 (Vperi
-Vt) is charged. Further, the node N3 of the capacitor MN13 is set to the ground level. Furthermore, the transistor MN5
As a result, the word line driver RLXH, which is set to low logic as RLEN_0, becomes high logic level.

START OF AN ACTIVE
CYCLE: RL1_ becomes a low logic and becomes “NAN
D ”gate ND1 is RLB, ROW LOGIC BO
It can be prepared as a circuit that responds to the OT signal.

COMPLETION OF FACTO
RS ENCDING: RLEN_0 goes low active. Due to the high stray capacitance of the N-channel transistor MN4 from the nodes N1 to N4, the node N4 becomes (Vperi
+ Vperi-Vt). When RLEN_0 becomes low logic, N1 changes from low logic to high logic. When N4 is boosted, the node N5 of the capacitor MN11 is at the full Vpe
It is charged up to ri. The node N3 of the capacitor MN13 is charged to Vperi via MN9. Further, the transistors MN6 and MN4 are turned on, and the word line driver becomes Vperi like the node N1.

START OF DRIVER BOO
TING: RLB goes high active. Transistor MN4 is turned off to isolate RLXH from node N1 and protect the CMOS device at node N1 when RLXH is fully boosted. MN9 is also cut off when the node N3 is boosted. When RLB is activated, node N
Twelve is a logical one. As a result, the node N5 becomes (Vper
i + Vperi−Vt). Further, the node N3 is boosted at the same time when the node N20 becomes logic 1 and at the same time. Further, the boosted voltage of the capacitor MN11 by the boosted node N3 is completely transferred to the word line driver RLXH. Since the word line driver is boosted in this manner, the addressed row is driven.

END ACTIVE CYCLE: R
L1_ and RLEN_ are invalid (high logic level).
The boosted signal is emitted via MN10 and MN5. Return the node to the precharged state, as at point A_.

As described above, AT PRECHARGE
To END ACTIVE CYCLE from normal operation, PBOSC signal from oscillator is LONG RA
Excited during the S cycle. This is capacitor MN16
By constantly boosting RLHX, the leak in the word line is compensated. In the 2DFT mode, the boosting function of the word line driver for the word line stress and the word line leak is "NOR" gates NR3 and NR4.
Has been deactivated by. The transistor MN19 is turned on in the word line stress mode, and when boosting is deactivated, an external voltage can be applied to the driver. Regarding the word line leak mode, the boosting function is deactivated, and the leak test is simply a word line leak test instead of the boost capacitor. The only drawback is not the main check for leaks. That is, since the word line is at the (Vperi-Vt) level, no high voltage word line actually exists. The oscillation signal from the PBOSC is also deactivated through the "NOR" gate NR5 during either one of these 2DFT modes. This can prevent recharging of the word line via the other source.

FIG. 28 shows an RDDR (row decoder driver) circuit. This is the row predecoder of the device. Used for initial address decoding, each predecoder gates the RLXH signal to select one of each row for two 256K array blocks in each quadrant. The predecoder circuit consists of five input "NOR" gates. The input used for predecoding is R
A0, RA1, RA9 and RA10. The last input is RRQSQ, which is used to disable the predecoder if the row is programmed redundancy. During precharge, BNKPC_Q is used to charge node N3. Inverter IV1 and transistor MP3 are used to keep node N3 high when selected, and RLXH drives the word line decoder. However, when the device is operating in DFT wordline stress mode, a low active TLW
The LS_ signal disables address decoding based on RA0. This allows two adjacent rows to be selected.

FIG. 29 shows a BNKPC_ (bank selection precharge clock generator) circuit. It receives a clock stop from the reset pulses RID and RLT2. The output signal BNKPC_Q excites the precharge of the row decoder driver RDDR, the bank selection circuit BNKSL, the left end bank selection circuit of FIG. 37 and the right end bank selection circuit of FIG. 38.

FIG. 30 shows an XDECM (row: ROW decoder). The purpose of row decoding is to do final address decoding to select only the correct word line. That is, when an address signal is received from a place distant from the decoder, the timing is delayed and all address bits are correctly decoded when they are ready.
The row decoder uses a 3-input "NAND" gate. Inputs are row factors, RF47, RF811 and RF121
It is 5. This is 64 in each block of the 256K array.
Select one of the groups. The source of the "NAND" gate transistor is connected to the block select signal BSSJK_M, which is decoded by RA8 to RA11.
With this setting, only one of the active 256K array blocks having a set of 4 word lines can be selected. Set of 4 word lines is XWJMK1, XWJMK
1, XWJMK2 and XWJMK3. Since it has already been predecoded in the RDDR circuit, only one of them has been activated. BSSJMK
The M signal is used to precharge N1 to "1" and inverter IV2 and transistor MP2 are used to hold the signal when selected. The purpose of the row redundancy circuit is to replace a defective word line with another normal word line to repair the entire chip for proper operation. There are 16 blocks of an array of 512K bits in a quadrant of 64M memory. Each of these blocks has four physically redundant word lines. All the four redundant rows are arranged at the positions farthest from the sense amplifiers of the block of the 512K array, and each redundant word line is defective in any defective row in the same block or in another memory quadrant as well as another defective memory block. You can exchange rows.
It should be noted that there is no dummy word line that limits the type of redundant row, ie the row that can be replaced by the BL or BL_row. In redundancy programming, one quadrant is divided into two octant spaces of 8 blocks each. 8
For any redundant row programmed in the subspace, similar redundancy can be programmed into the image blocks of the other 8-section space. The characteristic of this circuit is that the DFT x in which the array block is operating in two octant spaces.
In various special modes of operation such as 32 parallel and COPY, complex decoding circuits are required to distinguish between octal spaces with redundant rows and octal spaces without redundant rows. To avoid this, both octet spaces can be programmed symmetrically to omit extra decoding circuitry and fuses. Further, since the RA11 address line is not decoded in order to improve the access speed, the access time of the redundant row becomes faster than the time of decoding the RA11 address line. The device has 64 redundant decoders RRDEC. 51 in total
Two logical word lines can be exchanged. Each logical redundant line consists of a pair of two physical rows in each memory block. However, since there are only four physically redundant rows within each 512K memory block, only four maximum rows can be swapped within the 512K memory block.
On the other hand, in the all-arbitrary method, there is no such restriction, and a redundant row in a quadrant including a redundant row can be replaced with a defective row in another quadrant. A total of 512 word lines can be replaced for the entire device, with no restrictions on its location. For example, all repairs can be done in all quadrants as long as there is unused redundant memory.

FIG. 31 shows RRA (ROW redundant address)
The circuit is shown. This is for generating the redundant address of the redundant decoder. 120 RRs in the device
There is an A circuit, and each 10 RRA circuits are divided into 12 groups. Row address RA0 / RA_0 to RA9 / R
A_9 is used as an input for each of these groups. Each group represents a logical redundant row address. For programming redundancy, if the address line is desired to be logic "1", the fuse F1 can be blown to program the redundant row address. On the other hand, F1 when the redundant row is not used
Can be left as it is without melting. By programming this fuse during the operating cycle, R will only occur when the input address during the operating cycle matches the redundant address.
RA output and RRUVAX are set to logic "0". If the input address does not match the redundant address, RRUVAX
Will provide a logical "1" output. Therefore, the redundancy circuit programs the RRDSPU input pulse signal to a high level when the power is turned on, and the pulse latches the redundancy address, for example, as the A72H row. Where 1
The set of 10 RRA circuits will use addresses RA0 / RA_0 through RA9 / RA_9 for programming. It should be noted that the addresses RA11 and RA10 are not used here. RA11 is ignored because it is not necessary to select an octet space in each quadrant, so that the chip can be effectively used. R
A10 is decoded in the RRDEC circuit. Finally there is the node RRUVPN. This node acts as a power supply line for an inverter having MP2 and MN2. This is to prevent the voltage of N1 from dropping too much when the power is turned on when the fuse is not blown. When this signal is generated, it becomes difficult for MP1 to pull up the node N1 mainly as a limiter. Due to layout restrictions, two RRA circuits are (W / 2 = 20 /
Transistor MP with a size of 0.8 μm)
1 is shared, and the size of MP1 in the circuit is (W / 1 = 10
/0.8 micrometers). Thus, RRU
VPN is only a common contact between two RRA circuits.

FIG. 32 shows an RRDEC (ROW redundancy decoder). This circuit is used to decode the redundancy address generated by the RRA circuit and integrally forms a redundancy mechanism. A set of 10 RRA outputs form the inputs of a "NOR" structure decoder. The ten RRA outputs originate from row addresses RA0 / RA_0 through RA9 / RA_9. In addition to this, RA10 and RA_10 are also “NO
It is connected through two fuses as the "R" input. The fuse acts as a switch that energizes the circuit. At least one of these must be blown to excite the circuit. When the programmed redundant RA10 is a logic "1", the fuse connected to the input RA10 is blown. When programming to a logic "0", the other fuse is blown. If neither fuse blows, RRDEC remains disabled during any operating cycle. However, if both fuses are blown, the device can ignore the address R10 / R_10 and simultaneously select two rows in the octet space. The output is precharged to a high level by RRL2 switching "on" transistor MP1 during precharge. It is possible to avoid the flow of high current because all the input rows are made into the invalid theory. In the operating cycle, if the address RA0 / RA10 matches the programmed redundancy address, the output remains high to indicate that a redundant row selection has been detected. Unlike typical redundancy decoding circuits that use a one-stage "NOR" decoder, this uses a two-stage decoding system. RRA is a predecoder and RRDEC is used for final decoding. This circuit can reduce the number of fuses required on the chip, whereas each has a true and complement address that enters the decoder in the conventional manner, each requiring a fuse. It is also possible to reduce the capacity of the decoding node N2 and speed up the decoding time.

FIG. 33 shows an RRX (ROW redundant X factor) circuit. Eight of these circuits are provided in the DRAM. Each of them simultaneously selects three gates in the twelve RRDEC outputs in parallel one of the four redundant rows in each 512K block. The output signal is RRQS,
It can be applied to the ROW redundant quadrant selection circuit. RRX
The E signal activates three "NAND" gates.
Only when the redundancy decoding is completed, that is, after the non-selected RRUDV signal becomes low level, RRXE
It is important to start energizing the signal. If the RRXE signal arrives too fast, the output PROX will be greater than the spacing between the rising edge of the RRXE and the falling edge of the unselected RRUVD signal.
High pulses occur in U, RR1XU or RR2XU. A high pulse on these outputs causes the RRQSQ signal to be emitted, making it impossible to make an accurate determination of which quadrant uses redundancy. Another important aspect of RRXE gate timing is the need to switch off gating as soon as possible after an operating cycle. This is to disable the "NOR" gate RRQS decoder to eliminate high current during precharge.

FIG. 34 shows an RRXE (ROW redundant X factor evaluation) circuit. To achieve the correct timing, similar to the RRX circuit described above, this RRXE circuit is designed to interfere with the operation of the row redundancy decoder. This allows the RRX circuit to be gated in with the proper sequence of the RRXE signal. In the RRXE circuit, RA0 and RA_0 are used to evaluate the address of redundancy within RRDEC. Used to precharge the circuit. P-channel transistor M
P1 is much larger than that of the RRCED circuit. It slows the switch off, delaying the start of RRXE, and is further delayed by the inverter IV2. Also, since it is a large transistor, the node N
A fast pull-up of 2 is performed to nullify the input of the RRQS "NOR" gate, thus avoiding high current flow. R using two bus gates MN2 and MN3
The bus gates in RA can be matched. RL1
_ And RL2 signals at the same time and the precharge signal is applied to the gate of MP1 to prematurely switch off precharge due to the falling edge of RL1_ and RL2.
The falling edge of allows a slow pre-charge turn-on. The gated RL1_ and RL2 signals can finally be gated by the delayed RRXE signal to generate the precharge signal RRL2 of the redundancy circuit. This is done by setting R before the other row redundancy circuits perform precharge.
This is to perform interlock so that the RXE circuit becomes a precharge cycle. Therefore, in the precharge of the RRXE circuit, various decoder inputs can be invalidated before starting the precharge of these decoders by the activation of RRL2. As a result, there is no collision between the decoder input and the precharge cycle for a decoder with active inputs. If this collision occurs, a high current will be drawn in the decoder. Here, by fusing the two fuses,
It should be noted that the row redundancy circuit for the entire device can be disabled.

FIG. 35 shows an RRQS (ROW redundant quadrant selection) circuit. Although the above-mentioned circuit decodes and identifies the row address used as redundancy, RRQS and quadrant selection further perform decoding to identify which quadrant the redundant row belongs to. The device has four RRQS circuits, each of which selects a quadrant of the array. RRQS
The circuit is designed as a 12-input "NOR" gate. When designing this circuit, if the redundant address does not belong to the repaired quadrant, the corresponding fuse in RRQS is blown. The quadrant does not blow the fuse to the repaired row. By doing so, if a redundant row is addressed and belongs to that quadrant, node N2 is always
Goes low and the activation output RRQS signal, that is, TL
RQ_ and RRQSQ occur. If the redundant row does not belong to that quadrant or is not the addressed redundant row, node N2 remains high. The RRL2 signal is used to turn on MP1 and precharge N2 to a high level during precharge. MP2 with an inverter is used to hold the precharge level at node N2 when it is not selected. It should be noted that, by design, the redundant address can choose any number of active quadrants. This is accomplished by not blowing the fuse corresponding to the selected address in the RRQS circuit for the quadrant with the repaired row. When the fuse of the RRQS circuit is blown, the potential of the node N1 is not discharged even if the predecoded address bit signal is applied to the gate of the transistor. By discharging this node N1, the output of the inverter IV2 can be set to a high logic level. However, the number of address bits is 64M DRAM
In the above case, the 13-bit state must be decoded in parallel and at the same time, so that the parallel combined resistance of the specific resistances of the fused fuse becomes low. Therefore,
The P-channel transistor MP1 that drives the inverter IV2 via the common node N1 has a strong driving ability to drive the parallel combined resistance of all fuses and the inverter IV2 when all the address bits are at a high level and the transistors MN1 to MN12 conduct. Must. If the drivability is not sufficient, a malfunction that a true coincidence signal cannot be generated will occur. Especially, when the power is turned on, all the address bits are at a high level together with the reset signal, so this danger is great. In the fuse decoder circuit RRQS shown in FIG. 35, the transistor MP2 that pulls up the common contact N1 can be composed of a small transistor required to maintain the potential of the node N1, but the potential of the common contact N1 temporarily drops. And RRL again
It should be noted that the next cycle of redundant address decoding cannot be performed unless it is precharged by 2 signals.

FIG. 36 shows a redundant address matching circuit.
This circuit is improved in operation speed and circuit area as compared with the redundant address matching circuits shown in FIGS. 31 and 32. When using the redundant memory, it is sufficient to blow off the energizing fuse FE. The P-channel transistor PCH_1 is energized by the activation signal STARTUP 68 to generate the REN_ signal. The address signals AF_0 to AF11 whose input addresses are adjusted to low active signals in the preceding stage of this circuit
And the REN_ signal can be logically operated by the "NOR" logic gate 70 to obtain the output signal. This signal is output via programmable fuses F0 to F11 to N1, N2 and N3 which are connected in a wired "OR". Further, the address fuse coincidence signal can be obtained by inputting this output to the "NAND" logic gate 65 and performing a logical operation. Therefore, the device decides to use redundant memory rather than defective memory. here,
Each AF_ signal is input to the "NOR" gate 70, which is composed of a "NAND" gate and
If the "D" gate 65 is changed to a "NOR" gate, the operating speed of the entire circuit can be increased. Also,
Since four fuses are used in parallel as a group, for example, when leaving the fuse of F0, the other fuses F1,
It is necessary to blow out F2 and F3. This is because, when the output of the fuse F0 is at a high level, if the fuse of F1 remains, this signal is drawn through the F1 to the “NOR” gate output, which may cause a logic malfunction or damage the circuit. is there. Each “NOR” gate 70 has a high resistance value after the fuses connected in series are blown or a medium resistance value due to an incomplete blowout.
5 cannot be driven. Therefore, the address coincidence signal is highly reliable. Furthermore, although the fan-out of the P-channel transistor PCH_1 increases,
In order to drive about 12 gates in a normal operation state, a transistor having a normal size may be used. Here, N
Although the common nodes of the address decoders corresponding to 1, N2 and N3 are used, it is possible to connect all the addresses at one common node in a yard. In this case, the last-stage "NAND" gate 65 shown in FIG. 36 may be replaced with an inverter. The decoder shown in FIG. 35 can decode the redundant address only after precharging the common contact N1, but the circuit of FIG. 36 has no such limitation. That is, as long as the circuit is energized by the STARTUP signal, REN_ is active, so when the logic state of the address signals AF_0 to AF_11 changes,
A redundant address signal match signal for a new cycle can be generated. It should be noted that this is effective for high-speed access such as static column mode.

FIG. 37 shows an RXDEC (redundant X word decoder) circuit. In the RXDEC circuit used as the final decoding of the redundant row, the boosted voltage level is propagated from the word line driver to the redundant row. Each physical redundant row is generated by the RXDEC circuit. Redundancy decoding is performed by a 3-input "NAND" gate. With the given redundant address, RRQSQ identifies the quadrant and RRXU decodes one of the four redundant rows in each 256K array block. Finally, when the regular row decoding is performed, the block signal BSSJK_M can select one of the 16 array blocks to complete the row redundancy decoding.

FIG. 38 shows an RRDSP (ROW redundant decoder set signal) circuit. The purpose of this circuit is RRA
And generating a pulse in the CRRA circuit to generate a redundant address when the power is turned on. There is also a series of connected inverters and capacitors whose input and output stages are gated by "NAND" gates to provide the pulses. The circuit utilizes the RID as an input and is energized at power up. Where all RRA
Instead of generating one pulse in the circuit, four pulses are generated by the 120 RRA circuits at different times. Therefore, simultaneous excitation of all RRA circuits, which causes high peak current, is avoided, and problems such as noise do not occur. Besides, RR having RRDSP1 by changing the metal mask of SW2A, SW2B, SW2C, SW2D
By combining the pulse widths of RRDSP2 with DSP0 and RRDSP3 respectively, two sets of pulses can be generated instead of four sets of pulses. After the pulse is generated, the output CRDST is excited. This makes CRDS
The pulse output for performing the column redundancy address latch is started in the P circuit.

FIG. 39 shows the RRATTST circuit. The purpose of this circuit is to test whether the pulses generated by the RRDSP are sufficient to latch the RRA address. This is used only for internal probing.
RRATTST is the same as RRA, except that the fuse used in RRA is replaced by capacitor MP1. Instead of using regular inputs, probe pads for external signals are placed on RA_X and for RAX inputs, grounded. Another probe pad is RRDS
It is connected in parallel to the PU signal. This allows the alternating signal to be latched. The capacitor MN5 sets the node N2 to a low level when the power is turned on. This circuit is RRDSP
It can be checked whether the U pulse width is sufficient to discharge the node N1 of the capacitor MP1. The condition can be monitored from the probe pads at nodes N1 and N3. The sense clock, which carries out the operation chain of the data sensing procedure in the device, is activated at every completion of the row address decoding in any operation cycle. This involves the generation of various clocks that turn on the selected sense amplifiers. Before entering the individual sense clock circuits, 6
The sense amplifier circuit of 4M memory will be investigated. First, the quadrant is divided into 16 blocks of 512K memory array. Eight banked sense amplifiers are arranged in one quadrant, and these sense amplifiers are arranged parallel to the central bond pad row from the center side to the chip side. 64M DRAM to minimize chip area
Is designed with a shared sense amplifier. In the shared sense amplifier circuit, each sense amplifier bank has two 512K
Shared by the memory array block of bits. That is, 1M bits can be sensed. Therefore,
Note that there are no sense amplifier banks at each end of each quadrant. 25 for each sense amplifier bank
It has six sense amplifiers, so each bank is responsible for 256 columns of memory arrays on either side of it. A point to be noted in this circuit is that two columns which are handled by the same sense amplifier do not have the same Y address, and one has an odd address and the other has an even address. Therefore, this switching can be performed by selecting the YS line that crosses the sense amplifier vertically.

The column redundancy configuration, like the row redundancy configuration, has the purpose of replacing defective columns to complete a chip capable of complete operation. Within the chip, the memory array is divided into eight quadrants. Each quadrant has 16 array blocks of 256 columns. Each array block has 6 redundant columns. These redundant columns can be provided on the side facing the center of the chip. The redundant column consists of a pair of bit lines (BL and BL_) and a sense amplifier. Unlike a row redundancy circuit that can replace a redundant row with any defective row, column redundancy repair is dominated by the defective column data path. Each array block is supported by two sense amplifier banks. Each of these banks has two local (LOCAL) I / O data paths to two different main (MAIN) I / O lines. Therefore, the same main I /
Use redundant columns with O lines.

The redundant column array has the same form as the block array. The redundant sense amplifier bank is a continuation of the normal sense amplifier bank. Each of these banks has six redundant sense amplifiers. The first three sense amplifiers are connected to even main I / Os, and the other three sense amplifiers are connected to odd main I / Os. For redundant repairs, we first need to know which sense amplifier the bad column is connected to.
Once the sense amplifier containing the bad column and the fault is identified,
They would have their sense amplifiers replaced with redundant columns having the same main I / O.

In redundancy programming, it is necessary to replace two adjacent columns for each defective column in the array block. Two columns have common column addresses CA11 to CA1
have. At the same time, another column at the same address in the next octet space is replaced. The reason why the two 8-minute space repairs are simultaneously performed is the same as in the case of the row redundancy circuit. Besides repairing two columns at a time, the adjacent four columns of columns CA11 to CA2, which optionally have the same redundant decoder, can be replaced. It is also possible to consider the option of completely arbitrary replacing several quadrants with the same redundant decoder.

There are the following restrictions on whether or not some columns can be replaced. The 64 redundant decoders can only replace 64 logical columns, have 6 physical redundant columns per array block, but each repair uses at least 2 columns, so each array block has only 3 possible redundant locations. Absent. Since each bank has six redundant sense amplifiers, three of them are connected to even main I / Os and the other three are connected to odd main I / Os. Substitution with O is limited to a maximum of 3. Furthermore, repairs to the same address column from different blocks would require the addition of an independent redundant decoder if they did not share the same RA8 to RA9 addresses.

Although the present invention has been described in detail above with reference to examples, this description is merely illustrative and should not be construed in a limiting sense. Furthermore, many modifications in details of the embodiments of the present invention and other embodiments of the present invention will be apparent and feasible to those of ordinary skill in the art having reference to this description. You should understand. For example, although the inventions described above have been described with respect to DRAMs, they can also be used as a redundant configuration for any memory, including read only memory (ROM) and static random access memory (SRAM). Furthermore, the N-channel transistor can be replaced with a P-channel transistor, and the field-effect transistor can be replaced with a bipolar transistor. Note that what is called a field effect transistor here may be a MOS transistor. These structures are formed on an integrated circuit by using a well-known semiconductor manufacturing technique. All such modifications and other embodiments are within the true scope and spirit of the invention as claimed.

[0056]

The effects obtained by the typical one of the inventions disclosed in the present invention will be briefly described as follows.
It is as follows.

(1) More electric circuits can be mounted in the semiconductor integrated circuit chip.

(2) A defective memory cell generated in a semiconductor integrated circuit manufactured by the submicron technique can be replaced with a programmable redundant memory cell by blowing another fuse.

(3) It is possible to provide a memory cell redundancy mechanism for relieving defective memory cells and row line short-circuit defects in all memory quadrants at high speed and without malfunction.

(4) It is possible to provide an address coincidence signal generating circuit which operates with low power consumption at a low manufacturing cost.

(5) It is possible to provide a semiconductor integrated circuit device capable of improving the manufacturing yield.

[0062]

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor memory chip.

FIG. 2 is a plan view of a portion of a memory array.

FIG. 3 is a perspective view of a portion of a memory array.

FIG. 4 is a cross-sectional view of the memory array of FIG.

5 is a three-dimensional view of the chip of FIG. 1 sealed with resin.

6 is an explanatory view of assembling the semiconductor device of FIG.

7 is a cross-sectional view of the semiconductor device of FIG.

8 is a bond pad layout of the chip of FIG. 1. FIG.

FIG. 9 is a layout view of output pins of a semiconductor memory device.

FIG. 10 is a conventional address matching circuit.

FIG. 11 is an address matching circuit that can be used in 16 MDRAM.

FIG. 12 is another address matching circuit used in a 16M DRAM.

FIG. 13 is a plan view of a 64M DRAM chip.

FIG. 14 is a 64M DRAM pin layout diagram of 64M × 1 bit and 16M × 4 bit configurations.

FIG. 15 is a 64M DRAM pin layout diagram of 8M × 8 bit configuration.

FIG. 16 is a pin layout diagram of 64M DRAM having a 4M × 16 bit configuration.

FIG. 17 is a redundancy mechanism for compensating for defective memory cells in 64 DRAM.

FIG. 18 is a correlation diagram showing the number of defective memories and the redundancy by the yield rate.

FIG. 19 is a circuit diagram of a CBR (CAS before RAS) detector.

FIG. 20: RBC_RESET (RAS Before CA
S) is a circuit diagram of the detector.

FIG. 21: RBC_RESET (RAS Before CAS
It is a circuit diagram of (reset).

FIG. 22: PADABUF (PAD ADDRESS
It is a circuit diagram of BUFFER).

FIG. 23: RADR (ROW ADDRESS DRI
3 is a circuit diagram of VER).

FIG. 24 is a circuit diagram of BITCOUNT (CBR internal bit counter).

FIG. 25: RF & RF (CODE ROW FACTO
It is a circuit diagram of R).

FIG. 26: RLEN (ROW LOGIC ENABL
It is a circuit diagram of E).

FIG. 27: RLXH (ROW LOGIC X WOR
It is a circuit diagram of DHIGT).

FIG. 28 is a circuit of an RDDR (row decoder driver).

FIG. 29 is a circuit diagram of BNKPC_ (bank selection precharge clock generator).

FIG. 30 shows a circuit diagram of an XDECM (row decoder).

FIG. 31 is a circuit diagram of an RRA (row redundancy address) generator.

FIG. 32 is a circuit diagram of RRDEC (row redundancy decoder).

FIG. 33 is a circuit diagram of an RRX (row redundancy X factor) generator.

FIG. 34 is a circuit diagram of RRXE (row redundancy X factor evaluation).

FIG. 35 is a circuit diagram of RRQS (row redundancy quadrant selection).

FIG. 36 is a circuit diagram of a fuse decoder of a redundant address matching circuit.

FIG. 37 is a circuit diagram of RXDEC (redundant X word decoder).

FIG. 38 is a circuit diagram of an RRDSP (row redundancy decoder set signal) generator.

FIG. 39 is a circuit diagram of RRATTST.

[Explanation of symbols]

2 Transistor group 3 P-channel transistor 4, 164 Fusing fuse 5, 8, 162 Inverter 6 Inverter group 7 "NAND" gate 10 Semiconductor chips 12a, 12b, 12c, 12d Memory quadrant 15 Bit line contact 16 Memory block 17 Bit line 17a Titanium Layer 17b Polycrystalline silicon layer 18 Decoder 19 Word line 19a Pass transistor gate 22 Peripheral circuit 24 Bond pad 26 Resin encapsulant 30 Lead frame 32 Polyimide tape 38 Power supply bus lead 40 Bond wire 40a Lead finger 41, 42 Interconnection wire 43 Transistor 44, 45 Trench Capacitor Region 46 Semiconductor Substrate 47, 51, 53, 55 Insulator Layer 48 Electric Field Plate 49 Multilevel Interconnection Line 50 Impurity Region 5 2 Storage Dielectric 54 Gate Oxide Film 56 Source Region 58 Drain Region 59 High Concentration N-type Impurity Diffusion Part 60 P-Tank Region 61 Nitride Layer 62 Oxide Layer 65 “NAND” Logic Gate 68 Redundancy Mechanism Activation Signal 70 “NOR” Logic gate 166, 168, 170, 172 Field effect transistor 194, 196 Word line 202 Defective memory 204 Redundant memory 206 Address bus 208 Fuse decoder 300 Redundant energizing line 302 Redundant select line 304 Memory block 306 Redundant row 308 Predecoder 312 MS signal

[Table 1] Type Redundancy method Yield limitation (block unit) Number of decoders Number of redundant word lines A All arbitrary 8 words / 4M (32 decoder / 32M) 64 512 512 B All arbitrary 8 words / 4M (32 decoder) / 32M) 64 512 512 C fixed 2 words / 512K (2 decoder / 2M) 64 512 512 D All arbitrary 2 words / 2M (2 decoder / 16M) 8 128 E Semi fixed 4 words / 512K ( 12 decoder / 16M) 12 pieces 128 pieces

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takumi Nasu 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. (72) Hidetoshi Iwai 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device In the development center

Claims (3)

[Claims] 1. A semiconductor memory device for receiving a row and column memory address signal to access a predetermined memory cell, wherein each input means is a plurality of programmable fuse means connected to the memory address signal. A semiconductor memory including a common node commonly connecting outputs of the fuse means, an address match signal generating means connected to the common node for generating an address match signal, and a means for receiving the address match signal and replacing a defective memory cell with a redundant memory cell. apparatus. 2. A semiconductor memory device for receiving a row and column memory address signal to access a predetermined memory cell, wherein a plurality of programmable fuse means connected to a common node and a redundancy mechanism activation signal are provided. Means for inputting a memory address signal to the fuse means, means for generating a redundant address match signal in response to the potential of the common node, and redundant row or column lines including defective memory cells in response to the redundant address match signal. A semiconductor memory device including means for replacing a row or column line connected to a memory cell. 3. A semiconductor memory device which receives a row and column memory address signal to access a predetermined memory cell, wherein a plurality of programmable fuse means having one end connected to a common node and a redundancy mechanism activation signal are provided. Means for connecting the memory address signal to the other end of the fuse means, means for generating a redundant address match signal in response to the potential of the common node, and a row including a defective memory cell in response to the redundant address match signal. Or a semiconductor memory device including means for replacing a column line with a row or column line associated with a redundant memory cell.