JPH065738B2 - Semiconductor device - Google Patents

Description

The present invention relates to a gate turn-off thyristor (hereinafter abbreviated as GTO) capable of controlling conduction / non-conduction of a main current by a control current.
Alternatively, the present invention relates to a semiconductor device such as a transistor (hereinafter abbreviated as TRS), and more particularly to a junction structure capable of improving its breaking performance.

[Background of the Invention] In GTO and TRS, an emitter layer is composed of at least one strip-shaped region having a substantially constant width and is exposed on one main surface of a semiconductor substrate together with a base layer adjacent to the strip-shaped region. One main electrode is in low resistance contact with the base region, the control electrode is in low resistance contact with the base layer so as to substantially surround each strip region, and the other main electrode is in low resistance contact with the other main surface of the semiconductor substrate. Each electrode is connected to a pair of main terminal and control terminal.

The GTO will be specifically described below as an example.

FIG. 1 shows an example of a conventional GTO. A cathode electrode 2 and a gate electrode 3 are formed on one main surface of the semiconductor substrate 1.
Are provided alternately. These electrodes are connected to the cathode terminal 5 and the gate terminal 6, respectively. Also,
An anode electrode 4 is provided on the other main surface and is connected to an anode terminal 7. FIG. 2 is a partial longitudinal sectional view of FIG. 1, and the same parts as those shown in FIG. The semiconductor substrate 1 is composed of an n-type emitter layer 20, a p-type base layer 30, an n-type base layer 10, and a p-type emitter layer 40.

The configuration of FIG. 2 is regarded as a unit GTO, and a configuration in which a plurality of GTOs are arranged in parallel is shown in FIG. That is, the n-type emitter layer 20 has a strip shape, the cathode electrode 2 makes low resistance contact with each strip-shaped n-type emitter layer 20, and the gate terminals 6 are provided on both sides in the width direction of each strip-shaped n-type emitter layer 20. The gate electrode 3 directly connected to the p-type emitter layer 40 has a low resistance contact, and the p-type emitter layer 40 has an anode electrode having a low resistance contact.

Although not shown, a passivation film such as a silicon oxide film, a glass film, or a silicon rubber film is provided on the surface where the pn junction is exposed in FIGS. 1 and 2. Also, gold or the like is doped as a life time killer.

Next, the turn-off operation of the conventional GTO will be described with reference to FIG.

To turn off the GTO from the conducting state to the non-conducting state, the gate current is drawn from the gate terminal 6. At this time, the excess carriers accumulated in the p-type base layer 30 that creates the GTO conduction state are sequentially swept from the region near the gate electrode 3. Therefore, the conduction region is turned off sequentially from the side closer to the gate electrode 3. Therefore, in the case of the conventional GTO, the gate current having the same magnitude is drawn from both sides of the n-type emitter layer 20, so that the conduction region C ₁ is finally left in the center of the n-type emitter layer 20 and the current concentrates. . Since there is no excess carrier in the p-type base layer 30 that has been turned off and finished below the n-type emitter layer 20, the resistance in that portion is equivalent to that in the thermal equilibrium state.
Therefore, the resistance r of the gate current path from the gate electrode 3 to the conduction region at the center of the n-type emitter layer 20 becomes larger than that at the initial stage of turn-off, and the gate current becomes difficult to be drawn. In this state, if the gate current sufficient to completely turn off the GTO cannot be drawn out, an excessive temperature rise occurs due to power loss in the current concentrated portion, resulting in thermal destruction.

Now, there is a safe operation area (hereinafter abbreviated as ASO) as an important characteristic that represents whether or not the GTO is turned off without being destroyed. This is a range obtained by plotting the anode current and the anode-cathode voltage when the GTO can be turned off without destroying them on the vertical axis and the horizontal axis, respectively, and it is naturally desirable that the range is wide. FIG. 3 is an example of this ASO. The shaded area is ASO, and if the current / voltage locus at turn-off falls within this range, G
The TO operates without being destroyed. The vertical axis of FIG. 3 may be represented by the cathode current density instead of the anode current. Also, when the GTO is turned off at a cathode current density of a specific value, the magnitude of ASO may be expressed by the maximum anode-cathode voltage that does not destroy the GTO.

In the conventional GTO, in order to expand ASO, the gate electrodes 3 are formed on both sides of the n-type emitter layer 20 as shown in FIG.
To reduce the width of the n-type emitter layer 20, and n
Various efforts have been made to increase the thickness of the mold base layer 10, but the width of ASO is limited. In fact, when the cathode current density is about 1000 A / cm ² , the maximum anode-cathode voltage at which the GTO does not break is 200 to 300.
It was impossible to exceed V. For this reason, when using the GTO, a protection circuit called a snubber circuit is required to prevent destruction, which leads to a complicated circuit and an increase in size of the device. In addition, a spike-like voltage is generated between the anode and cathode terminals 7 and 6 due to the current flowing through the snubber circuit and the wiring inductance at the time of turn-off. The voltage locus deviated from ASO, and a large current could not be interrupted. In order to ensure that the current / voltage locus when a large current is turned off is within ASO, it has conventionally been necessary to connect a large capacitor to the snubber circuit, resulting in a large power loss in the snubber circuit. It was Further, it is necessary to install the capacitor as close as possible to the GTO in order to make the wiring inductance as small as possible, but this has a limit, and there is a problem that the cutoff limit current of the high power GTO is limited to a small value.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device in which the effect of drawing out the current from the control terminal at the time of cutting off the current is improved and the ASO is expanded.

Another object of the present invention is to increase high power GTO by expanding ASO.
It is intended to increase the maximum breaking current of.

[Outline of Invention]

A feature of the present invention is that the n emitter layer is formed in a ring shape, and the first control electrode is provided on the p base layer so as to surround the n emitter layer on the outer peripheral side of the n emitter layer. A second control electrode is provided on the p base layer on the circumferential side, and one of the first and second control electrodes is directly connected to a control terminal to which a control signal is externally applied.

First, the operating principle of the present invention will be described.

The present inventors have confirmed that the ASO dramatically expands due to the structure in which every other gate electrode of the GTO is directly connected to the gate terminal 6 as shown in FIG. Therefore, as a result of experimental and theoretical studies, it was clarified that ASO is expanded by the following mechanism. FIG. 5 shows a vertical cross section of the unit GTO as in FIG.

Incidentally, in FIGS. 4 and 5, the same or corresponding parts as those in FIGS. 1 and 2 are designated by the same reference numerals.

The gate electrodes 3 are formed on both sides of the strip-shaped n-type emitter layer 20.
Although a and 3b are in low resistance contact with each other, the gate electrode 3a is directly connected to the gate terminal 6, but the gate electrode 3b is connected to the gate terminal 6 through the resistance R. The resistance R is an internal resistance of the p-type base layer 30 as described later.

Since the resistor R exists, the gate current is mainly drawn from one side of the n-type emitter layer 20, that is, the gate electrode 3a side, at the initial stage of turn-off. Therefore, the conductive region is sequentially turned off from the side of the gate electrode 3a, so that the current concentrates in the region near the gate electrode 3b on the opposite side as shown by C _{2 in} the figure. FIG. 6 is a plan view of the cathode side of FIG.
At the final stage of turn-off, as observed in the conventional GTO, the current concentrates in a spot shape like S in the figure. In the case of the conventional GTO, the current spot S occurs near the center of the n-type emitter layer 20 in the width direction.
In the case of TO, it occurs in a region near the gate electrode 3b. At this time, since the resistance r ₁ in the p-type base layer 30 between the gate electrode 3a and the current spot S is considerably large, it is difficult to extract the gate current from the gate electrode 3a side. However, on the contrary, the gate current is easily extracted from the gate electrode 3b side. This is because the current path shown by the broken line in FIG. 6 is formed in the p-type base layer 30. Since the current spot S and the gate electrode 3b are close to each other, the resistance r ₂ in the p-type base layer 30 between them is considerably small. Further, between the gate electrodes 3b and 3a,
Almost the entire p-type base layer below the n-type emitter layer 20 serves as a current path (only two broken lines are shown in the figure for convenience). Therefore, the resistance between both gate electrodes (the resistance R in FIG. 5) is also considerably reduced, and a relatively large gate current is extracted through the current path indicated by the broken line. Therefore, ASO
Expands.

The greater the variation of the variable internal resistance R, the easier the extraction of the gate current. That is, in the initial stage of turn-off, the conduction region exists in the entire region between the n-type emitter layer 20 and the p-type emitter layer 40, and therefore the current path shown by the dotted line in FIG. 6 does not exist. Therefore, the internal resistance R at this time is, as shown in FIG. 6, in the current path indicated by the alternate long and short dash line that goes around the longitudinal end of the n-type emitter layer 20. If the internal resistance of the current path indicated by the one-dot chain line is small, the gate current is also extracted from the gate electrode 3b side at the initial stage of turn-off. The larger this component is, the smaller the gate current drawn from the gate electrode 3a side is, and the bias of the conduction region C _{2 to} the gate electrode 3b side is delayed. Therefore, the larger the internal resistance of the current path indicated by the alternate long and short dash line, the better. On the other hand, as the gate current drawn from the gate electrode 3b side at the final turn-off time is larger, the current spot closer to the gate electrode 3b side easily disappears. Even if the internal resistance of the current path shown by the one-dot chain line is increased, the internal resistance of the current path shown by the dotted line is sufficiently small.
The increase in internal resistance as a whole is small. Rather, it is preferable that the current spot S is formed more rapidly on the gate electrode 3b side due to the large internal resistance in the current path indicated by the alternate long and short dash line, and the internal resistance of the current path indicated by the dotted line is quickly reduced sufficiently. From the perspective of turn-off as a whole, it is rather convenient.

When the inventors of the present invention conducted an experiment to examine how the voltage between the anode and the cathode immediately before the breakdown changes due to the internal resistance of the current path indicated by the alternate long and short dash line when the same current is interrupted, the internal resistance It was found that the larger the voltage, the more the anode-cathode voltage can be increased and the ASO can be expanded.

Based on the above consideration, in the present invention, the internal resistance in the current path indicated by the alternate long and short dash line is made large by making the n emitter layer annular.

Example of Invention

 The present invention will be described below with reference to the embodiments shown in the drawings.

In the following embodiments of the drawings, the same parts as those shown in FIGS. 4 to 6 and corresponding parts are designated by the same reference numerals as those in FIGS. 4 to 6.

FIG. 7 is a bird's-eye view on the cathode side of a unit GTO according to an embodiment of the present invention, and FIG. 8 is a vertical cross-sectional view taken along the line II of FIG.

The first gate electrode 3b is completely surrounded by the n-type emitter layer 20 and the cathode electrode 2 in low resistance contact therewith, and the n-type emitter layer 20 and the cathode electrode 2 are completely surrounded by the second gate electrode 3a. It is surrounded. The gate terminal 6 is directly connected only to the second gate electrode 3a. Therefore, there is no resistance path (current path) shown by the alternate long and short dash line in FIG. 6 between the first gate electrode 3b and the second gate electrode 3a, and the internal resistance between them is n-type emitter layer 20 and n-type base. Only the lateral resistance of the p-type base layer 30 sandwiched between the layers 10 is provided, and the resistance between the gate electrodes 3a and 3b can be maximized. In this embodiment, the cathode electrode 2 and the second gate electrode 3a on the n-type emitter layer 20 are the n-type emitter layer 2 respectively.
Although it is provided on the surface of 0 and the entire periphery of the n-type emitter layer 20, it is not necessarily limited to that shape, and even if each portion is provided, equivalent performance is guaranteed.
For example, FIG. 9 and FIG. 10 show the modified examples.

Both figures are plan views, but each electrode is shaded. Further, the irregularities on the surface and the passivation film are omitted.

In each of the embodiments shown in both figures, the first gate electrode 3b is used.
Is completely surrounded by the n-type emitter layer 20, and the current is considered to flow through the entire surface of the n-type emitter layer 20 in the conductive state. It can be said that there is no current path for the gate current connecting the electrode 3a and the first gate electrode 3b. That is, at the initial stage of turn-off, it can be considered that the gate electrodes 3a and 3b are connected to each other with an internal resistance close to infinity. Therefore, at the initial stage of turn-off, the gate current is extracted only from the second gate electrode 3a side. When the turn-off progresses and the conduction region contracts and becomes a non-elliptical shape, both gate electrodes 3a and 3b are connected via the p-type base layer 30 in the non-conduction region, and the first gate electrode 3b side Also,
The gate current is extracted. At the beginning of turn-off,
Since the internal resistance of the p-type base layer 30 between the two gate electrodes 3a and 3b is extremely large, the turn-off operation proceeds rapidly.

In such a structure, a circular semiconductor substrate is used, the radial direction thereof is aligned with the axial direction of the n-type emitter layer 20, the n-type emitter layers 20 are radially arranged, and a cathode plate common to each cathode electrode 2 is provided. It is suitable for a power GTO having a pressure contact structure. Etching down the p-type base layer 30 on the upper main surface on the cathode side is a measure for avoiding contact with the gate electrodes 3a and 3b when the cathode plate is pressure-welded, but other means for avoiding contact is provided. If you do, you don't have to etch down.

The n-type emitter layers 20 arranged radially may be provided in a multiple ring shape.

In the above-mentioned embodiments, the p-type emitter layer 40 is provided on the entire lower main surface, but a part of it is omitted, and n
The present invention can also be applied to an anode-emitter short-circuit type GTO in which a high-impurity-concentration layer is provided to make low resistance contact with the anode electrode 4.

Further, it is also applicable to a GTO in which the conductivity types of the layers 10 to 40, 21, 22 are reversed.

Although no examples have been given for the TRS, the n-type base layer corresponds to the n-type collector layer, and the collector electrode may be brought into contact therewith with low resistance.

According to experiments by the present inventors, it was confirmed that the maximum interruptable current, which was about 2000 A in the past, can be improved to 2500 A or more.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain the semiconductor device in which the current drawing from the control terminal when the current is cut off is improved and the ASO is increased.

Then, it is possible to obtain a semiconductor device having an improved maximum breakable current.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of a conventional GTO, FIG. 2 is a partial vertical sectional view of the conventional GTO shown in FIG. 1, FIG. 3 is an explanatory view of a conventionally known ASO, and FIG. A schematic perspective view of a GTO as a prior example of the present invention, FIG. 5 is a G shown in FIG.
Partial longitudinal section of TO, FIG. 6 shows unit GT shown in FIG.
FIG. 7 is a plan view of the cathode side of O, FIG. 7 is a bird's eye view of the cathode side of the unit GTO according to one embodiment of the present invention, and FIG.
FIGS. 9 and 10 are plan views of the cathode side of the unit GTO according to the modified example of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Cathode electrode, 3a, 3b ... Gate electrode, 4 ... Anode electrode, 5 ... Cathode terminal, 6 ... Gate terminal, 7 ... Anode terminal, 10 ... N-type base layer, 2
0 ... n-type emitter layer, 30 ... p-type base layer, 40 ... p-type emitter layer, 21, 22 ... n-type diffusion layer, 31, 32 ...
Grooves 1a, 1b ... Inclined surface of removal portion.

Claims (1)

[Claims] 1. A pair of main surfaces located on opposite sides of each other,
A first conductive type first emitter layer adjacent to one main surface, a second conductive type first base layer adjacent to the first emitter layer, the first base layer and the other main surface A second base layer of the first conductivity type adjacent to the second base layer, and a second emitter layer of the second conductivity type adjacent to the second base layer and the other main surface of the second base layer, the second emitter layer of the other A semiconductor substrate composed of a plurality of annular regions on the main surface, a first main electrode in low resistance contact with a first emitter layer on one main surface of the semiconductor substrate, and another main surface of the semiconductor substrate At a second main electrode in low resistance contact with each region of the second emitter layer, and so as to surround each region of the second emitter layer on the second base layer on the other main surface of the semiconductor substrate. A first control electrode provided on the second main surface of the semiconductor substrate, A second control electrode provided on a second base layer surrounded by respective regions of the second emitter layer, and one of the first control electrode and the second control electrode is externally controlled. A semiconductor device, which is directly connected to a control terminal to which a signal is applied.