JPH0657455B2 - Method for manufacturing multilayer wiring board - Google Patents
Method for manufacturing multilayer wiring boardInfo
- Publication number
- JPH0657455B2 JPH0657455B2 JP60020962A JP2096285A JPH0657455B2 JP H0657455 B2 JPH0657455 B2 JP H0657455B2 JP 60020962 A JP60020962 A JP 60020962A JP 2096285 A JP2096285 A JP 2096285A JP H0657455 B2 JPH0657455 B2 JP H0657455B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- wiring
- wiring board
- conductor post
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title description 25
- 239000010410 layer Substances 0.000 claims description 62
- 239000004020 conductor Substances 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 19
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 229910001651 emery Inorganic materials 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 description 11
- 239000003822 epoxy resin Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 229920000647 polyepoxide Polymers 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920002284 Cellulose triacetate Polymers 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- NNLVGZFZQQXQNW-ADJNRHBOSA-N [(2r,3r,4s,5r,6s)-4,5-diacetyloxy-3-[(2s,3r,4s,5r,6r)-3,4,5-triacetyloxy-6-(acetyloxymethyl)oxan-2-yl]oxy-6-[(2r,3r,4s,5r,6s)-4,5,6-triacetyloxy-2-(acetyloxymethyl)oxan-3-yl]oxyoxan-2-yl]methyl acetate Chemical compound O([C@@H]1O[C@@H]([C@H]([C@H](OC(C)=O)[C@H]1OC(C)=O)O[C@H]1[C@@H]([C@@H](OC(C)=O)[C@H](OC(C)=O)[C@@H](COC(C)=O)O1)OC(C)=O)COC(=O)C)[C@@H]1[C@@H](COC(C)=O)O[C@@H](OC(C)=O)[C@H](OC(C)=O)[C@H]1OC(C)=O NNLVGZFZQQXQNW-ADJNRHBOSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/335—Structure of thermal heads
Landscapes
- Electronic Switches (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は多層配線基板の製造方法に関する。The present invention relates to a method for manufacturing a multilayer wiring board.
（従来の技術） 従来、多層配線基板として周知のプリント配線基板があ
り、多層構造を得るために基材の両面あるいは片面に貼
りつけられた銅箔を必要なパターン形状にエッチング
し、接着層を介してこれらを積層することにより、多層
配線基板を形成していた。また、スルーホール形成とし
て基材に穴をあけ、その内壁をメッキすることにより層
間導通を得る方法を用いていた。一方、ベース基材とし
てセラミックなど、基材にスルーホールを形成するため
の穴加工が困難な材料を用いる場合には、基材の一方の
面に絶縁層と導体層を交互に積層し多層化構造を得てい
た。一般的にこの方法をビルドアップ法という。ここ
で、このビルドアップ法による従来の多層配線基板の製
造方法の例として、サーマルプリンタなどに用いる二次
元サーマルヘッドの製造方法を用いて説明する。(Prior Art) Conventionally, there is a well-known printed wiring board as a multilayer wiring board. To obtain a multilayer structure, a copper foil attached to both sides or one side of a base material is etched into a required pattern shape to form an adhesive layer. A multilayer wiring board is formed by stacking these via the above. Further, as a method of forming a through hole, a method has been used in which a hole is made in a base material and an inner wall of the base material is plated to obtain interlayer conduction. On the other hand, when using a material such as ceramics, which is difficult to drill for forming through holes in the base material, as the base material, insulating layers and conductor layers are alternately laminated on one surface of the base material to form a multilayer structure. Was getting the structure. This method is generally called the build-up method. Here, as an example of a conventional method of manufacturing a multilayer wiring board by the build-up method, a method of manufacturing a two-dimensional thermal head used for a thermal printer or the like will be described.
従来の二次元サーマルヘッドの製造方法としては、例え
ば特開昭58−101080号公報に開示のものと類似したもの
が考えられており、その例を第２図に示す。まず、第２
図(a)に示すように、セラミック等の基板１の上にメッ
キ等の湿式のプロセス、あるいは蒸着やスパッタ等の乾
式のプロセスを用い、下層配線２を形成する。その上に
第２図(b)に示すように、ポリイミド樹脂をスピンコー
ターで塗布すること等により絶縁層３を設け、これをエ
ッチングしてスルーホール４を形成する。更に、第２図
(c)に示すように、スルーホール４に導電性ペースト５
を埋め込み、上層との導通をとる。次に、第２図(d)に
示すように、スパッタリング等で抵抗層を形成し、エッ
チングにより発熱抵抗体６を形成する。更に、上層配線
７を乾式のプロセスを用い形成することにより、第２図
(e)に示すような二次元サーマルヘッド（すなわち多層
配線基板）を製造していた。As a conventional method for manufacturing a two-dimensional thermal head, for example, a method similar to that disclosed in Japanese Patent Laid-Open No. 58-101080 is considered, and an example thereof is shown in FIG. First, the second
As shown in FIG. 1A, the lower wiring 2 is formed on a substrate 1 made of ceramic or the like by using a wet process such as plating or a dry process such as vapor deposition or sputtering. As shown in FIG. 2 (b), an insulating layer 3 is provided by applying a polyimide resin with a spin coater or the like, and this is etched to form a through hole 4. Furthermore, FIG.
As shown in (c), the conductive paste 5 is applied to the through hole 4.
Is embedded to establish continuity with the upper layer. Next, as shown in FIG. 2 (d), a resistance layer is formed by sputtering or the like, and a heating resistor 6 is formed by etching. Further, by forming the upper layer wiring 7 using a dry process, as shown in FIG.
A two-dimensional thermal head (that is, a multilayer wiring board) as shown in (e) has been manufactured.
（発明が解決しようとする問題点） しかしながら、上記従来の製造方法により得られる多層
配線基板にあっては、絶縁層３をポリイミド樹脂等を塗
布することによって得ているため、電流容量を増すため
に下層配線２の厚みを厚くすると、このエッジ部におい
て絶縁不良が生じたり、下層配線２の厚みによる段差に
より絶縁層３の上面の平坦度が著しく悪化したりする傾
向がみられた。これを防ぐためには、絶縁層３の厚みを
厚くする必要がある。しかし、この場合、スルーホール
４の形成が困難になり、例えば貫通していないスルーホ
ールが形成されてしまうことがある。その結果、従来の
製造方法は歩留りが悪く、また得られた多層配線基板は
信頼性が低いという問題点があった。また、上記製造方
法は、形成された絶縁層３の表面には微細な荒れがな
く、密着性の問題があるためコストの低いメッキ等の湿
式のプロセスを利用しにくいという問題点があった。(Problems to be Solved by the Invention) However, in the multilayer wiring board obtained by the above-mentioned conventional manufacturing method, the insulating layer 3 is obtained by applying a polyimide resin or the like, so that the current capacity is increased. When the thickness of the lower layer wiring 2 is increased, there is a tendency that insulation failure occurs at the edge portion or the flatness of the upper surface of the insulating layer 3 is significantly deteriorated due to a step due to the thickness of the lower layer wiring 2. In order to prevent this, it is necessary to increase the thickness of the insulating layer 3. However, in this case, it becomes difficult to form the through hole 4, and for example, a through hole that does not penetrate may be formed. As a result, the conventional manufacturing method has a problem that the yield is low and the obtained multilayer wiring board has low reliability. Further, the above-mentioned manufacturing method has a problem that it is difficult to use a low-cost wet process such as plating because the surface of the formed insulating layer 3 does not have fine roughness and there is a problem of adhesion.
従って、この発明はこれらの問題点を解決することを目
的とする。Therefore, the present invention aims to solve these problems.
（問題点を解決するための手段） この発明による多層配線基板の製造方法は、基板上に下
層配線を形成する第１の工程と、前記下層配線上に層間
接続用導体ポストを形成する第２の工程と、前記層間接
続用導体ポストの周囲に樹脂を塗布し、表面にエメリー
ペーパー状の適度な荒れを持つ離型フィルムを介して前
記樹脂をプレスして絶縁層を形成し、かつ前記層間接続
用導体ポストの上面を露出させる第３の工程と、前記絶
縁層の上部および前記層間接続用導体ポストの上部に上
層配線を形成する第４の工程とを有する。(Means for Solving Problems) In the method for manufacturing a multilayer wiring board according to the present invention, a first step of forming a lower layer wiring on the board and a second step of forming an interlayer connection conductor post on the lower layer wiring And the step of applying a resin around the conductor post for interlayer connection, and pressing the resin through a release film having a moderate roughness like emery paper on the surface to form an insulating layer, and The method includes a third step of exposing the upper surface of the connecting conductor post, and a fourth step of forming an upper layer wiring on the insulating layer and the interlayer connecting conductor post.
（作用） この発明によれば、基板上に形成した下層配線（第１の
工程）上に層間接続用導体ポストを先に形成した後（第
２の工程）、樹脂を塗布しこれをプレスすることにより
絶縁層を形成する（第３の工程）こととしため、絶縁層
表面に下層配線の厚みによる段差に起因した凹凸を生じ
させることなく絶縁層表面をほぼ平坦な面とすることが
でき、また、第１の工程で形成される下層配線の厚みを
厚くすることができると共に、従来のスルーホールの形
成の困難性に起因する信頼性の悪化を回避することがで
きる。特に、第３の工程において、適度な荒れをもつ離
型フィルムを介して樹脂をプレスしているため、第４の
工程において、上層配線をメッキ等の湿式のプロセスを
利用して形成することができる。(Operation) According to the present invention, after the conductor post for interlayer connection is first formed on the lower layer wiring (first step) formed on the substrate (second step), resin is applied and this is pressed. Since the insulating layer is formed by this (third step), the insulating layer surface can be made substantially flat without causing unevenness due to the step due to the thickness of the lower layer wiring on the insulating layer surface, Further, it is possible to increase the thickness of the lower layer wiring formed in the first step, and it is possible to avoid the deterioration of reliability due to the difficulty of forming a conventional through hole. In particular, in the third step, the resin is pressed through the release film having an appropriate roughness, so that the upper wiring can be formed by using a wet process such as plating in the fourth step. it can.
（実施例） 以下、この発明の多層配線基板の製造方法を実施例に基
づき図面を参照して詳細に説明する。なお、以下の実施
例では多層配線基板の製造方法の一例として二次元サー
マルヘッドの製造方法を例に挙げて説明する。(Examples) Hereinafter, a method for manufacturing a multilayer wiring board according to the present invention will be described in detail based on examples with reference to the drawings. In the following embodiments, a method for manufacturing a two-dimensional thermal head will be described as an example of a method for manufacturing a multilayer wiring board.
第１図は本発明の一実施例による二次元サーマルヘッド
の製造方法を示す工程図である。FIG. 1 is a process drawing showing a method for manufacturing a two-dimensional thermal head according to an embodiment of the present invention.
まず、第１図(a)に示すように、セラミックス等で形成
された基板１上に、無電解銅メッキ、フォトリソグラ
フ、エッチング及び電解銅パターンメッキを用いて下層
配線２を形成する。次に、第１図(b)に示すように、層
間接続用導体ポスト８を形成する部分以外にフォトリソ
を行ない、レジスト９を設ける。次に、第１図(c)に示
すように、電解メッキで層間接続用導体ポスト８を形成
し、レジスト９を剥離する。この表面に、第１(d)に示
すように、エポキシ樹脂１０（例えばエマーソンアンド
カミング社製のエコボンド５５）を塗布し、0.5μｍ〜
５μｍ程度の適度の荒れをもつエメリーペーパー（例え
ば３Ｍ社製の荒さ１μｍのもの）に離型加工を施した離
型フィルム１１を用いてエポキシ樹脂１０上を覆い、１
５kg／cm2程度のプレス圧で、約８０℃の温度で１時間
程プレスを行なってエポキシ樹脂１０を硬化させ、第１
図(e)に示すような無電解メッキに適した微細な荒れを
有する表面１４をもつ絶縁層１２を形成する。これと同
時に、層間接続用導体ポスト８の上面が絶縁層１２の表
面に露出される。次に、下層配線２を形成したのと同様
のプロセス、すなわち無電解銅メッキ、フォトリソグラ
フ、エッチング及び電解銅パターンメッキを用いて第１
図(f)に示すように上層配線１３を形成する。このと
き、層間接続用導体ポスト８も同時に電解銅メッキによ
り盛り上げておく（第１図(f)の参照番号１５の部
分）。これに再びエポキシ樹脂を塗布し、三酢酸セルロ
ースを離型フィルムとして用いプレスすると、第１図
(g)に示すように、上層配線１３がエポキシ樹脂１６で
埋め込まれた形となる。最後に、第１図(h)に示すよう
に、スパッタリング等により発熱抵抗体として窒化タン
タル層を形成し、フォトリソグラフ及びドライエッチン
グにより発熱抵抗体６を形成する。この発熱抵抗体６は
下層配線２に電気的に接続された層間接続用導体ポスト
８と上層配線１３とに接続される。そして、下層配線２
と上層配線１３との間に選択的に通電することにより選
択された発熱抵抗体６が加熱されることとなる。First, as shown in FIG. 1A, a lower layer wiring 2 is formed on a substrate 1 made of ceramics or the like by electroless copper plating, photolithography, etching and electrolytic copper pattern plating. Next, as shown in FIG. 1B, photolithography is performed on a portion other than the portion where the inter-layer connection conductor post 8 is formed, and a resist 9 is provided. Next, as shown in FIG. 1C, the conductor post 8 for interlayer connection is formed by electrolytic plating, and the resist 9 is peeled off. As shown in the first (d), epoxy resin 10 (e.g., Ecobond 55 manufactured by Emerson and Cumming) is applied to this surface, and the thickness is 0.5 .mu.m.
An epoxy resin 10 is covered with a release film 11 obtained by subjecting an emery paper having an appropriate roughness of about 5 μm (for example, a roughness of 1 μm manufactured by 3M Co., Ltd.) to a release process.
The epoxy resin 10 is cured by pressing at a pressure of about 5 kg / cm 2 for about 1 hour at a temperature of about 80 ° C.
An insulating layer 12 having a surface 14 having fine roughness suitable for electroless plating is formed as shown in FIG. At the same time, the upper surface of the conductor post 8 for interlayer connection is exposed on the surface of the insulating layer 12. Next, using the same process as that for forming the lower layer wiring 2, that is, electroless copper plating, photolithography, etching, and electrolytic copper pattern plating,
Upper layer wiring 13 is formed as shown in FIG. At this time, the conductor post 8 for interlayer connection is also raised by electrolytic copper plating at the same time (reference numeral 15 in FIG. 1 (f)). When epoxy resin is applied to this again and cellulose triacetate is used as a release film and pressed, the
As shown in (g), the upper wiring 13 is filled with the epoxy resin 16. Finally, as shown in FIG. 1 (h), a tantalum nitride layer is formed as a heating resistor by sputtering or the like, and a heating resistor 6 is formed by photolithography and dry etching. The heating resistor 6 is connected to the conductor post 8 for interlayer connection electrically connected to the lower layer wiring 2 and the upper layer wiring 13. And the lower layer wiring 2
The selected heating resistor 6 is heated by selectively energizing between the upper wiring 13 and the upper wiring 13.
以上、この発明を一実施例に基づいて説明した。この実
施例によれば、下層配線２上に層間接続用導体ポスト８
が形成された後エポキシ樹脂１０をプレスして絶縁層１
２が設けられるので、絶縁層表面に下層配線の厚みによ
る段差に起因した凹凸を生じさせることなく絶縁層表面
をほぼ平坦な面とすることができ、また、下層配線２の
厚みを厚くすることができる。また、絶縁層１２の表面
は微細な荒れをもつので、上層配線１３をコストの低い
メッキ等の湿式のプロセスを用いて形成することが可能
となる。The present invention has been described above based on the embodiment. According to this embodiment, the conductor post 8 for interlayer connection is formed on the lower layer wiring 2.
After the resin is formed, the epoxy resin 10 is pressed to insulate the insulating layer 1
2 is provided, it is possible to make the surface of the insulating layer a substantially flat surface without causing unevenness due to the step due to the thickness of the lower layer wiring on the surface of the insulating layer, and to increase the thickness of the lower layer wiring 2. You can Further, since the surface of the insulating layer 12 has fine roughness, the upper wiring 13 can be formed by a low-cost wet process such as plating.
次に、この発明の他の実施例として、一般的な多層配線
基板の製造方法について、以下に説明する。Next, as another embodiment of the present invention, a general method for manufacturing a multilayer wiring board will be described below.
ここでは、まず、前述の実施例に示される第１図(a)〜
(e)までの各工程を実施することにより、基板１上に、
下層配線２、層間接続用導体ポスト８。絶縁層１２を順
次形成する。次いで、無電解鋼メッキ、フォトリソグラ
フ、エッチング、及び電解銅パターンメッキにより絶縁
層１２上及び層間接続用導体ポスト８上に上層配線１３
を形成する。この上層配線１３は層間接続用導体ポスト
８を介して所定の下層配線２と接続される。これによ
り、この実施例による多層配線基板が完成する。Here, first, FIG. 1 (a) to FIG.
By performing each step up to (e), on the substrate 1,
Lower layer wiring 2, conductor post 8 for interlayer connection. The insulating layer 12 is sequentially formed. Then, by electroless steel plating, photolithography, etching, and electrolytic copper pattern plating, the upper wiring 13 is formed on the insulating layer 12 and the conductor posts 8 for interlayer connection.
To form. The upper layer wiring 13 is connected to a predetermined lower layer wiring 2 via the interlayer connecting conductor post 8. As a result, the multilayer wiring board according to this embodiment is completed.
尚、この発明を実施する当り、用いられる材料等は上記
実施例に限定されず、他の材料を用いて同様に実施でき
る。例えば、下層配線２及び上層配線１３は銅に限定さ
れず、金等の他の金属を用いてもよい。また、絶縁層１
２はエポキシ樹脂に限定されず、硬化したときに体積変
化の少ない種々の樹脂が適用可能である。In carrying out the present invention, the materials and the like used are not limited to those in the above embodiment, and other materials can be used in the same manner. For example, the lower layer wiring 2 and the upper layer wiring 13 are not limited to copper, and other metals such as gold may be used. Also, the insulating layer 1
No. 2 is not limited to epoxy resin, and various resins having a small volume change when cured are applicable.
（発明の効果） 以上説明したように、この発明による多層配線基板の製
造方法によれば、下層配線上に層間接続用導体ポストを
形成した後、樹脂をプレスすることにより絶縁層を形成
することとしため、絶縁層表面に下層配線の厚みによる
段差に起因した凹凸を生じさせることなく絶縁層表面を
ほぼ平坦な面とすることができ、また、下層配線の厚み
を厚くすることができる。また、樹脂をプレスする際に
エメリーペーパー状の適度な荒れを有する離型フィルム
を用いているため、上層配線の形成を湿式のプロセスで
行なうのに適した表面をもつ絶縁層を得ることとができ
る。(Effect of the Invention) As described above, according to the method for manufacturing a multilayer wiring board according to the present invention, after forming the interlayer connection conductor post on the lower layer wiring, the resin is pressed to form the insulating layer. Therefore, it is possible to make the surface of the insulating layer a substantially flat surface without causing unevenness due to the step due to the thickness of the lower layer wiring on the surface of the insulating layer, and to increase the thickness of the lower layer wiring. Further, since a release film having an appropriate roughness like an emery paper is used when pressing the resin, it is possible to obtain an insulating layer having a surface suitable for forming the upper wiring by a wet process. it can.
第１図(a)〜(h)はこの発明の一実施例による二次元サー
マルヘッドの製造方法を示す工程図、及び第２図(a)〜
(e)は従来の二次元サーマルヘッドの製造方法を示す工
程図である。 １……基板、２……下層配線、 ６……発熱抵抗体、８……層間接続用導体ポスト、 ９……レジスト、10……エポキシ樹脂、 11……離型フィルム、12……絶縁層、 13……上層配線、14……絶縁層の表面、 16……エポキシ樹脂。1 (a) to 1 (h) are process drawings showing a method of manufacturing a two-dimensional thermal head according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (h).
(e) is a process drawing showing a conventional method for manufacturing a two-dimensional thermal head. 1 ... Substrate, 2 ... Lower wiring, 6 ... Heating resistor, 8 ... Interlayer connection conductor post, 9 ... Resist, 10 ... Epoxy resin, 11 ... Release film, 12 ... Insulating layer , 13 …… upper layer wiring, 14 …… insulating layer surface, 16 …… epoxy resin.
フロントページの続き (72)発明者 鶴岡 泰治 東京都港区虎ノ門１丁目７番12号 沖電気 工業株式会社内 (56)参考文献 特開 昭61−179597（ＪＰ，Ａ)Front page continued (72) Inventor Taiji Tsuruoka 1-7-12 Toranomon, Minato-ku, Tokyo Within Oki Electric Industry Co., Ltd. (56) Reference JP-A-61-179597 (JP, A)
Claims (1)
と、 前記下層配線上に層間接続用導体ポストを形成する第２
の工程と、 前記層間接続用導体ポストの周囲に樹脂を塗布し、表面
にエメリーペーパー状の適度な荒れをもつ離型フィルム
を介して前記樹脂をプレスして絶縁層を形成し、かつ前
記層間接続用導体ポストの上面を露出させる第３の工程
と、 前記絶縁層の上部および前記層間接続用導体ポストの上
部に上層配線を形成する第４の工程とを有することを特
徴とする多層配線基板の製造方法。1. A first step of forming a lower layer wiring on a substrate, and a second step of forming a conductor post for interlayer connection on the lower layer wiring.
A step of applying a resin around the conductor post for interlayer connection, and pressing the resin through a release film having a moderate roughness like emery paper on the surface to form an insulating layer, and A multilayer wiring board comprising: a third step of exposing the upper surface of the connecting conductor post; and a fourth step of forming an upper layer wiring on the insulating layer and on the interlayer connecting conductor post. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60020962A JPH0657455B2 (en) | 1985-02-07 | 1985-02-07 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60020962A JPH0657455B2 (en) | 1985-02-07 | 1985-02-07 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61181662A JPS61181662A (en) | 1986-08-14 |
| JPH0657455B2 true JPH0657455B2 (en) | 1994-08-03 |
Family
ID=12041796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60020962A Expired - Lifetime JPH0657455B2 (en) | 1985-02-07 | 1985-02-07 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0657455B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4247880B2 (en) * | 2002-12-24 | 2009-04-02 | Ｔｄｋ株式会社 | Manufacturing method of electronic parts |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61179597A (en) * | 1985-02-04 | 1986-08-12 | 沖電気工業株式会社 | Formation of multilayer interconnection |
-
1985
- 1985-02-07 JP JP60020962A patent/JPH0657455B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61181662A (en) | 1986-08-14 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |