JPH065748A - Mounting structure for semiconductor chip - Google Patents
Mounting structure for semiconductor chipInfo
- Publication number
- JPH065748A JPH065748A JP4159643A JP15964392A JPH065748A JP H065748 A JPH065748 A JP H065748A JP 4159643 A JP4159643 A JP 4159643A JP 15964392 A JP15964392 A JP 15964392A JP H065748 A JPH065748 A JP H065748A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- heat transfer
- transfer piece
- mounting
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07221—Aligning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】半導体チップの実装構造に係り、特にフリップ
チップ実装において、半導体チップ上に放熱手段を重ね
て設けたりすることなく、放熱手段を構成し、電子機器
の小型化を図る。
【構成】半導体チップ１の回路面１１と基板表面２１と
の間に伝熱片３を介在して基板２側へ放熱するように
し、かつ伝熱片３を弾性材より構成するとともに、高さ
Ｈを実装時の間隙Ｄよりも大きくして、圧縮変形状態で
実装し、接続を確実に行う。
(57) [Abstract] [Purpose] The present invention relates to a mounting structure of a semiconductor chip, and particularly in flip-chip mounting, the heat dissipation means is configured without overlapping the heat dissipation means on the semiconductor chip to reduce the size of electronic equipment. Try. [Structure] A heat transfer piece 3 is interposed between a circuit surface 11 of a semiconductor chip 1 and a board surface 21 to radiate heat to the board 2 side, and the heat transfer piece 3 is made of an elastic material and has a height. H is made larger than the gap D at the time of mounting to mount in a compressive deformed state to securely connect.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップの実装構
造に係り、特に半導体チップにパッケージングを行わず
に実装するフリップチップ実装において、放熱を良好に
する半導体チップの実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting structure and, more particularly, to a semiconductor chip mounting structure for improving heat dissipation in flip chip mounting which is mounted on a semiconductor chip without packaging. .
【０００２】近年、半導体チップの実装構造において
は、電子機器の小型化の要求に伴い、基板上への実装密
度を高めるため、半導体チップにパッケージングを行わ
ずに実装するフリップチップ実装が行われている。しか
し、高発熱型の半導体チップをフリップチップ実装する
場合には、パッケージングを利用した放熱手段が構成で
きず、加熱が問題となるため、放熱機能の高い半導体チ
ップの実装構造が求められている。In recent years, in the mounting structure of a semiconductor chip, flip chip mounting has been performed in which the semiconductor chip is mounted without packaging in order to increase the mounting density on a substrate in accordance with the demand for miniaturization of electronic devices. ing. However, in the case of flip chip mounting of a high heat generation type semiconductor chip, a heat dissipation means utilizing packaging cannot be configured and heating becomes a problem. Therefore, a semiconductor chip mounting structure having a high heat dissipation function is required. .
【０００３】[0003]
【従来の技術】従来、半導体チップの実装構造において
は、フリップチップ実装した半導体チップの放熱のため
に半導体チップの背面に冷却フィンを取り付けたり、熱
伝導モジュールを取り付けることによって、半導体チッ
プの加熱を防止していた。2. Description of the Related Art Conventionally, in a semiconductor chip mounting structure, the semiconductor chip is heated by mounting a cooling fin on the back surface of the semiconductor chip or mounting a heat conduction module for heat dissipation of the flip chip mounted semiconductor chip. Had been prevented.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
構成では半導体チップの背面に冷却フィンや熱伝導モジ
ュールを取り付けるため、電子機器の充分な小型化を図
ることができず、また製造も面倒であるという欠点があ
った。However, in the conventional structure, since the cooling fins and the heat conduction module are attached to the back surface of the semiconductor chip, it is not possible to sufficiently reduce the size of the electronic device and the manufacturing is troublesome. There was a drawback.
【０００５】従って、本発明は、特に実装密度の高密度
化を図るフリップチップ実装において、半導体チップ上
に積み重ねたりすることなく放熱手段を形成して、電子
機器の小型化を図ることのできる半導体チップの実装構
造を提供することを目的とする。Therefore, according to the present invention, particularly in flip-chip mounting in which the mounting density is increased, the heat radiation means is formed without stacking on the semiconductor chip, and the electronic device can be miniaturized. It is intended to provide a chip mounting structure.
【０００６】[0006]
【課題を解決するための手段】上記目的は、半導体チッ
プ１の回路面１１と基板２との間に、熱伝導性を有する
とともに、弾性変形可能な伝熱片３を介在し、かつ前記
伝熱片３の高さＨが、前記回路面１１と基板表面２１と
の間隙Ｄよりも大きく形成され、前記伝熱片３を圧縮変
形して前記回路面１１と基板表面２１とを接続してなる
ことを特徴とする半導体チップの実装構造、によって達
成される。The above-mentioned object is to provide a heat transfer piece 3 which is thermally conductive and elastically deformable between the circuit surface 11 of the semiconductor chip 1 and the substrate 2, The height H of the heat piece 3 is formed to be larger than the gap D between the circuit surface 11 and the substrate surface 21, and the heat transfer piece 3 is compressed and deformed to connect the circuit surface 11 and the substrate surface 21. And a semiconductor chip mounting structure.
【０００７】[0007]
【作用】すなわち、本発明においては、熱伝導率の大き
い伝熱片３を介在することにより、半導体チップ１の回
路面１１の発熱を伝熱片３を介して基板２へ伝え、放熱
面積の大きい基板２から効率的に放熱することができる
もので、伝熱片３を弾性材により形成して、弾性変形さ
せることにより、確実に半導体チップ１の発熱部と基板
２を熱伝導状態で接続することができ、実装高さの誤差
を吸収して容易に実装することができるものである。That is, in the present invention, by interposing the heat transfer piece 3 having a large thermal conductivity, the heat generated on the circuit surface 11 of the semiconductor chip 1 is transmitted to the substrate 2 through the heat transfer piece 3 to reduce the heat dissipation area. It can efficiently dissipate heat from a large substrate 2. By forming the heat transfer piece 3 with an elastic material and elastically deforming it, the heat generating portion of the semiconductor chip 1 and the substrate 2 are reliably connected in a heat conductive state. Therefore, the mounting height error can be absorbed and the mounting can be easily performed.
【０００８】[0008]
【実施例】以下、本発明の実施例を図１を用いて詳細に
説明する。図１において（Ａ）は、伝熱片３を取り付け
た基板２を示す図であり、（Ｂ）は、半導体チップ１を
実装した状態を示すものである。Embodiments of the present invention will be described in detail below with reference to FIG. In FIG. 1, (A) is a diagram showing the substrate 2 to which the heat transfer piece 3 is attached, and (B) is a state in which the semiconductor chip 1 is mounted.
【０００９】半導体チップ１は、回路面１１を基板２の
基板表面２１側へ向けて実装されるように、回路面１１
側に、半田あるいは金のバンプ１２を形成している。そ
して、回路面１１の表面にはガラスあるいはポリイミド
の薄膜層１３が形成され、回路面１１を絶縁保護してい
る。The semiconductor chip 1 is mounted so that the circuit surface 11 is mounted with the circuit surface 11 facing the substrate surface 21 side of the substrate 2.
Solder or gold bumps 12 are formed on the side. Then, a thin film layer 13 of glass or polyimide is formed on the surface of the circuit surface 11 to insulate and protect the circuit surface 11.
【００１０】基板２は、半導体チップ１の搭載部分に電
極２２を半導体チップ１のバンプ１２に対応するように
形成している。さらに、電極２２、２２間には断面アー
チ状の伝熱片３の脚部３１固定して、伝熱片３が弾性変
形可能なように取り付けられている。The substrate 2 has electrodes 22 formed on the mounting portion of the semiconductor chip 1 so as to correspond to the bumps 12 of the semiconductor chip 1. Further, between the electrodes 22, 22, a leg portion 31 of the heat transfer piece 3 having an arch-shaped cross section is fixed, and the heat transfer piece 3 is attached so as to be elastically deformable.
【００１１】伝熱片３は、銅等の熱伝導率が高く、しか
も弾性変形可能な材質より形成され、弾性変形を効果的
に行うように、図１（Ａ）に示すように、断面アーチ状
の突面部３２が形成されている。さらに、伝熱片３の高
さは、半導体チップ１の非搭載時においては、図１
（Ａ）に示すように高さＨで形成されるが、半導体チッ
プ１の搭載状態においては、Ｈ＞Ｄとなるような搭載間
隙Ｄに圧縮変形するようになっている。The heat transfer piece 3 is made of a material having a high thermal conductivity such as copper and capable of being elastically deformed. As shown in FIG. The projecting surface portion 32 is formed. Further, the height of the heat transfer piece 3 is as shown in FIG. 1 when the semiconductor chip 1 is not mounted.
Although it is formed with a height H as shown in (A), it is adapted to be compressed and deformed into a mounting gap D such that H> D when the semiconductor chip 1 is mounted.
【００１２】すなわち、半導体チップ１の搭載時には、
半導体チップ１のバンプ１２を基板２の電極２２に押圧
状態にしてバンプ１２を接合するため、伝熱片３の突面
部３２は、圧縮変形した状態で、半導体チップ１と基板
２との間に介在される。従って、伝熱片３の突面部３２
は偏平状に変形して確実に半導体チップ１の回路面１１
に接触して、脚部３１を介して基板１へ熱を伝えること
ができる。That is, when the semiconductor chip 1 is mounted,
Since the bump 12 of the semiconductor chip 1 is pressed against the electrode 22 of the substrate 2 to bond the bump 12, the projecting surface portion 32 of the heat transfer piece 3 is compressed and deformed between the semiconductor chip 1 and the substrate 2. Intervened. Therefore, the projecting surface portion 32 of the heat transfer piece 3
Is deformed into a flat shape and surely the circuit surface 11 of the semiconductor chip 1
The heat can be transferred to the substrate 1 via the leg portions 31 by contacting with.
【００１３】なお、図１において、伝熱片１は、帯状に
形成されるほか、中央を突出させた円板状に形成しても
よい。また、伝熱片１の弾性変形による復元力が、バン
プ２の接合強度よりも充分小さくなるようにして、バン
プ１２の剥離が生じないように設定されている。In addition, in FIG. 1, the heat transfer piece 1 may be formed in a belt shape, or may be formed in a disk shape with its center protruding. Further, the restoring force due to the elastic deformation of the heat transfer piece 1 is set sufficiently smaller than the bonding strength of the bumps 2 so that the bumps 12 are not separated.
【００１４】図２（Ａ）および（Ｂ）は、伝熱片３の変
形例を示すもので、弾性を有する中空の樹脂球３３の表
面に熱伝導率の高い銅メッキ層３４を形成して、伝熱片
３に弾性と伝熱性を付与するようにしたものである。な
お、樹脂球３３に代えて、管状の樹脂心材を用いたり、
上下の接合部分を予め偏平状に形成して、接合面積を広
くして、伝熱効果を高めるようにすることもできる。2A and 2B show a modification of the heat transfer piece 3, in which a copper plating layer 34 having a high thermal conductivity is formed on the surface of a hollow resin sphere 33 having elasticity. The heat transfer piece 3 is made to have elasticity and heat transfer properties. In place of the resin balls 33, a tubular resin core material may be used,
It is also possible to form the upper and lower joints in a flat shape in advance to widen the joint area and enhance the heat transfer effect.
【００１５】なお、上記実施例においては、伝熱片３を
基板２側に予め固定するもので説明したが、半導体チッ
プ１側に予め固定しておくものでも良い。In the above embodiment, the heat transfer piece 3 is fixed to the substrate 2 side in advance, but it may be fixed to the semiconductor chip 1 side in advance.
【００１６】[0016]
【発明の効果】以上説明したように、本発明において
は、フリップチップ実装のように、半導体チップの放熱
手段の構成が難しい実装構造においても、伝熱片を基板
との間に介在するだけの簡単な構成によって、半導体チ
ップの発熱を放熱面積の大きい基板へ逃がして放熱する
ことができるため。半導体チップの上面に放熱手段を突
設したりする必要がなく、電子機器の小型化を可能と
し、加熱による誤動作を防止することができる。As described above, according to the present invention, even in the mounting structure in which the heat dissipating means of the semiconductor chip is difficult, such as the flip chip mounting, the heat transfer piece is merely interposed between the heat transfer piece and the substrate. With a simple structure, the heat generated by the semiconductor chip can be radiated to the substrate with a large heat dissipation area. It is not necessary to dispose a heat dissipation means on the upper surface of the semiconductor chip, which enables downsizing of electronic equipment and prevents malfunction due to heating.
【図１】本発明の実施例を示す図で、（Ａ）は、半導体
チップの搭載前の基板を示す断面図、（Ｂ）は、半導体
チップの搭載状態を示す断面図である。1A and 1B are views showing an embodiment of the present invention, FIG. 1A is a sectional view showing a substrate before mounting a semiconductor chip, and FIG. 1B is a sectional view showing a mounting state of a semiconductor chip.
【図２】本発明の実施例の変形例を示す図で、（Ａ）
は、半導体チップの搭載前の基板を示す断面図、（Ｂ）
は、半導体チップの搭載状態を示す断面図である。FIG. 2 is a view showing a modified example of the embodiment of the present invention, (A)
Is a cross-sectional view showing a substrate before mounting a semiconductor chip, (B)
FIG. 4 is a cross-sectional view showing a mounted state of a semiconductor chip.
１ 半導体チップ １１ 回路面 ２ 基板 ２１ 基板表面 ３ 伝熱片 1 Semiconductor Chip 11 Circuit Surface 2 Substrate 21 Substrate Surface 3 Heat Transfer Piece
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 直樹 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Nakamura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited
Claims (1)
(2) との間に、熱伝導性を有するとともに、弾性変形可
能な伝熱片(3) を介在し、かつ前記伝熱片(3)の高さ(H)
が、前記回路面(11)と基板表面(21)との間隙(D) より
も大きく形成され、前記伝熱片(3) を圧縮変形して前記
回路面(11)と基板表面(21)とを接続してなることを特徴
とする半導体チップの実装構造。1. A circuit surface (11) of a semiconductor chip (1) and a substrate.
A heat transfer piece (3), which has thermal conductivity and is elastically deformable, is interposed between (2) and the height (H) of the heat transfer piece (3).
Is formed larger than the gap (D) between the circuit surface (11) and the substrate surface (21), and the heat transfer piece (3) is compressed and deformed to cause the circuit surface (11) and the substrate surface (21). A mounting structure for a semiconductor chip, characterized in that it is formed by connecting and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15964392A JP3265544B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15964392A JP3265544B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH065748A true JPH065748A (en) | 1994-01-14 |
| JP3265544B2 JP3265544B2 (en) | 2002-03-11 |
Family
ID=15698200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15964392A Expired - Fee Related JP3265544B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3265544B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2017122254A1 (en) * | 2016-01-15 | 2018-11-08 | パナソニックＩｐマネジメント株式会社 | Electronics |
| EP3817518A1 (en) * | 2019-10-31 | 2021-05-05 | Aptiv Technologies Limited | A method for manufacturing a circuit board, and associated circuit board |
-
1992
- 1992-06-18 JP JP15964392A patent/JP3265544B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2017122254A1 (en) * | 2016-01-15 | 2018-11-08 | パナソニックＩｐマネジメント株式会社 | Electronics |
| EP3817518A1 (en) * | 2019-10-31 | 2021-05-05 | Aptiv Technologies Limited | A method for manufacturing a circuit board, and associated circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3265544B2 (en) | 2002-03-11 |
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