JPH0660645A - Power saving storage device - Google Patents

Abstract

(57) [Summary] [Object] To provide a memory device in which power consumption is reduced in a memory device using a DRAM. [Structure] The detection means 1 detects whether the memory 5 is in use or not. The selection means 4 refreshes the memory with the normal refresh signal 12 from the normal refresh circuit 2 when the result detected by the detection means is in use, and the backup refresh from the backup refresh circuit 3 when the detection result is not used. The signal 13 refreshes the memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power saving type memory device, and more particularly to a power saving type memory device using a DRAM as a memory element.

[0002]

2. Description of the Related Art Conventionally, in a battery-powered information processing apparatus (hereinafter referred to as a personal computer), power consumption has been reduced (hereinafter referred to as low power consumption) in order to extend the continuous operation time of the battery. There is. As part of such low consumption,
The semiconductor memory element portion (hereinafter, referred to as a memory), which is one of the components of a personal computer, is also being reduced in power consumption. And since the memory capacity of personal computers tends to increase in recent years, it is important to reduce memory consumption.
In particular, the aforementioned low consumption is indispensable for DRAM, which has a large ratio in cost and capacity among memories.

The power consumption reducing means in the memory can be roughly divided into the following two means. The first means is a means for reducing power consumption during operation of the memory. Specifically, the operation current is reduced and the operation voltage is lowered, and in a typical DRAM, the DRAM has a long refresh cycle. It is becoming. The second means is a means for cutting off the power of the unused memory. For example, as disclosed in Japanese Unexamined Patent Publication No. 64-51512 and Japanese Unexamined Patent Publication No. 2-232752, there is a method of detecting an unused memory and cutting off and stopping the power supply.

[0004]

However, the above-mentioned "reduction of power consumption while the memory is operating" has no great effect, and only a numerical value such as a reduction of several tens of percent from the conventional value can be achieved. There is little effect on. In contrast,
The "means for cutting off unused memory power" has a great effect in terms of low power consumption since the power consumption becomes 0.
It is applicable to all systems regardless of memory type. However, the memory that has been used even once after the system starts operating cannot be reduced in power consumption because the power is always on thereafter. The reason is that necessary data has been input to the memory once used, and the data will be lost when the power is turned off. The means for cutting off the power in this way has a disadvantage when the information processing apparatus is actually used.

Further, when a memory whose power supply is cut off is used, it takes a startup time after the power is turned on again until the memory is actually ready for use, so that the system performance is deteriorated. Therefore, an object of the present invention is to extend the continuous operation time of a battery in a memory using a DRAM that requires a refresh operation without losing the data in the memory, and reduce the system performance. An object of the present invention is to provide a power-saving memory device without a problem.

[0006]

According to a first aspect of the present invention, there is provided an information processing apparatus, wherein a memory is constituted by a DRAM and the memory is selectively used in either an operation mode or a data holding mode. Detecting means for detecting whether or not the memory is in use, a normal refresh circuit for performing a refresh operation in a normal operation mode when the memory is in use, and a refresh operation in a data holding mode when the memory is not in use And a refresh operation of the memory on the basis of a signal from the detecting means, either a refresh operation in an operation mode from the normal refresh circuit or a refresh operation in a data holding mode from the backup refresh circuit. Configuration with switching selection means To achieve the above object Te. Claim 2
In the invention described above, the mechanism for selectively using the memory is configured by an EMS or a bank switching system to achieve the above object. In a third aspect of the present invention, the mechanism for selectively using the memory is configured by a cache system to achieve the above object. According to the invention of claim 4,
The object is achieved by executing the switching of the refresh circuit by the selecting means by a program.

[0007]

In the power saving type memory device according to the first aspect, the detecting means detects whether or not the memory is in use. The selecting means performs the refresh operation in the normal operation mode by the normal refresh signal from the normal refresh circuit when the memory is in use, and the data holding mode by the backup refresh signal from the backup refresh circuit when the memory is not used. Perform a refresh operation. In this way, the refresh current is switched depending on whether the memory is used or not used, so that the power consumption of the entire memory device can be reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a power saving type memory device of the present invention will be described in detail below with reference to FIGS. (1) Principle Configuration and Operation FIG. 1 shows a block diagram of the principle configuration of the present invention. As shown in FIG. 1, a power-saving memory device using a DRAM that requires a refresh operation includes a detection unit 1 that detects whether the memory 5 is in use or an unused state, and a normal device when the memory 5 is in use. A normal refresh circuit 2 that performs a refresh operation in an operation mode, a backup refresh circuit 3 that performs a refresh operation in a data holding mode when the memory 5 is unused, a signal indicating the busy state from the detection means 1 and an unused signal. The selection means 4 selects whether the refresh operation of the memory 5 is in use or not based on the signal shown.

The detection means 1 detects whether the memory is in use or is unused and outputs a busy signal 10 or an unused signal 11 to the selection means 4. The selection means 4
Selects the normal refresh signal 12 from the normal refresh circuit 2 and outputs it as the refresh signal 14 to the memory 5 when the busy signal 10 is valid, and the backup refresh circuit 3 when the unused signal 11 is valid. The backup refresh signal 13 is selected and output to the memory 5 as the refresh signal 14. Here, the normal refresh and the backup refresh will be described.

Model name of semiconductor data book: μPD426
According to 07 (product name: silicon file, a kind of DRAM), the refresh current is 10 at the time of RAS only refresh and CAS before RAS refresh.
mA (MAX). On the other hand, the current during self-refresh is 30 μA (0 ° C. to 50 ° C., MAX), 6
0 μA (0 ° C. to 60 ° C., MAX), 120 μA (0 ° C. to
70 ° C, MAX). At the time of RAS only refresh or CAS before RAS refresh, since it can be mixed with read / write, it is refresh when the memory is being used (read / write) (normal operation mode).

Self-refresh is unused (no read / write) because it cannot be mixed with read / write.
Data is refreshed while it is being held (data holding mode). In this way, the refresh performed during use (read / write) is referred to as normal refresh, and the refresh during data retention only when not used (no read / write) is referred to as backup refresh.

FIG. 2A shows μ at the time of normal refresh.
The timing of each control signal of the PD42601 is shown in FIG.
(B) shows the timing of each control signal at the time of backup refresh. As described above, according to the present invention, in a memory using a DRAM that requires a refresh operation, an unused memory is detected, and the data is held in the memory, whereby the data in the memory can be lost. It is possible to achieve a large reduction in consumption. Further, according to this method, since the memory can be switched to the unused state or the used state without any limitation, the effect of reducing the system consumption is great, and the continuous operation time in the battery can be extended. Furthermore, since the unused state and the used state can be rapidly changed, the system performance is not deteriorated.

(2) Specific Configuration and Operation Next, a specific circuit configuration and its operation will be described. EMS (Lotus In
tel Microsoft expanded memory specification) has become popular. FIG. 3 shows a method of selecting a memory in EMS. The real address memory shown in FIG. 3A is an area that can be actually read / written. Figure 3 (B)
Is a set of memories prepared as EMS memory. In FIG. 3, four memories can be used as the real address memories, and the shaded areas A, B, C, and D of the EMS memory are allocated to the four memories and are in use.
This is shown in a block diagram in FIG. As shown in FIG. 4, the memory 21 corresponds to the EMS memory shown in FIG. The EMS controller 22 uses registers R1 to R4.
And the address conversion unit 22a, and controls the EMS memory to correspond to the real address memory. As a corresponding method, the address conversion unit 22a generates a memory address and a control signal according to the values set in the registers R1 to R4 in the EMS memory.

Therefore, the memory to be used can be determined by outputting the contents of the registers R1 to R4 to the detecting means 1. The signal from the detecting means 1 to the selecting means 4 informs the use or non-use of each of the plurality of memories (A to H), so that the selecting means 4 also performs normal refresh or backup refresh on each memory. Similarly bank system, there is a bank system as a selection method of a memory. FIG. 5 shows a memory map of the bank system, and FIG. 6 shows a block diagram of the bank system. In FIG. 5, the shaded bank B2 is selected (that is, assigned). The operation of the block diagram of FIG. 6 is the same except that the EMS controller of the EMS block of FIG. 4 is changed to the bank controller 31.

A cache system is also conceivable as a method of selecting and using the cache system memory. FIG. 7 shows a block diagram of the cache system. When the cache hits, the CPU
When the is accessed, the cache is in use and the memory is not used, and when the cache misses and the memory is accessed, the memory is in use and the cache is unused. Therefore, the signal to the detection means 1 becomes a signal indicating a cache hit or miss. Although the three memory selection systems have been described above, it goes without saying that the present invention can be applied to other memory selection systems. In addition, in the present embodiment, the method has been described in which the memory is a DRAM and the refresh operation is switched.
Of course, any device having a data retention or power saving mode can be easily applied.

Furthermore, although the present invention can achieve low power consumption in backup refresh, some users may demand even higher performance than low power consumption. In that case, it becomes possible by inputting a signal for enabling or disabling the execution of the switching to the selecting means shown in FIG. Programmatically turns on / off this signal control
By using the output signal at the F-controllable port, selection by a program can be easily performed.

[0017]

As described above, according to the present invention, it is possible to reduce the current consumption of the memory by using the refresh operation of the memory and the operation of which the current consumption is small, and thus to reduce the battery consumption of the system. It is possible to extend the continuous operation time in.

[Brief description of drawings]

FIG. 1 is a block diagram of a principle configuration of the present invention.

FIG. 2A is a diagram showing an example of the timing of control signals at the time of normal refresh in the present invention, and FIG. 2B is a diagram showing an example of the timing of control signals at the time of backup refresh.

FIG. 3 is a diagram showing a method of selecting a memory in the EMS according to the embodiment of the present invention.

FIG. 4 is a block diagram of an embodiment when the EMS is used.

FIG. 5 is a memory map in an embodiment when a bank method is used.

FIG. 6 is a block diagram when the bank method is used.

FIG. 7 is a block diagram of an embodiment when a cache system is used.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 detection means 2 normal refresh circuit 3 backup refresh circuit 4 selection means 5 memory 10 in-use signal 11 unused signal 12 normal refresh signal 13 backup refresh signal 14 refresh signal

Claims (4)

[Claims] 1. An information processing apparatus comprising a memory constituted by a DRAM and selectively using either the operation mode or the data holding mode, the detecting means detecting whether or not the memory is in use. A normal refresh circuit that performs a refresh operation in a normal operation mode when the memory is in use; a backup refresh circuit that performs a refresh operation in a data retention mode when the memory is not in use; Selection means for switching the refresh operation of the memory to either the refresh operation in the operation mode from the normal refresh circuit or the refresh operation in the data holding mode from the backup refresh circuit based on a signal. Power saving memory device. 2. A mechanism for selectively using the memory comprises:
The power saving memory device according to claim 1, wherein the power saving memory device is an EMS or a bank switching system. 3. A mechanism for selectively using the memory comprises:
The power-saving memory device according to claim 1, wherein the power-saving memory device is a cache system. 4. The power-saving memory device according to claim 1, wherein the switching of the refresh circuit by the selecting means is performed by a program.