JPH0660656A - Semiconductor storage - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a semiconductor memory that can exchange two rows of data on a chip at high speed. [Configuration] Two sense amplifiers SA1 and SA2 are provided for each bit line pair BL and bar BL, and an NMOS transistor T, is provided between one sense amplifier SA1 and the bit line pair.
Insert T '. After reading the data of one word line WL _m and amplifying and latching it by the one sense amplifier SA1, the NMOS transistors T and T ′ are turned off. After that, the data of the other word line WL _n is read, amplified by the other sense amplifier SA2, and written in the memory cell of the former word line WL _m . After that, the NMOS transistors T and T'are turned on to turn on the former sense amplifier SA.
The data latched at 1 is written in the memory cell of the latter word line WL _n .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory such as a DRAM, and more particularly to a semiconductor memory on a memory chip.
A semiconductor memory capable of exchanging data in one row at high speed.

[0002]

2. Description of the Related Art Conventionally, when it is desired to exchange data on one memory, it has been realized by giving an address for each word via a CPU and repeating the operation of transferring the data. FIG. 2 is a conceptual diagram of a conventional system, where 1 is a memory and 2 is a CPU.

[0003]

In the conventional memory device described above, when the data of two rows are exchanged, as shown in FIG. 2, the CPU 2 gives an address to the memory 1 word by word, and Since the operation of reading data, writing one data from the CPU 2 to the memory 1 for each word and writing it in the other line, and writing the other data in the previous line, is proportional to the number of data. Then, there is a problem that the transfer time increases.

The present invention has been made in view of the above problems of the prior art, and provides a semiconductor memory capable of exchanging data in two rows at high speed.

[0005]

In a memory having a normal word line and a bit line, two sense amplifiers are provided for each bit line pair, and one sense amplifier and the bit line pair are provided between the sense amplifier and the bit line pair. A switching means for controlling conduction / interruption, for example, an NMOS transistor is inserted. 1
After the data of one word line is read and amplified and latched by the one sense amplifier, the switching means is turned off. After that, the data of the other word line is read, amplified by the other sense amplifier, and written in the memory cell of the former word line. After that, the switching means is turned on to write the data latched by the former sense amplifier into the memory cell of the latter word line.
By the above, the exchange of the data of the two word lines is completed.

[0006]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of a semiconductor memory according to an embodiment of the present invention.

In the figure, WL ₀ , ..., WL _m , ... W
L _n , ... Are word lines, BL ₀ , bars BL ₀ , ... Are bit line pairs, M ₀₀ , ..., M ₀₂ , ... M _n0 , ..., M _n2 ... Are memory cells, BLEQ ₀ ,. Circuit.
As shown in the figure, each bit line pair (BL ₀ , bar BL ₀ ),
(BL ₁ , bar BL ₁ ), ..., Two sense amplifiers (SA1 ₀ , SA2 ₀ ), (SA1 ₁ , SA)
2 ₁ ), ... are provided. In addition, each bit line pair (B
Between L ₀ , bar BL ₀ ), (BL ₁ , bar BL ₁ ), ... And sense amplifiers SA1 ₀ , SA1 ₁ ,.
OS transistors (T ₀ , T ₀ ′), (T ₁ , T ₁ ′), ...
Has been inserted. The sense amplifiers SA2 ₀ and SA
2 ₁ , ... Are NMOS transistors (CT ₀ , CT ₀ ′) which are on / off controlled by the column decoder output,
It is connected to the data line DL and the bar DL via (CT ₁ , CT ₁ ′).

The row data exchange method according to the present invention will be described below with reference to FIG. As shown in the figure, in a normal memory in which the memory cell M exists at the intersection of the word line WL and the bit line BL or bar BL, the bit line pair BL _p
, And the bar BL _p (hereinafter, p = 0, 1, ... Means the memory column number) are equalized by the equalizing circuit BLEQ _p , and then the m-th word line WL _m is raised to the H level, An NMOS transistor T _p placed between the line pair BL _p , bar BL _P and the sense amplifier SA1p
, And the gates of T _p ′ are set to H level, and the data of the memory cell Mm _p connected to the word line WL _m is transferred to the bit line pair BL _p.
And bar BL _p , and after amplification by the sense amplifier SA1 _p , the gates of the NMOS transistors T _p and T _p ′ are set to L level, and the data is sensed by the sense amplifier SA1 _p.
Latch to. Again, the bit line pair BL _p and bar BL
The _p, was equalized by the equalizing circuit BLEQ _p, launched n-th word line WL _n to H level, the read data of the memory cell M _np that led to the word line WL _n bit line pairs BLp and bar BL _p After amplification by the sense amplifier SA2 _p , the word line WL _n is lowered to L level, the word line WL _m is raised to H level, and data is written to the memory cell M _mp connected to the word line WL _m . The word line WL _m is lowered to L level. As a result, the data in the memory cell on the word line WL _n is transferred to the memory cell on the word line WL _m . Next, again, the bit line pair BL _p and the bar BL _p
Is equalized by the equalizing circuit BLEQ _p ,
The data previously latched in the sense amplifier SA1 _p is stored in the memory cell on the word line WL _n by setting the gates of the NMOS transistors T _p and T _p ′ to the H level and raising the word line WL _n to the H level. Write to M _np . Finally, the word line WL _n and the gates of the NMOS transistors T _p and T _p ′ are lowered to the L level. As described above, the data of the memory cell on the word line WL _m and the data of the memory cell on the word line WL _n are exchanged.

[0010]

As described above in detail, according to the present invention, one row in a memory chip can be read without repeating the operation of reading and writing data of two rows by giving an address from an external CPU. Since it is possible to process all the data in batch, the transfer time can be shortened regardless of the number of data in one row.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory according to the present invention.

FIG. 2 is a conceptual diagram of a conventional system.

[Explanation of symbols]

 BL, bar BL Bit line pair SA1, SA2 Sense amplifier T, T'NMOS transistor

Claims (1)

[Claims] 1. A bit line pair is provided with two sense amplifiers, and one sense amplifier is electrically connected to the bit line pair.
A semiconductor memory comprising switching means for controlling interruption.