JPH0660657A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce a chip size and cost by connecting a transistor which turns on or off with a write control signal between a transistor and a digit line in the read side. CONSTITUTION:When a write data is transmitted to data buses DB1, DB2 and a write control signal phiw is activated in the timing that the data inverted from that at the read time is transmitted the transistors T9, T10 turn on and data of the data buses DB1, DB2 can be transmitted to the digit lines DL2, DL1 through the transistors T5, T6, T9, T10. Data of the data buses DB1, DB2 are transmitted to the digit lines DL1, DL2. Next, the stand-by condition occurs, completing the read and write operations. Thereby, while the characteristic showing high operation rate and large degree of freedom of design of the conventional device, the number of lines of data buses can be reduced to 1/2 and the number of transistors can also be reduced to 3/4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device equipped with means for selecting and transferring data between digit lines and a data bus at high speed.

[0002]

2. Description of the Related Art In a semiconductor memory device, a random access memory (hereinafter referred to as DRA) which requires constant refreshing.
(Referred to as M), various functions have been added in addition to the increase in storage capacity accompanying the high integration. In particular, each digit line pair is associated with a complementary field effect transistor (CMOS) adopted from a 1-megabit DRAM and a static column mode and a first page mode in which a column, that is, a column side is realized as a static operation. Various improvements have been made to the type of amplifier circuit (sense amplifier) provided for each, and the selection and transfer circuit method for selecting cell data amplified by the amplifier circuit based on the column side address selection information.

A first example of a conventional semiconductor memory device is shown in FIG.

This semiconductor memory device includes a pair of first and second digit lines DL1 and DL2 and a word line WL.
And the data transmitted to the pair of first and second digit lines DL1 and DL2 selected by the word line WL and provided with the transistor Ts and the capacitive element Cs. 2 digit lines DL
1 and DL2, a memory cell MC for transmitting to the first and second digit lines DL1 and DL2 according to activation control signals Φp and Φn, a memory cell MC for transmitting to the first and second digit lines DL1, DL2, and a data input. The pair of first and second data buses DB1 and DB2 for outputting, the sources and drains thereof are connected to the digit lines DL1 and DL2 and the data buses DB1 and DB2, respectively, and the gate receives the column selection signal Φy. The transistors T11 and T12 for turning on and off by the digit lines DL1 and DL2.
The data selection transfer circuit 1a is configured to select and transfer data between the data buses DB1 and DB according to the column selection signal Φy.

This semiconductor memory device has a transistor T1.
Since the charges are directly exchanged between the digit lines DL1 and DL2 and the data buses DB1 and DB2 via T1 and T12, the data transfer speed is slow, and the multi-select countermeasure, the sense amplifier SA / digit line DL1, D
When a transfer gate is provided between L2, adjustment of transfer gate connection timing and activation timing of column selection signal Φy, adjustment of amplification degree between digit lines DL and DL2 and activation timing of column selection signal Φy, and writing Of the transfer switch transistor and the data buses DB1 and DB / digit line DL1 at the time of reading
There are various problems such as a trade-off with the ability of the transfer switch transistor to prevent data destruction due to exchange of charges between DL2.

FIG. 4 shows a second example of a conventional semiconductor memory device which solves these problems.

The difference between the second example and the first example is that
Read-only read data bus RDB
1, RDB2 and write-only write data bus WDB
1 and WDB2, and the data selection transfer circuit has one of the source and the drain read data buses RDB1 and RD.
Transistors T5 and T6 which are respectively connected to B2 and turn on / off by receiving the column selection signal Φy at their gates and their sources are connected to a reference potential point, and their gates are digit lines DL
A transistor T7 having a drain connected to 1 and a drain connected to the other of the source and the drain of the transistor T5; and a source connected to the reference potential point, a gate connected to the digit line DL2, and a drain connected to the other of the source and the drain of the transistor T6. Transistor T8, transistors T11 and T12 that connect one of sources and drains corresponding to digit lines DL1 and DL2, respectively, and turn on / off by receiving column selection signal Φy at the gates, and transistors T11 and T12 that have one of sources and drains Transistors T13 and T14 which are connected to the other of the source and the drain of the same and connected to the other of the source and the drain to the write data buses WDB1 and WDB2, respectively, and whose gates receive the write control signal Φw to turn on and off. The point is that it is configured with.

Next, the operation of this semiconductor memory device will be described. FIG. 5 is a waveform diagram of signals at various parts for explaining the operation of the semiconductor memory device.

At time t0, external row address strobe signal RAS attains an activation level, and in response thereto, word line WL designated by the row address signal.
Is the selection level. As a result, the transistor Ts of the memory cell MC connected to the word line WL at time t1
Is turned on and cell data is transmitted to the digit line DL1. The charge Qs = CsVs and the digit line charge Qd = CdVd accumulated in the capacitive element Cs of the memory cell MC.
The minute difference potential due to the capacitance division with and is amplified by the sense amplifier SA according to the activation signals Φp and Φn that are activated at time t2. By time t2, the external column address strobe signal CAS is activated, and the column address signal is fetched in synchronization with this. Next, at time t3, the column selection signal Φy is activated by the column address signal, and the transistors T5, T6, T11, and T12 are turned on. At this time, the digit lines DL1 and D1 connected to the sense amplifier SA that has started amplification at time t2
The level of L2 becomes a sufficient potential difference, and DL1 becomes high level (or low level) DL2 becomes low level (or high level). Therefore, the transistor T7 maintains the on (or off) state, and the transistor T8 maintains the off (or on) state. That is, at time t3, the transistors T5 and T
Even if both 6 are turned on, the transistors T5 and T7
Is connected to the sword data bus RDB1 which is pulled down to a low level, but the other transistors T6 and TDB
The read data bus RDB2 on the side to which 8 is connected maintains a high level, and the read data buses RDB1 and RDB2
The data is transmitted by.

Further, at time t4, the write data transmitted from the outside is the write data buses WDB1 and WD.
B2, and the write control signal Φw at time t5
Is activated, the transistors T13 and T14 are turned on, and the transistors T11 and T1 which are turned on by the column selection signal Φy already activated at the time t3.
Along with 2, the data of the write data buses WDB1 and WDB2 are transmitted to the digit lines DL1 and DL2. DL1,
It is the time when the writing of the reverse data to DL2 is completed, and at time t7, the read / write operation is completed, and all the internal states are
It shows the time to return to the deactivated standby state.

[0011]

The data selection transfer circuit 1b of the second example of the conventional semiconductor memory device can operate at a higher speed than the transfer switch type first example.
Moreover, as described above, it has the excellent characteristic that it has a large degree of freedom in design, but since the read side is a type that receives data at the gate, a separate write-only data bus and switch circuit must be provided for writing. Not
There is a drawback in that the device bus requires a double data bus and a quadruple number of transistors as compared with the first example, resulting in a large element area chip size and an increased cost.

An object of the present invention is to provide a semiconductor memory device which operates at high speed, has a large degree of freedom in design, and can reduce the cost by reducing the chip size.

[0013]

According to the present invention, a semiconductor memory device has a pair of first and second digit lines, a word line, and the first and second digit lines selected by the word line. Memory cells for storing the data transmitted to the first and second digit lines, and the first and second memory cells according to an activation control signal.
A sense amplifier for amplifying the data between the digit lines of
A pair of first and second data buses for inputting / outputting data and one of a source and a drain are connected to correspond to the first and second data buses respectively, and gates receive a column selection signal together. A first and a second transistor which are turned on and off, a source connected to a reference potential point, a gate connected to the first digit line, and a drain connected to the other of the source and the drain of the first transistor. A transistor and a source are connected to the reference potential point and a gate is connected to the second
A fourth transistor having a drain connected to the digit line and a drain connected to the other of the source and the drain of the second transistor, and a source and a drain connected to the other of the source and the drain of the first transistor. The other of the second transistor is connected to the second digit line and a gate receives a write control signal to turn on / off the fifth transistor, and one of the source and the drain is connected to the other of the source and the drain of the second transistor. The data selection transfer circuit includes a sixth transistor which connects the other of the source and the drain to the first digit line and has a gate which turns on and off in response to the write control signal.

[0014]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 4 in that read data buses RDB1,
The RDB2 and the write data buses WDB1 and WDB2 are integrated into a pair of data buses DB1 and DB2, and the data selection transfer circuit 1 has one of a source and a drain (first and second
Connected to the data buses DB1 and DB2 respectively, and connected to the gates to receive and turn on / off the column selection signal Φy (first and second) transistors T5 and T6, and the sources to the reference potential point. A (third) transistor T7 having a gate connected to the digit line DL1 and a drain connected to the other of the source and the drain of the transistor T5, and a source connected to the reference potential point to connect the gate to the digit line DL2 and a drain to the transistor A (fourth) transistor T8 connected to the other of the source and the drain of T6, and one of the source and the drain connected to the other of the source and the drain of the transistor T5 and the other of the source and the drain connected to the digit DL2 to write to the gate The control signal Φw is received to turn on / off the (fifth) transistor T9 and one of the source and the drain. The transistor T6 is connected to the other of the source and the drain, the other of the source and the drain is connected to the digit line DL1, and the gate receives the write control signal Φw to turn on and off (sixth) transistor T10. In point.

Next, the operation of this embodiment will be described.
FIG. 2 is a waveform diagram of signals at various parts for explaining the operation of this embodiment.

The data read operation is the same as that of the second conventional example shown in FIGS. 4 and 5, and therefore its explanation is omitted (up to before time t4 in FIG. 2).

Assuming that the write data is transmitted to the data buses DB1 and DB2 at time t4 and the reverse of the read data is transmitted, the transistors T9 and T10 are activated at the time when the write control signal Φw is activated at time t5.
Is turned on and the transistors T5, T6, T9, T
The data of the data bus DB1 is transferred to the digit line DL2 and the data of the data bus DB2 is transferred to the digit line D via
It becomes possible to transmit to L1. Then, at time t6, the data bus D
The data of B1 and DB2 are transmitted to the digit lines DL1 and DL2. Next, at time t7, the device returns to the standby state and the read / write operation is completed.

In this embodiment, the number of data buses is halved with respect to the second example while keeping the features of the high speed operation and the large degree of freedom of design in the second example. , And the number of transistors is reduced to 3/4.

[0021]

As described above, according to the present invention, the data bus is shared for writing and reading, and the data selection transfer circuit is
The read side is the same as the second conventional example, and the write side is connected between the first transistor on the read side and the second digit line and between the second transistor and the first digit line.
By connecting the fifth and sixth transistors that are turned on / off by the write control signal, the high speed operation and the high degree of freedom of design of the above-mentioned second conventional example are utilized, and Compared to the second example, the number of data buses can be reduced to 1/2 and the number of transistors can be reduced to 3/4, so that the chip size can be reduced.
There is an effect that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram of a first example of a conventional semiconductor memory device.

FIG. 4 is a circuit diagram of a second example of a conventional semiconductor memory device.

FIG. 5 is a waveform diagram of signals of respective parts for explaining the operation of the semiconductor memory device shown in FIG.

[Explanation of symbols]

 1, 1a, 1b Data selection transfer circuit DB1, DB2 Data bus DL1, DL2 Digit line MC Memory cell RDB1, RDB2 Read data bus SA Sense amplifier T1-T14 Transistor WDB1, WDB2 Write data bus WL Word line

Claims (1)

[Claims] 1. A pair of first and second digit lines, a word line, and data selected by the word line and transmitted to the first and second digit lines are stored and stored. A memory cell for transmitting data to the first and second digit lines, a sense amplifier for amplifying data between the first and second digit lines according to an activation control signal, and a pair for inputting and outputting data. The first and second data buses and one of the source and the drain are connected to the first data bus.
And a second data bus, which are respectively connected to the gates and receive the column selection signal at their gates to turn on and off.
And a source connected to the reference potential point, a gate connected to the first digit line, and a drain connected to the other of the source and the drain of the first transistor.
And a fourth transistor having a source connected to the reference potential point, a gate connected to the second digit line, and a drain connected to the other of the source and the drain of the second transistor. A fifth transistor which is connected to the other of the source and the drain of the first transistor, is connected to the other of the source and the drain to the second digit line, and is turned on and off by receiving a write control signal at the gate.
And one of a source and a drain of the second transistor is connected to the other of the source and the drain of the second transistor, the other of the source and the drain is connected to the first digit line, and the gate is turned on by receiving the write control signal, A semiconductor memory device, comprising: a data selection transfer circuit including a sixth transistor which is turned off.