JPH0661205A - Polishing method and polishing apparatus for semiconductor wafer - Google Patents

Polishing method and polishing apparatus for semiconductor wafer

Info

Publication number
JPH0661205A
JPH0661205A JP21432392A JP21432392A JPH0661205A JP H0661205 A JPH0661205 A JP H0661205A JP 21432392 A JP21432392 A JP 21432392A JP 21432392 A JP21432392 A JP 21432392A JP H0661205 A JPH0661205 A JP H0661205A
Authority
JP
Japan
Prior art keywords
polishing
wafer
jig
voltage
holding plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21432392A
Other languages
Japanese (ja)
Other versions
JP3276409B2 (en
Inventor
Sadahiro Kishii
貞浩 岸井
Hiroshi Horie
博 堀江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21432392A priority Critical patent/JP3276409B2/en
Publication of JPH0661205A publication Critical patent/JPH0661205A/en
Application granted granted Critical
Publication of JP3276409B2 publication Critical patent/JP3276409B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

(57)【要約】 【目的】 本発明は半導体ウェハの研磨方法、特にデバ
イス作製工程における配線層の平坦化や張り合わせSO
IウェハのSi層の薄膜化等に有用な研磨方法に関し、
ウェハ上の各位置における研磨量を制御することによ
り、配線層の平坦化方法として十分実用可能で、SOI
ウェハのSi層を更に薄膜化し得る、ウェハ全面の均一
な研磨を可能とした研磨方法およびその実施のための装
置を提供することを目的とする。 【構成】 半導体ウェハを保持板上に吸着保持し、研磨
治具に装着した研磨布を該ウェハの研磨対象面に接触さ
せ、研磨剤を該研磨布を透過させて該接触部に供給しな
がら該保持板と該研磨治具の少なくとも一方を回転させ
ることにより該ウェハを研磨する際に、該ウェハの吸着
部と該研磨治具との間に電圧を印加し、研磨中に両者間
の電圧および/または電流を検出し、得られた検出値に
基づいて各研磨位置での研磨速度を制御するように構成
する。
(57) [Abstract] [Purpose] The present invention is directed to a method for polishing a semiconductor wafer, and particularly to planarization and bonding SO of a wiring layer in a device manufacturing process
A polishing method useful for thinning the Si layer of an I wafer,
By controlling the polishing amount at each position on the wafer, it can be sufficiently practically used as a method for planarizing the wiring layer.
An object of the present invention is to provide a polishing method capable of further thinning the Si layer of a wafer and enabling uniform polishing of the entire surface of the wafer, and an apparatus for carrying out the method. [Structure] A semiconductor wafer is suction-held on a holding plate, a polishing cloth attached to a polishing jig is brought into contact with a surface to be polished of the wafer, and an abrasive is passed through the polishing cloth and supplied to the contact portion. At the time of polishing the wafer by rotating at least one of the holding plate and the polishing jig, a voltage is applied between the suction portion of the wafer and the polishing jig, and the voltage between the two is applied during polishing. And / or the current is detected, and the polishing rate at each polishing position is controlled based on the obtained detection value.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体ウェハの研磨方法
に関し、特にデバイス作製工程における配線層の平坦化
や張り合わせSOIウェハのSi層の薄膜化等に有用な
研磨方法に関する。半導体装置の集積度の増大に伴い、
配線の多層化が進み、それによって配線層の凹凸も増大
して断線の危険性が高くなる。その防止策として配線層
の平坦化が益々重要になる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer polishing method, and more particularly to a polishing method useful for flattening a wiring layer in a device manufacturing process and thinning a Si layer of a bonded SOI wafer. With the increase in the degree of integration of semiconductor devices,
As the number of wiring layers increases, the unevenness of the wiring layer also increases and the risk of disconnection increases. As a preventive measure, planarization of the wiring layer becomes more important.

【0002】デバイスの諸機能を増大させる上で非常に
有用なSOIウェハは、少なくとも一枚は酸化したウェ
ハを2枚張り合わせたもので、片側のSi層を研磨して
薄膜化しデバイス形成層として用いる。
A very useful SOI wafer for increasing various functions of a device is at least one oxidized wafer which is bonded to one another, and a Si layer on one side is polished and thinned to be used as a device forming layer. .

【0003】[0003]

【従来の技術】一般に市販されている半導体デバイス
は、配線層の平坦化に研磨は用いられていない。現在の
デバイスでは研磨を用いなくとも配線が可能なのであ
る。しかし近い将来、配線層の平坦化に研磨が必要にな
ることが十分予想される。そのために例えば W.J.Patri
ckらは研磨による平坦化を積極的に検討し、実際のデバ
イスの試作にも成功している(Journal Electrochem. S
oc., Vol.138, No.6, p1778-1784, Jun.,1991)。この方
法では、図1に示すように、基板10上に横方向導電部
(horizontal interconnection) 11を形成した後、そ
の上に縦方向導電部(studまたはvertical interconnec
tion) 12を形成する。次にCVDによりSiO2 絶縁
層13を形成する。絶縁層13は先に形成した横・縦の
導電部11および12の配置に応じた凹凸のあるプロフ
ァイルを有する。この絶縁層13を研磨して図中の破線
14の位置まで削除し、縦方向導電部12の上部が露出
したところで平坦化(研磨)を終了する。この研磨には
図2に示すような枚葉式の研磨装置を用いる。回転軸2
1により回転する定盤22の上面に研磨布23を装着す
る。回転軸24により回転するウェハ保持板25の下面
にウェハ26を吸着により保持し、研磨対象面であるウ
ェハ26下面を研磨布23に接触させ、上方より研磨布
23上に研磨剤を供給しながら、定盤22およびウェハ
保持板25を回転させて研磨を行う。
2. Description of the Related Art Generally, semiconductor devices on the market do not use polishing for planarizing a wiring layer. Current devices allow wiring without polishing. However, it is fully expected that polishing will be required to planarize the wiring layer in the near future. For that purpose, for example WJPatri
ck et al. have positively considered flattening by polishing and succeeded in trial production of actual devices (Journal Electrochem. S
oc., Vol.138, No.6, p1778-1784, Jun., 1991). In this method, as shown in FIG. 1, a horizontal conductive portion 11 is formed on a substrate 10 and then a vertical conductive portion (stud or vertical interconnec) is formed thereon.
tion) 12 is formed. Next, the SiO 2 insulating layer 13 is formed by CVD. The insulating layer 13 has a profile having irregularities according to the arrangement of the horizontal and vertical conductive portions 11 and 12 formed previously. The insulating layer 13 is polished and deleted up to the position of the broken line 14 in the figure, and the planarization (polishing) is completed when the upper portion of the vertical conductive portion 12 is exposed. For this polishing, a single-wafer polishing apparatus as shown in FIG. 2 is used. Rotating shaft 2
The polishing cloth 23 is attached to the upper surface of the surface plate 22 which rotates by 1. The wafer 26 is held by suction on the lower surface of the wafer holding plate 25 rotated by the rotating shaft 24, the lower surface of the wafer 26, which is the surface to be polished, is brought into contact with the polishing cloth 23, and an abrasive is supplied onto the polishing cloth 23 from above. The surface plate 22 and the wafer holding plate 25 are rotated to perform polishing.

【0004】上記の方法の最大の欠点は、ウェハの研磨
対象面全体について縦方向導電部12が露出した時点で
研磨を終了させることが実際上不可能なことである。す
なわち、ウェハの研磨対象面内の一部の領域を平坦化す
ることはできるが、高い研磨歩留りを得ることができな
い。そのため上記の方法は実用化されるには到っていな
い。
The greatest drawback of the above method is that it is practically impossible to finish the polishing when the longitudinal conductive portion 12 is exposed on the entire surface to be polished of the wafer. That is, although it is possible to flatten a part of the region within the surface to be polished of the wafer, a high polishing yield cannot be obtained. Therefore, the above method has not been put to practical use.

【0005】一方、張り合わせSOIウェハのSi層の
薄膜化は、図3に示す手順で行われる。例えば同図
(a)に示すように、Siウェハ31の表面に熱酸化に
より酸化膜33を形成したものと、酸化膜の無いSiウ
ェハ32とを準備し、同図(b)に示すようにこれら2
枚のウェハ31と32とを密着させて重ね合わせ、例え
ば窒素雰囲気中、900℃、30分の熱処理を行って接
着する。次に酸化膜33のあるウェハ31側を、同図
(c)に示すように厚さ3μm程度になるまで研削した
後、同図(d)に示すように更に厚さ2μm程度まで研
磨する。この研磨は通常、やはり図2に示すような枚葉
式の研磨装置を用いて行っており、研磨量は研磨時間で
制御している。しかし、ウェハ面内の位置によって研磨
量にばらつきが生ずることが避けられないため、高い歩
留りが得られない上、Si層の薄膜化に限界があるとい
う問題があった。
On the other hand, thinning of the Si layer of the bonded SOI wafer is performed by the procedure shown in FIG. For example, as shown in FIG. 3A, a Si wafer 31 having a surface on which an oxide film 33 is formed by thermal oxidation and a Si wafer 32 having no oxide film are prepared, and as shown in FIG. These two
The wafers 31 and 32 are superposed in close contact with each other, and heat-treated at 900 ° C. for 30 minutes in a nitrogen atmosphere for adhesion. Next, the side of the wafer 31 having the oxide film 33 is ground to a thickness of about 3 μm as shown in FIG. 4C, and then further polished to a thickness of about 2 μm as shown in FIG. This polishing is usually performed using a single-wafer polishing apparatus as shown in FIG. 2, and the polishing amount is controlled by the polishing time. However, since it is unavoidable that the polishing amount varies depending on the position on the wafer surface, there is a problem that a high yield cannot be obtained and there is a limit in thinning the Si layer.

【0006】[0006]

【発明が解決しようとする課題】本発明は、ウェハ上の
各位置における研磨量を制御することにより、配線層の
平坦化方法として十分実用可能で、SOIウェハのSi
層を更に薄膜化し得る、ウェハ全面の均一な研磨を可能
とした研磨方法およびその実施のための装置を提供する
ことを目的とする。
The present invention is sufficiently practical as a method of flattening a wiring layer by controlling the polishing amount at each position on the wafer, and the Si of an SOI wafer can be achieved.
An object of the present invention is to provide a polishing method capable of further thinning a layer and enabling uniform polishing of the entire surface of a wafer, and an apparatus for carrying out the method.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の研磨方法は、半導体ウェハを保持板上に
吸着保持し、研磨治具に装着した研磨布を該ウェハの研
磨対象面に接触させ、研磨剤を該研磨布を透過させて該
接触部に供給しながら該保持板と該研磨治具の少なくと
も一方を回転させることにより該ウェハを研磨する際
に、該ウェハの吸着部と該研磨治具との間に電圧を印加
し、研磨中に両者間の電圧および/または電流を検出
し、得られた検出値に基づいて各研磨位置での研磨速度
を制御することを特徴とする。
In order to achieve the above object, the polishing method of the present invention uses a polishing cloth attached to a polishing jig by sucking and holding a semiconductor wafer on a holding plate and polishing the wafer. When polishing the wafer by rotating at least one of the holding plate and the polishing jig while bringing the polishing agent into contact with the surface and supplying the polishing agent to the contact portion through the polishing cloth, suction of the wafer A voltage is applied between the polishing part and the polishing jig to detect the voltage and / or current between them during polishing, and control the polishing rate at each polishing position based on the detected value obtained. Characterize.

【0008】本発明の研磨方法を実施するための研磨装
置は、半導体ウェハを吸着保持する保持板と、先端に装
着した研磨布を該ウェハの研磨対象面に接触させるよう
に配置した研磨治具と、該研磨布を透過させて該接触部
に研磨剤を供給する手段と、該ウェハの吸着部と該研磨
治具との間に電圧を印加する手段と、研磨中に両者間の
電圧および/または電流を検出する手段と、得られた検
出値に応じて研磨速度を制御する手段とを有し、該保持
板と該研磨治具の少なくとも一方が回転し得ることを特
徴とする。
A polishing apparatus for carrying out the polishing method of the present invention comprises a holding plate for sucking and holding a semiconductor wafer, and a polishing jig arranged so that a polishing cloth attached to the tip of the wafer is brought into contact with the surface to be polished of the wafer. A means for supplying a polishing agent to the contact portion through the polishing cloth, a means for applying a voltage between the suction portion of the wafer and the polishing jig, and a voltage between the two during polishing. And / or a means for detecting an electric current and a means for controlling a polishing rate according to the obtained detection value, and at least one of the holding plate and the polishing jig can rotate.

【0009】[0009]

【作用】本発明によれば、ウェハの保持板吸着部と研磨
治具との間に電圧を印加し、研磨中に両者間の電圧およ
び/または電流を検出し、得られた検出値に基づいて各
研磨位置での研磨速度を制御することにより、ウェハ全
面を高度に均一研磨することができる。
According to the present invention, a voltage is applied between the holding plate attracting portion of the wafer and the polishing jig, the voltage and / or current between the two is detected during polishing, and based on the detected value obtained. By controlling the polishing rate at each polishing position, the entire surface of the wafer can be highly uniformly polished.

【0010】以下に、添付図面を参照し、実施例によっ
て本発明を更に詳細に説明する。
Hereinafter, the present invention will be described in more detail by way of examples with reference to the accompanying drawings.

【0011】[0011]

【実施例】〔実施例1〕図4を参照し、本発明に従って
デバイス作製工程中の配線層の平坦化を行う一例を説明
する。この例では、ウェハ面上の層間絶縁膜を研磨する
際に、各研磨位置で層間絶縁膜の厚さを実測しながら研
磨することにより、ウェハ全面について均一な所望の層
間絶縁膜を得る。
EXAMPLE 1 An example of flattening a wiring layer during a device manufacturing process according to the present invention will be described with reference to FIG. In this example, when the interlayer insulating film on the wafer surface is polished, polishing is performed while actually measuring the thickness of the interlayer insulating film at each polishing position, thereby obtaining a uniform desired interlayer insulating film over the entire surface of the wafer.

【0012】ウェハ401には、一方の全面に例えば横
方向導通部(インタコネクト)および縦方向導通部(ス
タッド)のような導電部402を形成した後、層間絶縁
膜403を形成してある。またウェハ401の側面およ
び下面は全体が熱酸化膜等の絶縁膜404で覆われてい
る。研磨装置のウェハ保持板411は金属等の導電材料
で作られており、同様の導電材料で作られている回転軸
412によって回転する。ウェハ401をウェハ保持板
411上に吸着保持する。この吸着は、真空吸着、吸着
パッド、ワックス、接着剤等の通常の方法により行う。
真空吸着を行う場合には、回転軸412内からウェハ保
持板411内を通ってウェハ保持板411の吸着面に開
口する真空排気用の通気路が用いられる。通常この吸着
用開口を多数設け、ウェハを全面で強固に保持できるよ
うにする。
On the entire surface of the wafer 401, a conductive portion 402 such as a horizontal conductive portion (interconnect) and a vertical conductive portion (stud) is formed, and then an interlayer insulating film 403 is formed. The side surface and the lower surface of the wafer 401 are entirely covered with an insulating film 404 such as a thermal oxide film. The wafer holding plate 411 of the polishing apparatus is made of a conductive material such as metal, and is rotated by a rotary shaft 412 made of a similar conductive material. The wafer 401 is sucked and held on the wafer holding plate 411. This suction is performed by a usual method such as vacuum suction, a suction pad, wax, and an adhesive.
When vacuum suction is performed, a ventilation passage for vacuum evacuation is used, which passes through the inside of the rotation shaft 412 and the inside of the wafer holding plate 411 and opens to the suction surface of the wafer holding plate 411. Usually, a large number of suction openings are provided so that the wafer can be firmly held on the entire surface.

【0013】研磨装置の回転式研磨治具421は金属等
の導電材料で作られた円柱状の部材であり、その下部端
面422に研磨布431を装着し、上部から導入された
研磨剤を内部の貫通孔(図示せず)を通して研磨布43
1に供給するようになっている。研磨剤としては、コロ
イダルシリカ等の微細な研磨砥粒を溶液中に分散させた
ものが一般的に用いられる。研磨布431は研磨砥粒が
自由に透過し得る多数の貫通路432を含んでいる。研
磨剤は電解質の添加によりその比抵抗値を必要な水準に
まで小さくすることができる。研磨治具421は、ウェ
ハ保持板411上のウェハ401の半径方向に移動し
て、ウェハ401の任意の半径位置を研磨できるように
なっている。
The rotary polishing jig 421 of the polishing apparatus is a cylindrical member made of a conductive material such as metal. A polishing cloth 431 is attached to a lower end surface 422 of the polishing tool 421 and the polishing agent introduced from the upper portion is internally supplied. Polishing cloth 43 through a through hole (not shown)
It is designed to supply one. As the polishing agent, one in which fine polishing abrasive grains such as colloidal silica are dispersed in a solution is generally used. The polishing cloth 431 includes a large number of through passages 432 through which polishing grains can freely pass. The specific resistance of the abrasive can be reduced to a required level by adding an electrolyte. The polishing jig 421 can move in the radial direction of the wafer 401 on the wafer holding plate 411 to polish an arbitrary radial position of the wafer 401.

【0014】ウェハ401は、下面の一部で絶縁膜40
4を除去し、この部分に導体ペースト等の導電物質40
5を配置して、ウェハ保持板411との間で電気的に導
通をとった状態で保持されている。ウェハ保持板411
と研磨治具412との間には直流電圧441が印加され
ており、ウェハ401上の各位置で層間絶縁膜403の
厚さに対応する電流値を電流計442により研磨中に連
続的に検出する。
The wafer 401 has an insulating film 40 on a part of the lower surface.
4 is removed, and a conductive material 40 such as a conductor paste is applied to this portion.
5 is arranged and held in a state of being electrically connected to the wafer holding plate 411. Wafer holding plate 411
A DC voltage 441 is applied between the polishing jig 412 and the polishing jig 412, and the current value corresponding to the thickness of the interlayer insulating film 403 at each position on the wafer 401 is continuously detected by the ammeter 442 during polishing. To do.

【0015】研磨は例えば下記のように行う。ウェハ4
01をウェハ保持板411に吸着して保持し、ウェハ保
持板411を回転させながら1〜4cm2 の面積を持つ
研磨布431をウェハ401に押し付ける。研磨剤を研
磨治具421を介して研磨布431に供給する。研磨治
具421と研磨板411との間に直流電圧を印加する。
研磨剤に適当な電解質を添加することにより、印加電圧
のほとんどが層間絶縁膜403に印加されるようにする
ことができる。
Polishing is performed as follows, for example. Wafer 4
01 is adsorbed and held on the wafer holding plate 411, and the polishing cloth 431 having an area of 1 to 4 cm 2 is pressed against the wafer 401 while rotating the wafer holding plate 411. The polishing agent is supplied to the polishing cloth 431 via the polishing jig 421. A DC voltage is applied between the polishing jig 421 and the polishing plate 411.
By adding an appropriate electrolyte to the polishing agent, most of the applied voltage can be applied to the interlayer insulating film 403.

【0016】層間絶縁膜403の研磨が進行して導電部
402が露出すると、研磨剤と導電部402とが電気的
に導通して電流が流れ、これが電流計442によって検
出される。この時に研磨を一時停止し、研磨治具421
をウェハ401の半径方向外側に移動させてから研磨を
再開する。ウェハ401の同一半径上では、回転するウ
ェハ401と研磨布431との相対速度がほぼ一定にな
り、研磨速度の分布も非常に小さい。このようにして研
磨治具421をウェハ401の中心付近から次第に外側
に移動させてウェハ401の全体を研磨する。研磨布4
31を介してウェハ401上に供給された研磨剤は、ウ
ェハ401の回転による遠心力により研磨位置からウェ
ハ401の外側へ向かって流れる。したがって、研磨位
置をウェハの内側から外側に移動させることにより、研
磨剤がウェハ401の研磨完了部分に供給されることが
防止できる。研磨剤が研磨完了部に供給されると、そこ
に露出されている導電部402を介して電流が流れてし
まい、現に進行中の研磨を制御することが困難になる。
When the polishing of the interlayer insulating film 403 progresses and the conductive portion 402 is exposed, the polishing agent and the conductive portion 402 are electrically connected to each other and a current flows, which is detected by the ammeter 442. At this time, polishing is temporarily stopped and the polishing jig 421
Are moved to the outside of the wafer 401 in the radial direction, and then polishing is restarted. On the same radius of the wafer 401, the relative speed between the rotating wafer 401 and the polishing cloth 431 is substantially constant, and the distribution of the polishing speed is very small. In this way, the polishing jig 421 is gradually moved outward from the vicinity of the center of the wafer 401 to polish the entire wafer 401. Polishing cloth 4
The polishing agent supplied onto the wafer 401 via 31 flows toward the outside of the wafer 401 from the polishing position due to the centrifugal force generated by the rotation of the wafer 401. Therefore, by moving the polishing position from the inside to the outside of the wafer, it is possible to prevent the polishing agent from being supplied to the polishing completed portion of the wafer 401. When the polishing agent is supplied to the polishing-completed portion, a current flows through the conductive portion 402 exposed there, which makes it difficult to control the polishing currently in progress.

【0017】なおウェハ401を回転させず研磨治具4
21のみを回転させて研磨を行う場合には、図5に示す
ようにウェハ401の中心部分上方に配置した流体供給
口461から純水等の流体462を供給し、ウェハ40
1面上を外側へ向かう流れ463を形成することによ
り、研磨完了部分への研磨剤供給を防止することができ
る。このための流体462としては、ウェハおよび研磨
装置を汚染しない液体および気体を用いる。
The polishing jig 4 is used without rotating the wafer 401.
When only 21 is rotated for polishing, as shown in FIG. 5, a fluid 462 such as pure water is supplied from a fluid supply port 461 arranged above the central portion of the wafer 401, and the wafer 40
By forming the flow 463 outward on one surface, it is possible to prevent the supply of the polishing agent to the polishing-completed portion. As the fluid 462 for this purpose, liquid and gas that do not contaminate the wafer and the polishing apparatus are used.

【0018】研磨が行われるためには、研磨板および研
磨治具の少なくとも一方を回転させればよいが、両者を
回転させるとウェハ全面について均一に研磨を行うのに
最も有利である。特に研磨治具を回転させることは、研
磨布面積内での研磨速度を均一化し、またウェハ上同一
半径位置での研磨量の制御を容易にする。また、研磨板
を回転させ研磨治具は停止させて研磨を行う場合には、
図6に示すように、研磨治具の研磨布装着面422の幅
Wを、ウェハ半径方向に対して内側(W1)よりも外側
(W2)を小さくすることが望ましい。これにより、研
磨布面積内での研磨板回転周速度の差による研磨速度差
を軽減でき、すなわち研磨布の面積内での研磨速度をよ
り均一にすることができる。
In order to perform the polishing, at least one of the polishing plate and the polishing jig may be rotated, but the rotation of both is most advantageous for uniformly polishing the entire surface of the wafer. In particular, rotating the polishing jig makes the polishing rate uniform within the polishing cloth area and facilitates the control of the polishing amount at the same radial position on the wafer. Also, when polishing is performed by rotating the polishing plate and stopping the polishing jig,
As shown in FIG. 6, it is desirable that the width W of the polishing cloth mounting surface 422 of the polishing jig be smaller on the outer side (W2) than on the inner side (W1) in the wafer radial direction. As a result, it is possible to reduce the difference in the polishing rate due to the difference in the peripheral speed of the polishing plate within the area of the polishing cloth, that is, to make the polishing rate within the area of the polishing cloth more uniform.

【0019】各研磨位置で検出された電流値の大小に応
じて研磨速度を増減することにより、ウェハ全面を均一
に研磨することができる。すなわち検出電流値が小さい
(大きい)領域では、(1)研磨圧力の増大(減少)、
(2)研磨治具の回転速度の増大(減少)および/また
は(3)ウェハ保持板の回転速度の増大(減少)によ
り、研磨速度を増大(減少)させることができる。
By increasing or decreasing the polishing rate according to the magnitude of the current value detected at each polishing position, the entire surface of the wafer can be uniformly polished. That is, in the region where the detected current value is small (large), (1) the polishing pressure increases (decreases),
The polishing speed can be increased (decreased) by (2) increasing (decreasing) the rotating speed of the polishing jig and / or (3) increasing (decreasing) the rotating speed of the wafer holding plate.

【0020】図5に示す方法で本発明により層間絶縁膜
の平坦化を行い、図2に示す従来の枚葉式研磨装置によ
る平坦化と比較した。
The interlayer insulating film was planarized by the method of the present invention by the method shown in FIG. 5 and compared with the planarization by the conventional single-wafer polishing apparatus shown in FIG.

【0021】<供試ウェハの準備>直径150mmのS
iウェハ601上に、直径2μm、高さ0.5μmのW
(タングステン)スタッド(縦方向導通部)602を1
0mm間隔で形成し、図7に示すスタッドパターンを形
成した。その上に、CVD−SiO2 を1μm堆積させ
た。
<Preparation of test wafer> S with a diameter of 150 mm
W with a diameter of 2 μm and a height of 0.5 μm on the i-wafer 601
(Tungsten) Stud (vertical conduction part) 602 1
The stud pattern shown in FIG. 7 was formed by forming the stud pattern at intervals of 0 mm. CVD-SiO 2 was deposited thereon to a thickness of 1 μm.

【0022】<研磨条件> 本発明による研磨 ウェハの中心から研磨を開始し、ウェハ保持板と研磨治
具との間に直流電圧を印加しておき、両者間の電流値が
所定値を超えた所で研磨を一時停止し、研磨治具をウェ
ハ半径方向外側に移動させて研磨を再開する。研磨中、
ウェハ中心部に純水を供給し、ウェハ研磨面上に中心か
ら外側へ向かう水流を形成しておく。 従来法による研磨 図2の研磨装置により単に研磨時間で研磨量を調節す
る。
<Polishing Conditions> Polishing according to the present invention: Polishing is started from the center of the wafer, a DC voltage is applied between the wafer holding plate and the polishing jig, and the current value between the two exceeds a predetermined value. The polishing is temporarily stopped at this point, the polishing jig is moved to the outer side in the radial direction of the wafer, and the polishing is restarted. During polishing,
Pure water is supplied to the center of the wafer to form a water flow from the center to the outside on the wafer polishing surface. Conventional Polishing The polishing apparatus shown in FIG. 2 simply adjusts the polishing amount by polishing time.

【0023】<研磨結果の評価>上記ウェハ10枚ずつ
を上記各研磨条件で研磨し、周辺部15mm以内(図7
中に603で表示した領域)にあるスタッド上のCVD
−SiO2 が全て除去された後、除去されていないスタ
ッドの個数を数えた。その結果を図8に示す。本発明に
より研磨した場合はスタッドはほぼ100%残っている
のに対し、従来法による研磨ではスタッドの70%が研
磨により除去されてしまっている。
<Evaluation of Polishing Result> Each of the above 10 wafers was polished under the above polishing conditions, and the peripheral portion was within 15 mm (see FIG. 7).
CVD on stud in area 603)
After -SiO 2 is entirely removed, it counted the number of studs that are not removed. The result is shown in FIG. Almost 100% of the studs remain when polished by the present invention, whereas 70% of the studs are removed by polishing by the conventional method.

【0024】このように本発明によれば、ウェハ全面に
ついて層間絶縁膜を極めて均一に研磨することができ
る。なお、本実施例では電流値により研磨の制御を行う
例を示したが、電位差を用いても同様の制御を行うこと
ができる。
As described above, according to the present invention, the interlayer insulating film can be polished extremely uniformly over the entire surface of the wafer. In this embodiment, an example in which the polishing is controlled by the current value is shown, but the same control can be performed by using the potential difference.

【0025】〔実施例2〕図9を参照し、本発明に従っ
て張り合わせSOIウェハのSi層を薄膜化する一例を
説明する。この例では、ウェハ面上のSi層を研磨する
際に、各研磨位置でSi層の厚さを実測しながら研磨す
ることにより、ウェハ全面について均一な所望の薄膜S
i層を得る。
[Embodiment 2] An example of thinning the Si layer of a bonded SOI wafer according to the present invention will be described with reference to FIG. In this example, when the Si layer on the wafer surface is polished, polishing is performed while actually measuring the thickness of the Si layer at each polishing position, so that the desired thin film S that is uniform over the entire wafer surface is obtained.
Get the i-layer.

【0026】張り合わせSOIウェハ501は、図3を
参照して既に説明した手順により同図(c)の研削まで
を行って準備したものである。図9中で図3と同一の対
象物は同一の参照番号で示してある。すなわち、SOI
ウェハ501は、3μm程度にまで研削されたSi層3
1と、支持側ウェハ32と、これら両者の間に介在する
絶縁膜33とから実質的になる構造を有する。
The bonded SOI wafer 501 is prepared by performing the steps up to the grinding shown in FIG. 3C by the procedure already described with reference to FIG. In FIG. 9, the same objects as those in FIG. 3 are designated by the same reference numerals. That is, SOI
Wafer 501 has Si layer 3 ground to about 3 μm
1, the support-side wafer 32, and the insulating film 33 interposed therebetween, and the structure is substantially formed.

【0027】実施例1と同様の研磨装置および研磨剤を
用いて研磨を行う。但し、ウェハ保持板411とと研磨
治具421との間に、交流電圧541を印加し、交流電
流計542により電流を検出する。SOIウェハ501
は、ウェハ保持板411との間で電気的に導通した状態
で保持されている。研磨は例えば下記のように行う。
Polishing is performed using the same polishing apparatus and polishing agent as in Example 1. However, an AC voltage 541 is applied between the wafer holding plate 411 and the polishing jig 421, and the current is detected by the AC ammeter 542. SOI wafer 501
Are held in a state of being electrically connected to the wafer holding plate 411. Polishing is performed as follows, for example.

【0028】SOIウェハ501をウェハ保持板411
に吸着して保持し、ウェハ保持板411を回転させなが
ら1〜4cm2 の面積を持つ研磨布431をウェハ50
1に押し付ける。研磨剤を研磨治具421を介して研磨
布431に供給する。研磨治具421と研磨板411と
の間に交流電圧541を印加する。研磨剤に適当な電解
質を添加することにより、印加電圧のほとんどがSi層
31および支持側ウェハ32に印加されるようにするこ
とができる。支持側ウェハ32のSiの抵抗値を小さく
しておくと実質的な電圧は研磨対象であるSi層31に
印加される。
The SOI wafer 501 is attached to the wafer holding plate 411.
The wafer holding plate 411 is rotated, and the polishing cloth 431 having an area of 1 to 4 cm 2 is held by the wafer 50.
Press on 1. The polishing agent is supplied to the polishing cloth 431 via the polishing jig 421. An alternating voltage 541 is applied between the polishing jig 421 and the polishing plate 411. By adding a suitable electrolyte to the polishing agent, most of the applied voltage can be applied to the Si layer 31 and the supporting-side wafer 32. If the resistance value of Si of the supporting side wafer 32 is made small, a substantial voltage is applied to the Si layer 31 to be polished.

【0029】Si層31の研磨が進行して薄くなると、
Si層31による抵抗値が減少して電流値は増大する。
所望のSi層厚さに対応する参照電流値を予め実験によ
り求めておく。研磨中に電流値がこの参照値になったら
研磨を一時停止し、研磨治具421をウェハ401の半
径方向外側に移動させてから研磨を再開する。ウェハ5
01の同一半径上では、回転するウェハ501と研磨布
431との相対速度がほぼ一定になり、研磨速度の分布
も非常に小さい。このようにして研磨治具421をウェ
ハ501の中心付近から次第に外側に移動させてウェハ
501の全体を研磨する。研磨布431を介してウェハ
501上に供給された研磨剤は、ウェハ501の回転に
よる遠心力により研磨位置からウェハ501の外側へ向
かって流れる。したがって、研磨位置をウェハの内側か
ら外側に移動させることにより、研磨剤がウェハ501
の研磨完了部分に供給されることが防止できる。研磨剤
が研磨完了部に供給されると、そこに露出されている導
電部402を介して電流が流れてしまい、現に進行中の
研磨を制御することが困難になる。
As the polishing of the Si layer 31 progresses and becomes thinner,
The resistance value due to the Si layer 31 decreases and the current value increases.
A reference current value corresponding to a desired Si layer thickness is previously obtained by an experiment. When the current value reaches this reference value during polishing, the polishing is temporarily stopped, the polishing jig 421 is moved to the outer side in the radial direction of the wafer 401, and then the polishing is restarted. Wafer 5
On the same radius of 01, the relative speed between the rotating wafer 501 and the polishing cloth 431 is substantially constant, and the distribution of the polishing speed is very small. In this way, the polishing jig 421 is gradually moved outward from the vicinity of the center of the wafer 501 to polish the entire wafer 501. The polishing agent supplied onto the wafer 501 via the polishing cloth 431 flows from the polishing position toward the outside of the wafer 501 due to the centrifugal force generated by the rotation of the wafer 501. Therefore, by moving the polishing position from the inside of the wafer to the outside, the polishing agent is removed from the wafer 501.
Can be prevented from being supplied to the polishing-completed portion. When the polishing agent is supplied to the polishing-completed portion, a current flows through the conductive portion 402 exposed there, which makes it difficult to control the polishing currently in progress.

【0030】なおウェハ501を回転させず研磨治具4
21のみを回転させて研磨を行う場合には、図5に示す
ようにウェハ501の中心部分に例えば純水等の流体を
供給し、ウェハ501面上を外側へ向かう流れを形成す
ることにより、研磨完了部分への研磨剤供給を防止する
ことができる。このための流体としては、ウェハおよび
研磨装置を汚染しない液体および気体を用いる。
The wafer 501 is not rotated and the polishing jig 4 is used.
When only 21 is rotated to perform polishing, a fluid such as pure water is supplied to the central portion of the wafer 501 as shown in FIG. 5 to form a flow outward on the surface of the wafer 501. It is possible to prevent the polishing agent from being supplied to the polishing-completed portion. Liquids and gases that do not contaminate the wafer and the polishing apparatus are used as the fluid for this purpose.

【0031】研磨が行われるためには、研磨板および研
磨治具の少なくとも一方を回転させればよいが、両者を
回転させるとウェハ全面について均一に研磨を行うのに
最も有利である。特に研磨治具を回転させることは、研
磨布面積内での研磨速度を均一化し、またウェハ上同一
半径位置での研磨量の制御を容易にする。また、研磨板
を回転させ研磨治具は停止させて研磨を行う場合には、
図6に示すように、研磨治具の研磨布装着面422の幅
Wを、ウェハ半径方向に対して内側(W1)よりも外側
(W2)を小さくすることが望ましい。これにより、研
磨布面積内での研磨板回転周速度の差による研磨速度差
を軽減でき、すなわち研磨布の面積内での研磨速度をよ
り均一にすることができる。
In order to perform the polishing, at least one of the polishing plate and the polishing jig may be rotated, but rotating both is most advantageous for uniformly polishing the entire surface of the wafer. In particular, rotating the polishing jig makes the polishing rate uniform within the polishing cloth area and facilitates the control of the polishing amount at the same radial position on the wafer. Also, when polishing is performed by rotating the polishing plate and stopping the polishing jig,
As shown in FIG. 6, it is desirable that the width W of the polishing cloth mounting surface 422 of the polishing jig be smaller on the outer side (W2) than on the inner side (W1) in the wafer radial direction. As a result, it is possible to reduce the difference in the polishing rate due to the difference in the peripheral speed of the polishing plate within the area of the polishing cloth, that is, to make the polishing rate within the area of the polishing cloth more uniform.

【0032】図9に示す方法で本発明により張り合わせ
SOIウェハのSi層の薄膜化を行い、図2に示す従来
の枚葉式研磨装置による薄膜化と比較した。
The Si layer of the bonded SOI wafer was thinned according to the present invention by the method shown in FIG. 9 and compared with the thinning by the conventional single-wafer polishing apparatus shown in FIG.

【0033】<供試ウェハの準備>直径150mmのS
iウェハに図3(c)の研削までを行って、Si層の厚
さ3μmのSOIウェハを準備した。
<Preparation of test wafer> S with a diameter of 150 mm
The i wafer was subjected to the grinding shown in FIG. 3C to prepare an SOI wafer having a Si layer thickness of 3 μm.

【0034】<研磨条件> 本発明による研磨 ウェハの中心から研磨を開始し、ウェハ保持板と研磨治
具との間に交流電圧を印加しておき、両者間の電流値が
所定値を超えた所で研磨を一時停止し、研磨治具をウェ
ハ半径方向外側に移動させて研磨を再開する。研磨中、
ウェハ中心部に純水を供給し、ウェハ研磨面上に中心か
ら外側へ向かう水流を形成しておく。 従来法による研磨 図2の研磨装置により単に研磨時間で研磨量を調節す
る。
<Polishing Conditions> Polishing according to the present invention: Polishing is started from the center of the wafer, an AC voltage is applied between the wafer holding plate and the polishing jig, and the current value between the two exceeds a predetermined value. The polishing is temporarily stopped at this point, the polishing jig is moved to the outer side in the radial direction of the wafer, and the polishing is restarted. During polishing,
Pure water is supplied to the center of the wafer to form a water flow from the center to the outside on the wafer polishing surface. Conventional Polishing The polishing apparatus shown in FIG. 2 simply adjusts the polishing amount by polishing time.

【0035】<研磨結果の評価>Si層厚さ1μmを目
標にして、上記ウェハ10枚ずつを上記各研磨条件で研
磨し、研磨後のウェハ中心部1点と周辺部4点のSi層
厚さを測定した。その結果を図10に示す。本発明によ
り研磨した場合はSi層の平均厚さが0.95μm、厚
さのばらつきが平均0.05μmであるのに対し、従来
法による研磨ではSi層の平均厚さが1.10μm、厚
さばらつきが平均0.5μmであった。このように、本
発明によれば従来法に比べて均一に且つより薄膜化が可
能である。
<Evaluation of Polishing Results> Aiming at a Si layer thickness of 1 μm, 10 wafers each were polished under each of the polishing conditions described above, and the Si layer thickness after polishing at one point in the central portion of the wafer and four points in the peripheral portion Was measured. The result is shown in FIG. In the case of polishing according to the present invention, the average thickness of the Si layer is 0.95 μm, and the variation in thickness is 0.05 μm, whereas in the conventional polishing, the average thickness of the Si layer is 1.10 μm. Variation was 0.5 μm on average. As described above, according to the present invention, it is possible to make the film more uniform and thinner than the conventional method.

【0036】なお、本実施例では電流値により研磨の制
御を行う例を示したが、電位差を用いても同様の制御を
行うことができる。
In this embodiment, the polishing is controlled by the current value, but the same control can be performed by using the potential difference.

【0037】[0037]

【発明の効果】以上説明したように、本発明によれば、
ウェハ上の各位置における研磨量を制御することにより
ウェハ全面の均一に研磨し、配線層の平坦化方法として
十分実用可能で、SOIウェハのSi層を更に薄膜化す
ることができる。
As described above, according to the present invention,
By controlling the polishing amount at each position on the wafer, the entire surface of the wafer can be uniformly polished, which is sufficiently practical as a method for planarizing the wiring layer, and the Si layer of the SOI wafer can be further thinned.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の方法によりデバイス作製過程で層間絶縁
膜を平坦化する研磨方法を示す断面図である。
FIG. 1 is a cross-sectional view showing a polishing method for planarizing an interlayer insulating film in a device manufacturing process by a conventional method.

【図2】従来の方法によりウェハ研磨を行う装置および
方法を示す配置図である。
FIG. 2 is a layout view showing an apparatus and a method for polishing a wafer by a conventional method.

【図3】張り合わせウェハの作製過程の一例を示す断面
図である。
FIG. 3 is a cross-sectional view showing an example of a manufacturing process of a bonded wafer.

【図4】本発明に従って、デバイス作製過程で層間絶縁
膜を平坦化するための研磨装置および研磨方法の一例を
示す配置図である。
FIG. 4 is a layout view showing an example of a polishing apparatus and a polishing method for planarizing an interlayer insulating film in a device manufacturing process according to the present invention.

【図5】本発明に従って、デバイス作製過程で層間絶縁
膜を平坦化するための研磨装置および研磨方法の他の例
を示す配置図である。
FIG. 5 is a layout view showing another example of a polishing apparatus and a polishing method for flattening an interlayer insulating film in a device manufacturing process according to the present invention.

【図6】本発明の研磨装置における研磨布装着面形状の
一例を示す図である。
FIG. 6 is a diagram showing an example of a polishing cloth mounting surface shape in the polishing apparatus of the present invention.

【図7】研磨試験に用いる供試ウェハ上のスタッドの配
置パターンを示す平面図である。
FIG. 7 is a plan view showing an arrangement pattern of studs on a test wafer used for a polishing test.

【図8】図7のウェハの研磨結果を示すグラフである。FIG. 8 is a graph showing a result of polishing the wafer of FIG.

【図9】本発明に従って、張り合わせSOIウェハはS
i層を薄膜化するための研磨装置および研磨方法の一例
を示す配置図である。
FIG. 9 shows a bonded SOI wafer according to the present invention as S.
It is a layout showing an example of a polishing device and a polishing method for thinning the i layer.

【図10】張り合わせSOIウェハの研磨結果を示すグ
ラフである。
FIG. 10 is a graph showing a polishing result of a bonded SOI wafer.

【符号の説明】[Explanation of symbols]

10…半導体基板 11…横方向導電部(horizontal interconnection) 12…縦方向導電部(studまたはvertical interconnec
tion) 13…CVDによるSiO2 絶縁層 14…研磨終了位置 21…回転軸 22…回転定盤 23…研磨布 24…回転軸 25…回転するウェハ保持板 26…ウェハ 31…Siウェハ 32…Siウェハ 33…熱酸化による酸化膜 401…Siウェハ 402…横方向導通部(インタコネクト)および縦方向
導通部(スタッド)のような導電部 403…層間絶縁膜 404…熱酸化膜等の絶縁膜 405…ウェハ401の下面の一部に配置された導体ペ
ースト等の導電物質 411…研磨装置のウェハ保持板(金属等の導電材料で
作られている) 412…ウェハ保持板411の回転軸(金属等の導電材
料で作られている) 421…研磨装置の回転式研磨治具(金属等の導電材料
で作られている) 422…研磨治具421の下部端面(研磨布装着面) W…研磨治具421の研磨布装着面422の幅 431…研磨布 432…研磨砥粒が自由に透過し得る多数の貫通路 441…ウェハ保持板411と研磨治具412との間に
印加される直流電圧 442…電流計 461…ウェハ401の中心部分上方に配置した流体供
給口 462…純水等の流体 463…ウェハ401面上を外側へ向かう流れの向き 501…張り合わせSOIウェハ 541…交流電圧 542…交流電圧計 601…ウェハ 602…Wスタッド
10 ... Semiconductor substrate 11 ... Horizontal conductive section 12 ... Vertical conductive section (stud or vertical interconnec)
13) ... SiO 2 insulating layer by CVD 14 ... Polishing end position 21 ... Rotating shaft 22 ... Rotating platen 23 ... Polishing cloth 24 ... Rotating shaft 25 ... Rotating wafer holding plate 26 ... Wafer 31 ... Si wafer 32 ... Si wafer 33 ... Oxide film by thermal oxidation 401 ... Si wafer 402 ... Conductive part such as lateral conducting part (interconnect) and vertical conducting part (stud) 403 ... Interlayer insulating film 404 ... Insulating film such as thermal oxide film 405 ... Conductive material such as a conductive paste disposed on a part of the lower surface of the wafer 401 411 ... Wafer holding plate of the polishing apparatus (made of a conductive material such as metal) 412 ... Rotating shaft of the wafer holding plate 411 (of metal or the like) 421 ... Rotary polishing jig of polishing apparatus (made of conductive material such as metal) 422 ... Lower end surface of polishing jig 421 (polishing cloth mounting surface) W ... Width of polishing cloth mounting surface 422 of polishing jig 421 ... Polishing cloth 432 ... Many through passages through which abrasive grains can freely pass 441 ... Applied between wafer holding plate 411 and polishing jig 412 DC voltage 442 ... Ammeter 461 ... Fluid supply port 462 disposed above the central portion of the wafer 401 ... Fluid such as pure water 463 ... Direction of flow outward on the surface of the wafer 401 501 ... Bonded SOI wafer 541 ... AC voltage 542 ... AC voltmeter 601 ... Wafer 602 ... W stud

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェハを保持板上に吸着保持し、
研磨治具に装着した研磨布を該ウェハの研磨対象面に接
触させ、研磨剤を該研磨布を透過させて該接触部に供給
しながら該保持板と該研磨治具の少なくとも一方を回転
させることにより該ウェハを研磨する際に、該ウェハの
吸着部と該研磨治具との間に電圧を印加し、研磨中に両
者間の電圧および/または電流を検出し、得られた検出
値に基づいて各研磨位置での研磨速度を制御することを
特徴とする半導体ウェハの研磨方法。
1. A semiconductor wafer is suction-held on a holding plate,
At least one of the holding plate and the polishing jig is rotated while the polishing cloth attached to the polishing jig is brought into contact with the surface to be polished of the wafer, and the polishing agent is passed through the polishing cloth and supplied to the contact portion. Thus, when polishing the wafer, a voltage is applied between the suction part of the wafer and the polishing jig, the voltage and / or the current between the two is detected during polishing, and the obtained detected value is obtained. A method of polishing a semiconductor wafer, which comprises controlling a polishing rate at each polishing position based on the polishing rate.
【請求項2】 前記保持されたウェハの研磨対象面のほ
ぼ中央部に流体を供給することにより、研磨屑をウェハ
外部へ排除することを特徴とする請求項1記載の研磨方
法。
2. The polishing method according to claim 1, wherein polishing debris is removed to the outside of the wafer by supplying a fluid to a substantially central portion of a surface to be polished of the held wafer.
【請求項3】 前記研磨布を装着する面の幅が、ウェハ
半径方向に対して内側よりも外側が小さい研磨治具を用
いることを特徴とする請求項1または2記載の研磨方
法。
3. The polishing method according to claim 1, wherein a polishing jig is used, in which the width of the surface on which the polishing cloth is mounted is smaller on the outer side than on the inner side in the radial direction of the wafer.
【請求項4】 研磨位置をウェハの半径方向内側から外
側に向けて順次移動させ研磨を行い、前記検出された電
流値が参照値以上または検出された電圧値が参照値以下
となったら研磨位置をウェハの半径方向外側に移動させ
るように制御することを特徴とする請求項1から3まで
のいずれか1項に記載の研磨方法。
4. The polishing position is sequentially moved from the inner side to the outer side in the radial direction of the wafer to perform polishing, and when the detected current value is equal to or higher than a reference value or the detected voltage value is equal to or lower than a reference value, the polishing position is set. 4. The polishing method according to claim 1, wherein the polishing is controlled so as to be moved to the outside in the radial direction of the wafer.
【請求項5】 前記ウェハの研磨対象面は絶縁体から成
る最表層とその下の導電体の層を有し、前記電圧として
直流電圧を印加することを特徴とする請求項1から4ま
でのいずれか1項に記載の研磨方法。
5. The surface to be polished of the wafer has an outermost surface layer made of an insulator and a conductor layer thereunder, and a DC voltage is applied as the voltage. The polishing method according to claim 1.
【請求項6】 前記ウェハの研磨対象面は半導体から成
る最表層とその下の絶縁体の層を有し、前記電圧として
交流電圧を印加することを特徴とする請求項1から4ま
でのいずれか1項に記載の研磨方法。
6. The surface to be polished of the wafer has an outermost layer made of a semiconductor and an insulating layer thereunder, and an alternating voltage is applied as the voltage. The polishing method according to item 1.
【請求項7】 前記ウェハ保持板を回転させて前記ウェ
ハの特定半径上を研磨する際に、該半径上で検出電流値
が小さいか検出電圧値が大きい位置では前記研磨布の接
触圧を増加させ、検出電流値が大きいか検出電圧値が小
さい位置では該接触圧を減少させることを特徴とする請
求項1から6までのいずれか1項に記載の研磨方法。
7. When the wafer holding plate is rotated to polish a specific radius of the wafer, the contact pressure of the polishing cloth is increased at a position where the detected current value is small or the detected voltage value is large on the radius. 7. The polishing method according to claim 1, wherein the contact pressure is reduced at a position where a detected current value is large or a detected voltage value is small.
【請求項8】 前記ウェハ保持板と前記研磨治具とを同
方向に回転させることを特徴とする請求項1から7まで
のいずれか1項に記載の研磨方法。
8. The polishing method according to claim 1, wherein the wafer holding plate and the polishing jig are rotated in the same direction.
【請求項9】 前記ウェハの特定半径上を研磨する際
に、該半径上で検出電流値が小さいか検出電圧値が大き
い位置では前記研磨治具の回転速度を増加させ、検出電
流値が大きいか検出電圧値が小さい位置では該回転速度
を減少させることを特徴とする請求項8に記載の研磨方
法。
9. When polishing a specific radius of the wafer, the rotation speed of the polishing jig is increased at a position where the detected current value is small or the detected voltage value is large on the radius to increase the detected current value. 9. The polishing method according to claim 8, wherein the rotation speed is reduced at a position where the detected voltage value is small.
【請求項10】 前記保持されたウェハの中央部に供給
する流体として、純水のような比抵抗の小さい液体、コ
ーティング剤または空気のような気体を用いることを特
徴とする請求項2〜9のいずれか1項に記載の研磨方
法。
10. A liquid having a low specific resistance such as pure water, a coating agent, or a gas such as air is used as a fluid supplied to the central portion of the held wafer. The polishing method according to any one of 1.
【請求項11】 半導体ウェハを吸着保持する保持板
と、先端に装着した研磨布を該ウェハの研磨対象面に接
触させるように配置した研磨治具と、該研磨布を透過さ
せて該接触部に研磨剤を供給する手段と、該ウェハの吸
着部と該研磨治具との間に電圧を印加する手段と、研磨
中に両者間の電圧および/または電流を検出する手段
と、得られた検出値に応じて研磨速度を制御する手段と
を有し、該保持板と該研磨治具の少なくとも一方が回転
し得ることを特徴とする半導体ウェハの研磨装置。
11. A holding plate for adsorbing and holding a semiconductor wafer, a polishing jig arranged so that a polishing cloth attached to a tip of the semiconductor wafer is brought into contact with a surface to be polished of the wafer, and the contact portion for transmitting the polishing cloth. A means for supplying an abrasive to the wafer, a means for applying a voltage between the suction portion of the wafer and the polishing jig, and a means for detecting the voltage and / or current between the two during polishing. And a means for controlling a polishing rate according to a detected value, wherein at least one of the holding plate and the polishing jig can rotate.
【請求項12】 前記保持されたウェハの研磨対象面の
ほぼ中央部に流体を供給する手段を有することを特徴と
する請求項1記載の研磨装置。
12. The polishing apparatus according to claim 1, further comprising means for supplying a fluid to a substantially central portion of a surface to be polished of the held wafer.
【請求項13】 前記研磨治具は前記研磨布を装着する
面の幅が、ウェハ半径方向に対して内側よりも外側が小
さいことを特徴とする請求項11または12記載の研磨
装置。
13. The polishing apparatus according to claim 11, wherein a width of a surface of the polishing jig on which the polishing cloth is mounted is smaller on the outer side than on the inner side in the wafer radial direction.
【請求項14】 研磨位置をウェハの半径方向に移動さ
せるための手段を有することを特徴とする請求項11か
ら13項のいずれか1項に記載の研磨装置。
14. The polishing apparatus according to claim 11, further comprising means for moving a polishing position in a radial direction of the wafer.
JP21432392A 1992-08-11 1992-08-11 Semiconductor wafer polishing method and polishing apparatus Expired - Fee Related JP3276409B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21432392A JP3276409B2 (en) 1992-08-11 1992-08-11 Semiconductor wafer polishing method and polishing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21432392A JP3276409B2 (en) 1992-08-11 1992-08-11 Semiconductor wafer polishing method and polishing apparatus

Publications (2)

Publication Number Publication Date
JPH0661205A true JPH0661205A (en) 1994-03-04
JP3276409B2 JP3276409B2 (en) 2002-04-22

Family

ID=16653858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21432392A Expired - Fee Related JP3276409B2 (en) 1992-08-11 1992-08-11 Semiconductor wafer polishing method and polishing apparatus

Country Status (1)

Country Link
JP (1) JP3276409B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02138577U (en) * 1989-04-21 1990-11-19
CN104493683A (en) * 2014-11-28 2015-04-08 上海华力微电子有限公司 Method for testing film grinding speed
JP2017216356A (en) * 2016-05-31 2017-12-07 株式会社Sumco Manufacturing method of SOI wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02138577U (en) * 1989-04-21 1990-11-19
CN104493683A (en) * 2014-11-28 2015-04-08 上海华力微电子有限公司 Method for testing film grinding speed
JP2017216356A (en) * 2016-05-31 2017-12-07 株式会社Sumco Manufacturing method of SOI wafer

Also Published As

Publication number Publication date
JP3276409B2 (en) 2002-04-22

Similar Documents

Publication Publication Date Title
KR100266119B1 (en) Method and apparatus for in-line oxide thickness determination in chemical-mechanical polishing
US5216843A (en) Polishing pad conditioning apparatus for wafer planarization process
KR100196590B1 (en) In situ monitoring technique and apparatus for semiconductor and optical device
JP3145010B2 (en) Semiconductor wafer processing apparatus and semiconductor wafer processing method
US6319420B1 (en) Method and apparatus for electrically endpointing a chemical-mechanical planarization process
US5321304A (en) Detecting the endpoint of chem-mech polishing, and resulting semiconductor device
US6306768B1 (en) Method for planarizing microelectronic substrates having apertures
US6132292A (en) Chemical mechanical polishing method suitable for highly accurate planarization
JPH0513389A (en) Polishing equipment
JP2001068441A (en) Selective damascene chemical mechanical polishing
JP2002528928A (en) Use of zeta potential for endpoint detection during chemical buffing
US20240308021A1 (en) Chemical mechanical polishing method
US20070135024A1 (en) Polishing pad and polishing apparatus
TW201926449A (en) Apparatus and method for planarizing substrate
JPH07153725A (en) Sub-micron bond SOI by trench flattening
JP2003526527A (en) Wafer polishing head and polishing method
US9962805B2 (en) Chemical mechanical polishing apparatus and method
JP3276409B2 (en) Semiconductor wafer polishing method and polishing apparatus
US20090061741A1 (en) Ecmp polishing sequence to improve planarity and defect performance
JP3916846B2 (en) Substrate polishing apparatus and substrate polishing method
TWI892619B (en) Chemical mechanical polishing apparatus for determining substrate orientation with acoustic signals
US7205236B2 (en) Semiconductor substrate polishing methods and equipment
KR20060038740A (en) Chemical mechanical polishing apparatus and polishing method using the apparatus
JP4849311B2 (en) Polishing method and semiconductor device manufacturing method using the polishing method
US20040181965A1 (en) Method and apparatus for cleaning and drying a workpiece

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20020108

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080208

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090208

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090208

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100208

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110208

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees