JPH066227A - A/d converter - Google Patents

Abstract

PURPOSE:To provide an A/D converter which can decrease the deterioration of the converting accuracy due to the offset dispersion of a voltage comparator. CONSTITUTION:The reference voltage ET and EB (ET>EB) are applied to the 1st and 2nd reference voltage input terminals 2 and 3 respectively. Under such conditions, the reference voltage having the subdivided scale (ET-EB)/256 (thereafter referred to as deltaE) is applied to one of both terminals of each voltage comparator 5. The output of a voltage comparator 5-2 is set at a high level when the analog input voltage applied to an analog signal input terminal 1 is higher than (EB+8deltaE). The high output of the comparator 5-2 is transmitted to a circuit 11. At the same time, the output of 3 less significant bits received from a digital signal generator 6 is supplied to an output terminal 13 of 3 less significant bits. Meanwhile the 3 less significant bits are calculated by majority of plural voltage comparison means by a block 8 and outputted to the circuit 11 when the analog input signal voltage is lower than (EB+8deltaE).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital (A / D) converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art Conventionally, there are several types of A / D converters for converting analog signals into digital signals.
Of these, the flash type A / D converter is often used for A / D conversion of high-frequency signals such as video signals because of its excellent conversion speed. FIG. 3 is a block diagram showing a conventional example of a flash type 8-bit A / D converter. In the figure, 31
Is an analog signal input terminal, 32 is a first reference voltage input terminal, 33 is a second reference voltage input terminal, 34 is a resistance element,
Reference numeral 35 is a voltage comparator including an operational amplifier, 36 is a circuit for generating a digital signal according to the output of the voltage comparator 35, and 37 is a digital signal output terminal. In this conventional example, the number of resistance elements 34 and voltage comparators 35 is 2 ⁸ =
The number is 256.

Next, the operation of the conventional flash type A / D converter will be described.

E is applied to the first reference voltage input terminal 32._T, Second
E to the reference voltage input terminal 33 of_B(E_T> E_B) Become a reference power
Assuming that a pressure is applied, the voltage comparator 35
The voltage applied to the terminals is (E_T-E_B) / 256
Each is 256 steps higher. The voltage comparator 35 is an analog
The analog signal voltage applied to the signal input terminal 31
Note: Compare 256 levels of reference voltage,
Output LOW or HIGH voltage. And the voltage ratio
Based on the output of the comparator 35, the circuit 36 outputs the digital code.
It is generated and output to the output terminal 37. Thus,
Shu type A / D converter has a reference voltage input terminal
The applied reference voltage is the upper and lower limits, and the upper and lower limits
Is divided into 256 equal parts and converted into digital signals. This and
Then, the number of bits of digital output is 8.

[0005]

The above-mentioned conventional flash type A / D converter requires a large number of resistance elements and voltage comparators, but the resistance values of these resistance elements and the characteristics of the voltage comparators are not constant. , There are variations. In particular, an operational amplifier is usually used for the voltage comparator, but the input voltage for setting the output of the operational amplifier to 0V is not 0V but has an error called offset. Since this offset varies, the linearity of A / D conversion,
That is, there is a problem that the conversion accuracy is inferior to other methods. In view of the above problems, it is an object of the present invention to provide an A / D converter that can reduce deterioration of conversion accuracy due to variations in offset of a voltage comparator.

[0006]

In order to achieve the above object, an A / D converter of the present invention has an analog signal input terminal, two reference voltage input terminals, and a series connection between the two reference voltage input terminals. It comprises a connected resistance element, a plurality of voltage comparison means for comparing the voltage between the plurality of resistance elements and the analog signal level, and a circuit for generating a digital signal from the outputs of the plurality of voltage comparison means. When the analog input voltage is within a predetermined range, the voltage comparison means compares the voltage between the resistance element and the analog input terminal by majority decision of the plurality of voltage comparator outputs connected in parallel to the same resistance element. Is used as a comparison result.

[0007]

With the above structure, it is possible to reduce deterioration in conversion accuracy due to variations in offset of the voltage comparator.

[0008]

FIG. 1 shows the first embodiment of the present invention. FIG. 1 shows a flash type 8-bit A /
It is a block diagram applied to a D converter. In the figure, 1 is an analog signal input terminal, 2 is a first reference voltage input terminal, 3 is a second reference voltage input terminal, 4 is a resistance element,
5 is a voltage comparator including an operational amplifier, 6 is a circuit for generating an 8-bit digital signal based on the output of the voltage comparator 5, 7 is a digital signal output terminal of the upper 6 bits,
Reference numeral 8 is a block for generating a digital signal of the lower 3 bits, the details of which are shown in FIG. 9 is a terminal connected to the terminal 21 of FIG. 2, 10 is a terminal connected to the terminal 22 of FIG. 2, 11 is a digital code transmitted to the lower 3 bits output terminal 13 based on the output of the voltage comparator 5-2. Is a 3-bit code of either the circuit 6 or the block 8, 12 is a terminal connected to the terminal 25 of FIG. 2, and 13 is a digital signal output terminal of the lower 3 bits.

FIG. 2 is a detailed view of block 8 of FIG.
2, 21 is a terminal connected to the terminal 9 of FIG. 1, 22 is a terminal connected to the terminal 10 of FIG. 1, 23 is a resistance element, 2
Reference numeral 4 is a voltage comparator composed of operational amplifiers, 25 is a terminal connected to the terminal 11 of FIG. 1, and 26 is five voltage comparators 2.
6 is a circuit for obtaining the majority decision of the output of 6; 27 is a code converter for generating a 3-bit digital code based on the output of the circuit 6;
28 is a digital output terminal of the lower 3 bits.

Next, the operation of the present invention will be described.

In FIG. 1, the first reference voltage input terminal 2
E _T in, if that second reference voltage E _B at the input terminal 3 (E _T> E _B) becomes the reference voltage is applied, to one terminal of the voltage comparator 5 in Figure 1, ( A reference voltage in increments of E _T −E _B ) / 256 (hereinafter referred to as δE) is applied. At this time
The voltage of the terminal 9, the E _B + 8δE. Thus, the analog input voltage applied to the analog signal input terminal 1, E _B
When + 8δE or more, the output of the voltage comparator 5-2 is HI.
Become GH. The HIGH output of the voltage comparator 5-2 is the circuit 1
1 is transmitted. At this time, the lower 3 bits output from the circuit 6 is connected to the lower 3 bits output terminal 13 of 13. In this state, the first embodiment of the present invention performs A / D conversion by the same method as the conventional example. When the analog input signal voltage is lower than E _B + 8δE, the voltage comparator 5-2
Becomes LOW, and at this time, the circuit 11 connects the 3-bit output from the block 8 to the lower 3-bit output terminal 13. At this time, the digital output is the upper 5 bits (0
Will be converted by the conventional method,
The lower 3 bits are converted by the present invention.

Now, the conversion means of the lower 3 bits will be described in detail with reference to FIG. In FIG. 2, the input analog signal is applied to the terminal 22, and the reference voltage is applied to the terminals 21 and 25. The input analog signal voltage is
When it is lower than E _B + 8δE, the analog input voltage is compared with the reference voltage divided by the resistance element 23 in FIG. The five voltage comparators 24 connected in parallel to the resistance element 23 of FIG. 2 compare the analog signal voltage with the reference voltage and transmit the outputs represented by LOW or HIGH to the respective circuits 26. In the circuit 26, the majority of the five input voltage comparator outputs is decided. That is, if LOW is 3 or more out of 5 inputs, LOW voltage is output and HIGH is 3
If it is more than this, it outputs HIGH voltage. Circuit 27 is circuit 26
A 3-bit digital code is generated on the basis of the output of 1 and is output to the output terminal 27.

[0013]

As described above, according to the present invention,
When the analog input voltage is within a predetermined range, a voltage comparison is performed using a plurality of voltage comparators connected in parallel to the same resistance element, and a majority of the plurality of comparison results is taken.
It is possible to reduce deterioration of conversion accuracy due to variation in offset of the voltage comparator.

[Brief description of drawings]

FIG. 1 is a block diagram applied to a flash type 8-bit A / D converter as one embodiment of the present invention.

2 is a detailed diagram of a block 8 for generating a digital signal of lower 2 bits of FIG. 1. FIG.

FIG. 3 is a block diagram showing a conventional example of a flash type 8-bit A / D converter.

[Explanation of symbols]

1 Analog signal input terminal 2 First reference voltage input terminal 3 Second reference voltage input terminal 4 Resistor element 5 Voltage comparator 6 Circuit for generating digital code of upper 5 bits 7 Upper 5 bit digital signal output terminal 8 Lower Block for calculating 3 bits and precision loss bit 9 Terminal connected to terminal 21 of FIG. 2 10 Terminal connected to terminal 22 of FIG. 11 Terminal connected to terminal 25 of FIG. 2 Lower 3 bits Digital signal output terminal 13 Terminal for outputting a 2-bit precision loss

Claims (1)

[Claims] 1. An analog signal input terminal, two reference voltage input terminals, a plurality of resistance elements connected in series between the two reference voltage input terminals, and a voltage between the plurality of resistance elements. In an analog-digital converter comprising a plurality of voltage comparing means for comparing the analog signal levels and a circuit for generating a digital signal from the outputs of the plurality of voltage comparing means, the analog signal input voltage is within a predetermined range. In one case, the voltage comparison means generates a digital code based on a majority decision of outputs of a plurality of voltage comparators connected in parallel to the same resistance element, and an analog-digital converter.