JPH0664478B2 - Pattern recognizer - Google Patents

Abstract

PURPOSE:To shorten the process time without requiring large memory capacity by detecting a target pattern from candidates obtained by setting a precedent- stage as candidate selection and a succeeding stage as high precision by DP arithmetic. CONSTITUTION:A CPU 6 controls the DP arithmetic and the output of the result of a personal computer 11 through an input/output control system 10 in addition to control over an A/D converter 4 and the storage of data. When data is inputted from the A/D converter 4, precedent-stage DP arithmetic is performed first. Namely, the distance to standard data previously stored in a RAM 9 is found. A next candidate selecting process is performed after speech data of a specific time, e.g. of one word and all inputted and arithmetic corresponding to the data is all completed. The precedent-stage arithmetic is naturally not certain, so a selecting process for performing the DP arithmetic again is carried out for standard pattern data of a distance result entering a specific range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recognizing device, and more particularly to a pattern recognizing device for selecting a candidate from a pre-matching result of a recognizing device which performs two-stage matching in dynamic programming (DP method).

[0002]

2. Description of the Related Art Generally, a character recognition device, a voice recognition device, or the like extracts characteristic parameters of an input character or voice,
Pattern matching is performed with a pattern stored in advance, and the pattern with the highest similarity is selected and recognized.

The voice frequency spectrum is often used as the above-mentioned voice characteristic parameter, and the spectrum is obtained by a method using a large number of bandpass filters or a fast Fourier transform. Then, the frequency spectrum of the voice obtained by these methods is compared with the pattern registered in advance as described above, that is, the similarity with the standard pattern is obtained, and the standard pattern closest to the input data is the input data. And output the result.

When the above-mentioned input data is compared with the registered pattern, the time axes do not always correspond to each other on a one-to-one basis, but change depending on the relationship between the preceding and following words or the length of a long sound. To do. As described above, there is a DP method as a method for obtaining the similarity between patterns whose time axes and the like do not correspond one-to-one, that is, a pattern matching method (generally, the similarity between two patterns is represented as a distance).

The DP method is applied not only to voice recognition but also to character recognition devices and the like. This DP method has a drawback that the calculation time increases as the number of feature points increases, because the minimum distance between the respective feature points is obtained over the entire distance. In order to compensate the above-mentioned drawbacks of the DP method,
Generally, the following method is used. First, the pattern itself is linearly expanded / contracted, pre-selection is performed by linear matching, and the DP selected for the standard pattern is selected.
This is a method for obtaining the standard pattern with the minimum distance by the method.

[0006]

Since the processing speed of the linear matching method is higher than that of the DP method, the processing speed of the above method is also faster than that of the case where the DP method is performed for all standard patterns. However, since this method linearly compresses the pattern, it has a drawback that the characteristic of the nonlinear nonlinear compression on the time axis, which is the characteristic of the DP method, is diminished. Further, the linear matching used for the preliminary selection has a problem that a target standard pattern may not be selected in the preliminary selection because there are many misrecognitions for a word having a long duration as compared with the DP method. .

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to effectively select a candidate from the DP matching result of the preceding stage in the two-stage DP matching and to select the candidate when performing the latter DP matching. Another object of the present invention is to provide a pattern recognition device.

[0008]

A feature of the present invention resides in a pattern recognition apparatus for determining a recognition result by performing pattern matching between input pattern data and standard pattern data stored in advance. A plurality of candidate standard pattern data is selected by the next DP matching process, and a candidate selecting unit for selecting a first candidate or a second candidate from the ones that are judged to have a higher similarity than the standard pattern data, and the first candidate. When it is determined that the distance between the input pattern data and the input pattern data is equal to or greater than a first specific value, it is determined that the recognition is impossible, and means for notifying the recognition failure; A means for determining the first candidate as a recognition result when it is determined that the distance between the first candidate and the second candidate is equal to or greater than a second specific value; Means for determining a recognition result by a secondary DP matching process from among the plurality of candidate standard pattern data selected by the candidate selecting means, when the recognition result is not determined by the means. The pattern recognition apparatus is characterized in that the first-order DP matching process is performed with a coarser accuracy than the second-order matching process.

[0009]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention using a processor. The microphone 1 is connected to the BPF circuit 3 via the AGC circuit 2. The output of the BPF circuit 3 is added to the A / D converter 4. The bus line 7 connected to the processor (CPU) 6 has the above A
Read-only memory (ROM) in addition to the / D converter 4
8, a random access memory (RAM) 9 and an input / output control system (IOCS) 10 are connected.
The input / output control system (IOCS) 10 is connected to another device such as a personal computer 11. The voice that has entered the microphone 1 is converted into a voice signal, that is, an electric signal. Since the level of this electric signal varies depending on the loudness of a person's voice or the distance between the person's mouth and the microphone, the level is almost constant.
Input to C circuit 2. The AGC circuit is a circuit whose gain changes so that its output becomes almost constant. The output of the AGC circuit 2, that is, the audio signal having a constant level is applied to the BPF circuit 3. The BPF circuit 3 has a plurality of band pass filters so that the voice band is divided into eight, for example.
The circuit 3 divides it into eight specific bands. 8 for each band
The divided audio signal is added to the A / D converter 4 to convert, for example, the power of the audio signal in each band into a digital amount. The A / D converter 4 converts one band of the output of the BPF circuit 3, that is, one channel into 8-bit data, so that a total of 64-bit data is output to the bus line 7 in 8-bit units, for example. The A / D converter 4 described above
Is controlled by a processor (CPU) 6 via a bus line 7, and the above-mentioned 64-bit data is divided in units of channels to generate a random access memory (RA).
M) 9 is stored.

The processor (CPU) 6 controls the A / D converter 4 and stores the data as well as the calculation process in the DP method, that is, the DP calculation and the personal computer 1.
Input and output control system (IOCS) 1
The output is controlled via 0. These calculations and controls are performed by the processor (CPU) 6 executing a program stored in advance in the read-only memory (ROM) 8. And random access memory (RA
M) 9 is also used as a work area at that time.

FIG. 2 is a flow chart for explaining the above-mentioned DP calculation processing. When data is input from the A / D converter 4, the DP calculation process starts 12, and first, the preceding stage DP calculation 13 is performed. The pre-stage DP operation 13 is to obtain the distance from the standard data stored in the random access memory (RAM) 9 in advance. However, this calculation is not performed for all input data, but is performed at a specific data interval, for example, once in three times of input data. In addition, one measurement data consists of 64 bits in total as described above. When all the voice data of one word is input for a specific time and all the calculations corresponding to the input are completed, the next candidate selection process 14 is executed. The preceding-stage DP operation 13 executed previously is one in which the DP operation is performed on the input data once in three times, and the operation naturally lacks certainty. Therefore, the selection process for performing the DP operation again is performed on the standard pattern data of the distance result that falls within the specific range. This selection process is the candidate selection process 1
It is 4. However, when the distance of only one standard pattern data is within the predetermined distance by the preceding DP calculation 13, the DP calculation is not performed again and it is determined that the standard pattern is the input data 15. It is output to the personal computer 11 via the input / output control system (IOCS) 10 shown in FIG. If there is nothing within the predetermined distance, the input data cannot be recognized and is invalidated 16. Furthermore, when the calculation result using a plurality of standard patterns is entered within the above-mentioned specific distance and the difference in distance from the first candidate falls within a specific range, the pattern from the minimum distance to, for example, the fifth pattern is selected. Select as a candidate. If the difference in distance from the first candidate is less than or equal to five within the specific range, only those numbers are selected as candidates. When the candidate is determined, the candidate selection processing 14 is ended and the subsequent second-stage DP calculation 17 is executed. In the front-stage DP operation 13, the input data and the standard pattern data lined up corresponding to the time are used once in every three operations, but the second-stage DP operation 17 performs all of the selected standard pattern data. Find the minimum distance to the data. Then, the standard pattern having the smallest value in the minimum distance corresponding to each selected standard pattern data is determined 15 as being in agreement with the input data, and is output.

FIG. 3 is a flowchart showing the candidate selection processing 14 in more detail. After Start 14-1,
First, the minimum distance D (1) with respect to the standard pattern is detected and compared 14-2 with the first specific value Drej. That is, D (1) is subtracted by Drej to determine whether or not there is a carry. D (1) ≧ Dr without carry
In the case of ej (Y), it is invalid 16. This is the front DP
In the calculation, it means that there is a high possibility that the target standard pattern does not exist even if the latter-stage DP calculation is performed because the distance is too large, and the first specific value Drej
Is the threshold value. D with carry
When (1) <Drej (N), it is determined 14-3 whether the difference value from the second minimum distance D (2) is equal to or larger than the second specific value Ddec. Although the error in the processing in the preceding DP calculation is larger than that in the processing in the subsequent DP calculation,
If the difference between the first candidate, that is, the standard pattern of the distance of D (1) and the second candidate, that is, the standard pattern of the distance of D (2) is equal to or more than the second specific value Ddec described above, the subsequent arithmetic processing Even if you do, there is no change in the candidate ranking.
As a result, if there is a difference equal to or greater than the second specific value, the first candidate is determined to be coincident and determined 15. That is, it is determined 15 that (D (2) −D (1)) ≧ Ddec is satisfied (Y).

If the above-mentioned difference is small, it is within the error range in the previous processing, so the first to fifth candidates are selected 14-
4. That is, a candidate D (n) whose difference from the minimum distance D (1) of the first candidate is smaller than the third specific value D _DP is obtained. Then, the first to fifth candidates are selected. That is, the standard pattern whose difference from the first candidate is less than or equal to the third specific value D _DP is selected within the fifth from the minimum value. When the selection process 14-4 described above ends, the candidate selection process 14 ends 14-5.

In FIG. 2, the post-stage DP operation 17 performs all the data corresponding to the time of the standard pattern. Since the maximum number of standard patterns at that time is 5, the operation time is all the standard patterns. It is much faster than the calculation. For example, when there are 64 standard patterns, the maximum is shortened to 5/64. Further, since the preceding-stage DP calculation is performed once every three times, the calculation processing is far less than that for all the data of one standard pattern.

Further, after selecting a candidate, the number of candidates may be 5 or less, or may be further determined, and the processing time is much faster than the processing in which the DP calculation is performed. .

FIG. 4 is a circuit configuration diagram of the second embodiment of the present invention. In the embodiment of the present invention shown in FIG. 1, the arithmetic operation and its control are performed in the processor, but in the embodiment of FIG. 4, all are controlled by the circuit, and the arithmetic operation is also performed by the circuit. The A / D converter 18 includes the BPF shown in FIG.
The output of the circuit 3 is added, and the output is input to the level detection unit 21 and the input pattern memory 20 via the parameter normalization compression unit 19. The detection output of the level detector 21 is added to the timing controller 22. And the timing control unit 2
The control output of No. 2 is input to the A / D converter 18, the parameter normalization compression unit 19, the frame counter 23, and the control unit 24. An address output output from the control unit 24 is added to the input pattern memory 20, standard pattern memory 25, work area memory 26, and minimum distance memory 27.

The distance calculation unit 28 includes the input pattern memory 2
0, the output of the standard pattern memory 25 is added, and the output is input to the work area memory 26 via the partial sum calculation unit 29. The output of the work area memory 26 is applied to the partial sum calculator 29 and the minimum distance calculator 30. In addition to this, the output of the standard pattern frame length memory 31, the output of the frame counter 23, and the gate circuit 33 and the frame number correction unit 3 are also output to the minimum distance calculation unit 30.
Join via 4. The output terminal of the minimum distance calculation unit 30 is connected to the input terminal of the minimum distance memory 27, and the output terminal of the minimum distance memory 27 is connected to the input terminal of the candidate selection unit 35. The output of the candidate selection unit 35 is the candidate number memory 3
6 and the controller 24. Then, the determination result 37 is further output. The candidate number memory 36 is connected to the control unit 24. The control output of the controller 24 is added to the distance calculator 28, the partial sum calculator 29, the minimum distance calculator 30, the standard pattern frame length memory 31, and the candidate selector 35. Further, a control signal is input from the control unit 24 to the control terminal of the gate circuit 32 and to the control terminal of the gate circuit 33 via the inverter 38. In the figure, A is a symbol indicating that it is connected.

The respective band-divided signals applied to the A / D converter 18 are converted into digital amounts and input to the parameter normalization compression unit 19. In the parameter normalization compression unit 19, the input data is normalized by the value of the maximum value + 1 and converted into the number of bits required for processing, that is, the effective bit number or less is cut. When the maximum value is equal to or smaller than the specific value, the input data is normalized with the specific value and converted into the number of bits necessary for the processing as described above. The data converted into the specific number of bits by this is stored in the input pattern memory 20. The level detection unit 21 detects whether the data processed by the parameter normalization compression unit 19 has a specific value, that is, a threshold level TH or higher. The timing control unit 22 performs an operation of switching the timing signal according to the result obtained by the level detection unit 21. This is performed in order to detect the start of the voice section TS early when the A / D converter 18 and the parameter normalization compression unit 19 operate. As a result, when the input parameter, that is, the data Da is below the threshold level TH, at the high-speed clock T _PS , when it is above the threshold level TH, that is, at a specific slow clock when entering the voice section, the A / D converter 18 In addition, the parameter normalization compression unit 19 operates.
The data obtained by the above operation is stored in the input pattern memory 20 in the voice section TS. Similar to the processing of the processing device using the processor of FIG.
Although the P operation and the post-stage DP operation are performed, the processing is performed by the same circuit in the circuit of the embodiment of the present invention shown in FIG. The control by the control unit 24 determines whether the preceding-stage DP calculation or the subsequent-stage DP calculation is performed. That is, the front DP calculation and the rear DP calculation are different only in access to the input pattern memory 20, the standard pattern memory 25, and the work area memory 26, and the distance calculation unit 28 related to the DP calculation,
The partial sum calculation unit 29 and the minimum distance calculation unit 30 perform exactly the same operation. As described in the description of FIG. 1, the difference is that the DP operation is not performed on all data,
This means that one out of three operations is performed, which means that the control unit 24
Only the generated address value of each memory is different.

The distance calculation unit 28, the partial sum calculation unit 29, and the minimum distance calculation unit 30 are circuit units related to the DP calculation as described above. First, the DP calculation will be described using equations.
Input pattern | A | and standard pattern | B | are respectively | A | = | A | ₁ , | A | ₂ , || A | _j ... (1) | B | = | B | ₁ , | Let B | ₂ , ... | B | _i ... (2). | A | ₁ to | A | _j , | B | ₁ to | B | _i are feature vectors at a certain time. The feature vector at this certain time is, for example, 8 in the embodiment of the present invention.
Dimensional (speech band is divided into 8) feature vectors, and | A | _j = (a _j1 , a _j2 , ... a _j8 ) ... (3) | B | _j = (b _i1 , b _i2 , ... b _i8 ) ... (4)

The partial sum g (i, j) in the DP operation is generally

[0021]

[Equation 1]

It is represented by Where d (i, j) is the distance between each feature vector,

[0023]

[Equation 2]

Is defined by Further, dw is the window width on one side, and if the window width is W, then W = 2dW + 1. The above equation (5) is an equation representing the partial sum in the DP operation, and the inter-pattern distance is obtained by g (I, J). On the other hand, in the case of voice recognition or the like, the input pattern data and the standard pattern data have different input times. That is, (1)
Since I and J in the equation (2) are not constant, they must be normalized by the number of samples. In the embodiment of the present invention, since the number of samples is different between the input pattern data and the standard pattern data, the final pattern distance G
(I, J) is

[0025]

[Equation 3]

[0026] On the other hand, in the embodiment of FIG. 4 of the present invention, variable conversion is performed for the calculation. That is, i = m + j-dw-1 (7) where 1 ≦ m ≦ w l = j (8) l ′ = j−1 (9) and m, l, l ′ Calculations are performed using related formulas.
By substituting the equations (7) to (9) into the equations (5) and (6) and converting them, e (dw + 1,1) = 2d (1,1) (10)

[0027]

[Equation 4]

[0028] And the final inter-pattern distance E (M, L) after conversion is

[0029]

[Equation 5]

However, M = I−J + dw + 1 (13) L = J (14)

In equation (10) ', m ≠ dw + 1,1
When ≦ m ≦ w, e (m, 1) is infinite. As will be described later, in order to store the minimum value of the expression (11) in the memory, the maximum value is stored in the memory at the same time as or before the operation of the expression (10).

Further explanation of FIG. 4 will be continued. The distance calculation unit 28 is a circuit that calculates the distance d (i, j) between the above-described feature vectors. That is, the input pattern memory 20
Then, the equation (5) ′ is calculated from each data input from the standard pattern memory 25. Then, the calculation result is output to the partial sum calculation unit 29. The partial sum calculation unit 29 calculates the formulas (10) and (11) from the calculation result obtained from the distance calculation unit 28 and the data obtained from the work area memory 26.

In the preceding DP calculation, the calculation is performed at a ratio of one in three of the input data, that is, the above-mentioned feature vectors. That is, | A | ₁ , | A | ₄ ...
_Operate only on | A | _{3P + 1} . Similarly, as for the standard pattern data, | B | ₁ , | B | ₄ ... | B | _3P ′ ₊₁ are read from the standard pattern memory 25 at a ratio of 1 in 3 and used for the calculation.

All the data are used in the latter DP calculation. The minimum distance calculation unit 30 is a circuit that operates after the end of a voice section described below. This minimum distance calculation unit 30
Calculates the minimum value of each standard pattern data from the distance data in the work area 26. That is, it is a circuit for obtaining E (M, L) in the above equation (12).

First, the work area memory 2 stores e (M, L) corresponding to M and L which satisfy the above-mentioned equations (13) and (14).
Calculated from 6. Standard pattern frame length memory 3
I output from 1 and data J output from the frame counter 23 are added, and e (M, L) is divided by the result. Then, the result is stored in the minimum distance memory 27.
However, in the case of the pre-stage processing, the frame lengths of the input pattern and the standard pattern are almost one-third, but I and J are integers and are not always divisible by 3, so I and J are the same. Is a multiple of 3 (I / 3) +1, (J / 3) +1
When I and J are multiples of 3 plus 1, {(I-1) /
3} +1, {(J-1) / 3} +1, and when I and J are multiples of 3 plus 2, {(I-2) / 3} +1, {(J-
2) / 3} +1 is output from the standard pattern length memory 31 and the frame number correction unit 34.

In this way, I / 3 and J / 3 are the case of the pre-stage processing, and in the case of the post-stage processing, I is from the standard pattern frame length memory 31 and J is from the frame counter 23 via the gate. Is entered.

[0037]

[Equation 6]

Is calculated. The candidate selecting unit 35 obtains a minimum distance from the minimum distances for the respective standard pattern data stored in the minimum distance memory 27,
The pattern number (1 to n) corresponding to the standard pattern data is stored in the candidate number memory 36. Candidate selection unit 35
Is the same as the two-stage DP operation using the processor described above,
The operation of storing in the candidate number memory 36 differs depending on the condition. When the distance of only one standard pattern data is within the predetermined distance by the preceding DP calculation 13, the determination result, for example, the pattern number is output to the terminal 37 as the determination. Further, this result is output to the input / output control system (IOCS) 10 via the control unit 24. At this time, the control unit 24 does not control the subsequent DP calculation processing and waits for the next input pattern data to be input. If there is nothing within the predetermined distance, the input data is output as the unrecognizable data to the control unit 24. In this case as well, the control unit 24 outputs to the input / output control system (IOCS) 10 that the recognition is impossible. Further, when the calculation result using a plurality of standard patterns is entered within the above-mentioned specific distance and the difference in the distance from the first candidate falls within the specific range, the pattern from the minimum distance to, for example, the fifth pattern is set as the candidate. Select. If there are only five or less in the specific range, or if the difference in distance from the first candidate does not fall within the specific range, only that number is selected as a candidate. That is, in this case, 2 to 5 numbers are stored in the candidate number memory 36. The candidate number memory 36
The number is stored only when the pre-stage processing is performed, and in the post-stage calculation, this candidate selection unit outputs the number (1 to n) to the control unit 24 after detecting the minimum value.

The above-described distance calculation unit 28 and partial sum calculation unit 2
9. The minimum distance calculation unit 30 and the candidate selection unit 35 are commonly used in the case of the front stage DP calculation and the rear stage DP calculation, respectively.

As described above, the level detection unit 21 is a circuit which determines whether or not the level of the parameter normalization compression unit 19, that is, the parameter Da is equal to or higher than a specific value (threshold level TH). TH
With the above detection, the clock T _PS is changed to T _S to start the DP calculation processing. On the contrary, when it is detected during the calculation processing, it becomes a signal for saving the candidates. Timing control unit 2
Reference numeral 2 is a circuit for controlling these timings.

FIG. 5 is a circuit diagram of the timing controller 22. The detection signal from the level detection unit 21 is passed through the set terminal S of the flip-flop 40, the reset terminal R of the counter 51 and the inverter 41, and AND gates 42 and 43.
Join the gate. The output Q of the flip-flop 40 is connected to the gates of the AND gates 44 and 45 and the gate of the AND gate 47 via the inverter 46. The clock outputs T _S and T _PS of the timing generator 48 are AND gates 4.
Input to the OR gate 49 via 5, 47. The output of the OR gate 49 is connected to the A / D converter 4 and the parameter normalization compression unit 19. Output T of AND gate 45
Input AND gate 42 of the _S 'are ternary counter 50,
Join the gate of 44. The output of the AND gate 44 is connected to the frame counter 23. The output of the AND gate 42 is added to the counter 51, and the NO.
The 7-output is applied to the reset terminal R of the flip-flop 40 and is output to the control unit 24 as a terminal output. The clock output of the timing generator, the output of the AND gate 43, and the output Q of the flip-flop 40 are added to the controller 24. The NO. 2 outputs are timing generator 4
8 and an AND gate 43.

FIG. 6 shows the timing of the timing control unit 22.
It is a chart figure. The timing control unit will be described below with reference to FIG.
The operation of 22 will be described. Flip-flop 40 is reset
Output Q is low level (L level)
Because of this, the AND gates 44 and 45 are turned off. However
However, the signal is added to the inverter 46.
Then, the output of the inverter 46 is high level (H level)
Become. The output of the inverter 46 is added to the AND gate 47.
Since the AND gate 47 is turned on,
Clock T generated by the ring generator 48_PSIs Andge
It is output via a gate 47 and an OR gate 49. In FIG.
Clock T_PS'Is a signal indicating the output of the AND gate 47.
No. The parameter Da is the threshold level T
When it becomes higher than H, the output of the level detection unit 21 becomes H level.
Next, set flip-flop 40 and cow
Reset the printer 51. This makes the flip flo
The output of the counter 40 becomes H level and the counter 51
Value becomes 0. The output of the flip-flop 40 is H level.
And gate 47 turns off and gate
44 and 45 are turned on. Timing is generated by this
The clock T generated by the unit 48_SAnd gate 45,
It is output via the OR gate 49. OR gate 49
Output is A / D converter 18 and parameter normalized pressure
It is added to each clock terminal of the reduction unit 19.
And, below the threshold level, the timing is
T_PSDone in T_SBecomes For example, T_SAnd T_PS
If the relationship of clock frequencies of T is set to 1: 3, T_Sof
Reads low level with 3 times clock and threshold
When the level is exceeded, T _SSampling at the clock
It is taken in as data for the DP calculation. And gate
45 outputs or clock T_S'Also on the counter 50
Since it is added, the output of the counter 50, that is, the cow
Since the input terminal 50 is a ternary counter, the signal divided by 1/3
Signal is inverted through the timing generator 48 and T
_FDPSignal to the control unit 24. T_FDPThe signal is
At the timing of, the circuit shown in FIG.
It will be Also, since the AND gate 44 is turned on,
Clock T_S′ Is output and added to the frame counter 23.
Wow The output Q of the flip-flop 40 is the control unit 2
4 is added to the start signal terminal, the control unit 24
The first stage DP performance when the lip flop 40 becomes H level
Start arithmetic control.

On the other hand, the signal level of an audio signal may temporarily drop. For example, the sound of "tsu" like a gackou (school) is a clogged sound, and the level of the sound is lowered. However, if this is set as the end point, there is erroneous recognition, so that it is recognized by detecting that the specific time level has decreased. The counter 51 detects this specific time. When the flip-flop 40 is in the set state and the level detection unit 21 is at the low level, the reset of the counter 51 is released, the H level is added through the inverter 41, and the AND gate 42 is turned on.
As a result, the clock generated from the AND gate 45 is added to the counter 51 via the AND gate 42. The counter 51 is an octal counter, and after the reset is released, 7 clocks are input, so that the NO. 7 output is H
It becomes a level. Level detection unit 21 again before 7 clocks
The counter 51 is reset when becomes H level. Then, when the signal input from the level detector 21 next becomes L level, the same operation is repeated. When the counter 51 counts 7 clocks, NO. Since the 7th output becomes the H level, the flip-flop 40 is reset and becomes the initial state. The NO. 7 outputs are control unit 2
4 has been added to the terminal for determining the termination, and the control unit 24 performs the DP calculation in the subsequent stage. On the other hand, since the signal of the level detecting unit 21 is also applied to the gate 43 via the inverter 41, when the signal of the level detecting unit 21 becomes L level, the H level is applied to the gate 43 and the output of the counter 50 serves as a save signal. Join the control unit 24.

The save signal, that is, the output signal of the AND gate 43 is output to the control unit 24 in synchronization with the output of the counter 50 when the level detection unit 21 is in the L state. Then, the control unit 24 saves the candidates. Retreat means to read data from the partial sum calculation result in the DP calculation stored in the work area memory 26, and the minimum distance calculation unit 30 performs the final calculation to perform the standard pattern number (1 to n) and the minimum distance memory 2
7, the candidate selection unit 35 determines a candidate, and the candidate number memory 36 stores the candidate. This evacuation is 7 after the output of the level detection unit 21 becomes L level.
It can also be done after the clock (T _S ′). However, by performing this saving during the L-level detection period, that is, the 7-clock period described above, it becomes possible to execute the latter-stage DP operation at the same time when the termination is determined. Becomes even shorter.

In the timing chart shown in FIG. 6, a temporary drop in the level is detected in the voice area, and the evacuation is being performed. However, since the subsequent level becomes the H level,
The previous DP calculation process is executed again. And the silent section T
In Sn, the candidate is saved again, the end is detected at the 7th clock, and the candidate is determined. The voice section TS and the silent section TSn are the front-stage DP calculation, and the rear-stage DP calculation is performed between the candidate determination and the word determination. This is the word determination section TJ of this section. The clocks T _BDP and T _FDP are the front and rear D
This is a clock for P operation, and the control unit 24 controls each operation unit in synchronization with this clock. Returning to FIG. 4, further description will be given. The clock generated by the timing control unit 22 and input to the frame counter 23 is the frame counter 23.
Is counted in. The counter 23 determines the number of frames of input pattern data. The output of the frame counter 23 is applied to the gate circuits 32 and 33.
Since the output signal of the control unit 24 is applied to the control terminal of the gate 32 and the control terminal of the gate 33 via the inverter 38, one of the gates 32 and 33 is always on. In the case of the preceding DP calculation, since the L level is output from the control unit 24, the gate 33 is turned on and the output of the frame counter 23 is added to the frame number correction unit 34 via the gate 33. The frame number correction unit 34 is a circuit that makes the value of the frame counter almost ⅓ as described above, and when the input J is 3U (U is an integer), (J / 3)
When +1 is output and the input J is 3U + 1, {(J-1) / 3}
When +1 is output and input J is 3U + 2, {(J-2) / 3}
Output +1. This output is used in the minimum distance calculation unit 30 in the preceding DP calculation. On the other hand, during the second-stage DP calculation, the gate 32 is turned on and the gate 33 is turned off, and the output J of the frame counter is directly added to the minimum distance calculation unit 30.

Further, the standard pattern frame length memory 31
As described above, the control unit 24 controls whether it is the front-stage DP calculation or the rear-stage DP calculation, and the minimum distance calculation unit 30 has a value related to the frame number I of each standard pattern corresponding thereto, that is, When I is 3U '(U' is an integer) in the previous DP calculation, (I / 3) +1, I is 3U '
When (+1), {(I-1) / 3} +1 is output, when I is 3U '+ 2, (I-2) / 3 + 1 is output.
Is output as is. Incidentally, I is the standard pattern memory 25.
It changes corresponding to the standard pattern data (1 to n) stored in.

FIG. 7 is a circuit diagram showing in detail the candidate selecting section 35 in FIG. The output of the minimum distance memory 27 is input to the minimum value selection unit 35-1. Minimum value selection unit 35-
The first output of No. 1 is connected to the input of the candidate memory 35-2, and the second output is output as the decision signal at the time of the post-DP calculation 35.
-3. An address counter 35 that counts a signal from the control 27 is input to the address of the candidate memory 35-2.
-4 output is added. The output of the candidate memory 35-2 is added to the first input of the latch 35-5 and the comparison circuit 35-6, and the first input of the selection circuit 35-7. Latch 35-5
Is connected to the input of the comparison circuit 35-8, the second input of the comparison circuit 35-6, and the second input of the selection circuit 35-7. The comparison output of the comparison circuit 35-6 is input to the selection circuit 35-7 and added to the control unit 24. Further, the decision output is input to the control unit 24 as a decision in the candidate selection processing 14 and is output as a decision 35-3 '. The output of the selection circuit 35-7 is input to the candidate number memory 36. The comparison circuits 35-8, 35-6 and the selection circuit 35-7 have the first to
The data of the third specific values Drej, Ddec, and D _DP are added, respectively.

The signal B applied to the address counter 35-4, the minimum value selection section 35-1, the control signal B'in the selection circuit 35-7 and the above-mentioned first to third specific values Drej and Dd.
The data of ec and D _DP are data added by the control unit 24. The minimum value selection unit 35-1 compares the minimum distance data sequentially input from the minimum distance memory 27 with the magnitude relationship between the data stored in the candidate memory 35-2. The candidate memory 35-2 is a memory for storing the smallest value of the minimum distance data to the fifth value. Then, the stored value and the input data are set to the minimum value selection unit 3
5-1 compares in ascending order, and if the data input from the minimum distance memory 27 is the data of the corresponding rank, the data and its candidate number are stored in the position of the corresponding rank,
The data of the subsequent ranks are sequentially shifted. That is,
For example, B ₂ , B ₇ , B ₁ , B ₈ , and B ₄ are smaller than the minimum distance data of the standard pattern, and the minimum distance data B ₉ of the standard pattern input from the minimum distance memory 27 is B ₁ if ranked third rather than smaller
Store B ₉ in the position of, and shift B ₁ and B ₈ thereafter. That is, as a result, B ₂ , B ₇ , B ₉ , B ₁ , B
₈ In this way, by performing the size comparison processing on the minimum distance data for all the standard pattern data, the smallest distance data is numbered 5 (D).
The values (1) to D (5)) and their numbers are the candidate memory 3
It is stored in 5-2. That is, the first to fifth candidates are unconditionally selected and stored. Control of these operations is performed by control signals B and B'input from the control unit 24.

Next, the minimum distance data of the minimum value, that is, the first
Candidate D (1) is output from the candidate memory 35-2 and stored in the latch circuit 35-5. Then, the comparison circuit 35-
8 and the first candidate is the first specific value Drej described above.
(Step 14-2 in FIG. 3). First candidate D
When (1) is equal to or larger than the first specific value Drej, an invalidation signal is output to the control unit 24 and is determined to be invalid. Further, when the value of the first candidate is smaller than the first specific value, a valid signal is output to the control unit 24, so that step 14 in FIG.
As indicated by -3, the address counter 35-4 is incremented by the control signal B of the control unit 24 and the candidate memory 3 in which the minimum distance data D (2) of the second candidate is stored.
5-2 is accessed, and the minimum distance data D (2) of the second candidate from the candidate memory 35-2 is stored in the first comparison circuit 35-6.
Join the input of. The comparison circuit 35-6 is step 1 in FIG.
As shown in 4-3, this is a circuit for determining the difference between the data applied to the first input and the data applied to the second input, and determining whether or not the difference is smaller than the second specific value Ddec. It operates by the output of the comparison circuit 35-8. That is, the latch 35 described above is connected to the second input of the comparison circuit 35-6.
Since the first candidate data D (1) stored in -5 is added, the difference is obtained and compared with the second specific value Ddec. As a result, when the difference value is greater than or equal to the second specific value Ddec, the determination signal and the determination number are output to the control unit 24 as a standard pattern intended for the first candidate (step 14-3 in FIG. 3). At this time, the selection circuit 35-7 does not operate. On the contrary to the above, when the difference value is smaller than the second specific value Ddec, there is a possibility that another candidate exists in addition to the first candidate, and therefore the operation signal for selecting them is selected. Output to the circuit 35-7. Selection circuit 35
-7 is a circuit for performing selection as shown in step 14-4 of FIG. 3, which determines whether or not the difference value between the first input and the second input is larger than the third specific value D _DP . It is a circuit that selects the second to fifth candidates. The first to fifth candidates are selected in the minimum value selection unit 35-1, but the difference from the first candidate data is not obtained in the selection in the minimum value selection unit 35-1. . The selection circuit determines this difference and determines whether or not the difference is smaller than the third specific value D _DP . That is, the signal D applied to the first input
The difference between (n) and the signal D (1) applied to the second input is obtained, and if the difference value is smaller than the third specific value D _DP , the candidate number is output to the candidate number memory 36. When the operation start signal of the selection circuit 35-7 is input from the comparison circuit 35-6, the selection circuit starts the above operation.

The operation of this circuit starts when the third candidate data is input to the first input, and the candidate numbers of the first and second candidates do not exist before the operation starts. The conditions are sequentially output to the candidate number memory via the selection circuit 35-7. That is, D (2)-in the comparison circuit 35-6.
When it is determined that D (1) <Ddec (step 1 in FIG. 3).
4-3), and outputs the first and second candidate numbers to the candidate number memory respectively. The selection circuit repeats the above-described discrimination operation sequentially from the third candidate data, and when the difference becomes larger than the third specific value D _DP , the candidate number is not output to the candidate number memory 36. Up to five candidate numbers are stored in the candidate number memory 36, but the number changes from 2 to 5 depending on the discriminating operation of the selection circuit.

Although the voice recognition device is used in the above-described embodiment of the present invention, the invention is not limited to this. For example, a character recognition device or the like can be applied as long as it recognizes a pattern.

[0052]

As described above, according to the present invention, the DP operation is performed in two stages, the former stage is a process for selecting a candidate, and the latter stage is a process from candidates obtained by the former stage with high accuracy. This is a process of detecting a target pattern. The former stage does not process all data, but performs distance calculation once for, for example, three measurement points, so that the processing speed is fast and a large amount of work memory is not required.
Similarly, in the latter stage, D only for a specific number of candidates
Since the P operation is performed, much memory is not required and the processing time is short.

According to the present invention, the target standard pattern is determined according to the result of the preceding DP matching, or 2
Since ~ 5 candidates are selected and the post-stage DP operation is performed, the average processing time is shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention using a processor.

FIG. 2 is a flowchart illustrating a DP calculation process.

FIG. 3 is a flowchart showing the candidate selection processing 14 of the embodiment of the present invention in more detail.

FIG. 4 is a circuit configuration diagram of a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a timing control unit.

FIG. 6 is a timing chart of a timing controller.

FIG. 7 is a detailed circuit diagram of a candidate selection unit 35 according to the embodiment of this invention.

[Explanation of symbols]

 1 Microphone 2 AGC circuit 3 BPF circuit 4,18 A / D converter 6 Processor 8 Read only memory 9 Random access memory 10 Input / output control system 13 First stage DP calculation 14 Candidate selection process 15 Second stage DP calculation 19 Parameter normalization compression unit 20 Input Pattern memory 21 Level detection unit 22 Timing control unit 23 Frame counter 24 Control unit 25 Standard pattern memory 26 Work area memory 27 Minimum distance memory 28 Distance calculation unit 29 Partial sum calculation unit 30 Minimum distance calculation unit 31 Standard pattern frame length memory 32, 33 gate circuit 34 frame number correction unit 35 candidate selection unit 36 candidate number memory 50, 51 counter 35-1 minimum value selection unit 35-2 candidate memory 35-4 address counter 35-5 latch 35 6,35-8 comparison circuit 35-7 selection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazumasa Fukushima 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (72) Masao Ninomiya Hamura-cho, Nishitama-gun, Tokyo 3-2-1 Sakaemachi Casio Computer Co., Ltd. in Hamura Technical Center (72) Inventor Kazuyuki Kurosawa 3-2-1 Sakaemachi Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. within Hamura Technical Center (56) References 56-101199 (JP, A)

Claims (1)

[Claims] 1. A pattern recognition device for determining a recognition result by performing pattern matching between input pattern data and standard pattern data stored in advance, wherein a plurality of candidates are subjected to a primary DP matching process for the input pattern data. Candidate selection means for selecting the standard pattern data and selecting as the first candidate or the second candidate from those judged to have higher similarity than the standard pattern data, and the distance between the first candidate and the input pattern data. Is determined to be unrecognizable when it is determined to be greater than or equal to a first specific value, and means for notifying the unrecognizable state; and in the case where it is not determined to be unrecognizable by the means, the first candidate and the first candidate Means for determining the first candidate as a recognition result when it is determined that the distance to the second candidate is equal to or greater than a second specific value, and the recognition result is determined by the means. And a means for determining a recognition result by a secondary DP matching process from among the plurality of candidate standard pattern data selected by the candidate selecting means, the primary D
A pattern recognition apparatus, wherein the P matching process is performed with a coarser accuracy than the secondary matching process.