JPH066548A - Access controller for page memory - Google Patents

Abstract

(57) [Abstract] [Purpose] Each line of image data can be effectively accessed, and each data line on the page memory can be surely accessed, by writing each line data of the image data to the page memory in a narrowed manner. Make sure that the cost does not increase significantly. [Structure] B4 size page memory 5 consisting of 2 ¹¹ pixels per line has 2 ⁶ pixels per line. × 3 ² When A4 size image data consisting of a number of pieces is stored in the tail, and this is accessed and read from 80 lines in the image data, numerical values 2 ¹¹ and 1 satisfying 2 ¹⁰ <80 <2 ¹¹
Number of pixels per line 2 ⁶ × 3 ² The least common multiple of and is 559
26 = 2 ⁶ × 2 ⁵ × 3 ² And this is A4 size 1
Number of memory pixels per line 2 ⁶ × 3 ² Divide by 32 = 2
^Five Then, the numerical value 65 (= 1 + 32 × 2) is obtained using this, and the access is actually performed from the head of the 65th line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page memory access control device suitable for a facsimile page memory and the like.
In particular, the present invention relates to an access control device for a page memory, which is capable of immediately accessing an arbitrary line of image data with a simple circuit configuration while effectively using a memory space.

[0002]

2. Description of the Related Art An example of a conventional page memory access control device is shown in FIG. In the figure, 1 is a memory access control unit, 2 is a read counter, 3 is a write counter, 4 is a multiplexer, and 5 is a page memory.

As shown in FIG. 5, a B4 size memory having 2048 pixels per line is used as the page memory 5, and the image data to be written in this page memory is per line. A4 size data of 1728 pixels is shown.

According to such a conventional apparatus, since the head address (lower) of each line of the image data stored in the page memory 5 is 00H, there is an advantage that the address management is easy.

However, in such a conventional access control device, since the data of each line of the image data is written from the head address of the corresponding line of the page memory, it is larger than A4 size 1729-.
There is a problem that the page memory for 2048 pixels is left unused and the page memory is not effectively used for that amount.

In order to solve such a problem, for example, as shown in FIG. 3, when A4 size data is written in the page memory while being justified, the pixels for one line of data are used to manage each line. A multiplier for obtaining a number × m (m = 0, 1, 2, ...), a memory for storing the start address of each line, and a circuit for controlling these are separately required, which leads to cost increase. However, a new problem arises that their management becomes complicated.

[0007]

As described above, in the conventional access control apparatus, since the data of each line of the image data is written from the head address of the corresponding line of the page memory, A4 is used. Larger than size 1
There is a problem that the page memory for 729 to 2048 pixels is left unused and the page memory is not effectively used for that amount. To solve such a problem, for example, as shown in FIG. When data of A4 size is written in the page memory while being left-justified, the number of pixels for one line of data × m (m = 0, 1, 2) is used to manage each line.
...), a memory for storing the start address of each line, and a circuit for controlling these are separately required, which leads to cost increase and management becomes complicated. was there.

The present invention eliminates the above-mentioned problems, writes the line data of the image data in the page memory by trimming the line data, and effectively uses the page memory, while ensuring each data line on the page memory. An object of the present invention is to provide an access control device for a page memory which can be accessed and which does not cause a significant increase in cost.

[0009]

According to the invention of claim 1 of this application, the number of pixels per line is 2 ^n. Number of pixels per line X (X <2 ⁿ ) In the page memory access control device for storing the image data consisting of a number of pieces of data in the tail, and accessing and reading the image data from an arbitrary line number L in the image data, 2 ^n-1 <Number of pixels per line X <2 ⁿ Numerical value 2 ⁿ And the number of pixels per line X, the first arithmetic means for obtaining N (= M / X) from the least common multiple M, 1 + N (K) ≦ line number L <1 + N (K + 1) for which access is requested Numerical value 1+
The second numerical calculation means (provided that K = 0, 1, 2, ...) Is used to obtain N (K) or 1 + N (K + 1), and the numerical value 1 is set.
The image data is read from the page memory with + N (K) or 1 + N (K + 1) as an access start address.

The invention according to claim 2 of this application is the same as the invention according to claim 1, in which the numerical value is 1 + M (K) or 1+.
Among M (K + 1), the one near the line number L for which the access is requested is used as the access start address.

[0011]

According to the structure of the present invention, line management can be performed with a simple circuit structure including only a latch and a multiplexer, and even if data is written in the page memory in a narrow manner, reading from almost any line is possible. Easy to do,
The page memory can be effectively used.

[0012]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. An embodiment of the page memory access control circuit according to the present invention is shown in FIG. In FIG. 1, 1 is a memory access control unit, 2 is a read counter, 3 is a write counter, 4 is a multiplexer, 5 is a page memory, 6 is a bus, and 7 is a least common multiple control unit.

An example of the least common multiple control circuit is shown in FIG.
As shown in the figure, this access control device latches the upper 6 bits A11 to A6 of the address data A11 to A0 in response to the latch signal LATCH and directly stores the higher 6 bits A11 'to page memory address data. A
The upper latch 8a which outputs 6'and the lower 6 bits A5 to A0 of the address data A11 to A0 are latched in response to the latch signal LATCH, and among them, A5 is directly output as A5 'of the page memory address data and the lower 5 For bits A4 to A0, the lower side latch 8b is appropriately sent to two multiplexers 4a and 4b, which will be described later, and when the content of the paper size designation signal is B4 size, the address data A4 is the other A4 size. Is a first multiplexer 4a which outputs "0" as A4 'of page memory address data in response to the strobe signal STB, and A3 to A0 of address data when the content of the paper size designation signal is B4 size. On the other hand, in the case of A4 size, "(0) (0) (0) (1)" is set to A3 'of page memory address data. Strobe signal ST as A0'
And a second multiplexer 4b which outputs in response to B.

Therefore, the least common multiple control circuit 7 is
When the content of the paper size designation signal is B4 size, the address data A11 to A0 are output as the page memory address data A11 'to A0' as they are, whereas when the content of the paper size designation signal is A4 size The address data A11 to A0 are set to “(A11) (A10) (A9)
(A8) (A7) (A6) (A5) (A4) (0)
After being converted into (0) (0) (1) ", it is output as page memory address data A11 'to A0'.

Next, the operation of the access control device having the above configuration will be described. A4 size (1728 = 2 ⁶ pixels) in B4 size (2048 = 2 ¹¹ pixels) memory space × 3 ²
When the data of the number of pixels) is written to the bottom, it becomes as shown in FIG.

Here, regarding the number of pixels 1728 per line for A4 size data, 2 ¹⁰ <1728
<2 ¹¹ holds, and the least common multiple of 2 ¹¹ and 1728 is 55926 = 2 ⁶ × 2 ⁵ × 3 ² When this is divided by the number of memory pixels 1728 of A4 size per line, 32 = 2 ⁵ Is obtained, which indicates that the lower bit of the start address of the line becomes 00H for every 32 lines of data.

From this, the read access of an arbitrary line is 1 + 32K by the least common multiple control circuit 7.
By converting to (K = 0, 1, 2, ...) Lines, read access from almost any line can be made possible.

Explaining with a concrete example with reference to FIG. 2, tentatively, A4 size data is written from the top of the page memory to the bottom, and a read access request from 80 lines is made in this state. Suppose that.

When 80 is represented by a binary number, 0000 0101
0000 (2) (A11 to A0), and since the image data is A4 size, the selectors of the multiplexers 4a and 4b select the A side, so the address data A4 to A0 are A4.
Is converted to A1 = 0 and A0 = 1. That is, 000
0 0100 0001 (2) (A11 to A0) is 10
Access is from the 65 (= 1 + 32 × 2) line in radix. Similarly, when a read access is made from 100 lines, 100 is expressed in binary as 0000 01.
Since it becomes 100100 (2), 00000110
It is converted into 0001 (2) = 97 (= 1 + 32 × 3).

According to the apparatus of the above embodiment, line management can be performed with a simple configuration of only a latch and a multiplexer. Therefore, even if data is written to the page memory in a tight manner, reading from almost any line can be easily performed, and the page can be easily read. The memory can be effectively used.

In the present invention, since the management is performed in units of a plurality of lines (32 lines in the above-mentioned example), the unit interest is somewhat rough, but even if the line density is 7.7 lines / mm, it is possible to read from any read position. The maximum deviation is about 4 mm, so it is not a big problem. Incidentally, as an application example of the present invention, when it is necessary to separately print the received image information on two sheets of paper, it may be used when the end of the first page and the beginning of the second page are overlapped. In such a case, it seems that the accuracy of the overlap is about 4 mm (maximum) and it does not matter so much.

Further, in the above embodiment, since the relationship of 1 + 32K ≦ read access request line <1 + 32 (K + 1) (here, K = 1, 2 ...) Is established in the least common multiple control circuit, the read access line is 1 + 32K. However, the read request line may be changed to 1 + 32K or 1 + 3 instead of 1 + 32 (K + 1).
By converting to a smaller difference of 2 (K + 1), the maximum deviation can be 2.08 mm, which is half of the above case.

[0023]

As described above, according to the present invention,
For example, line management can be performed with a simple circuit configuration including only a latch and a multiplexer, and even if data is tightly written in the page memory, reading can be easily performed from almost any line, and the page memory can be effectively used. Can be utilized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an access control device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a least common multiple control unit.

FIG. 3 is a diagram showing the contents of a page memory in which image data is written according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a conventional access control device.

FIG. 5 is a diagram showing the contents of a page memory in which image data is written by a conventional device.

[Explanation of symbols]

 1 Memory Access Control Unit 2 Read Counter 3 Write Counter 4 Multiplexer 5 Page Memory 6 Bus 7 Least Common Multiple Control Unit

Claims (2)

[Claims] 1. Number of pixels per line 2 ⁿ Number of pixels per line X (X <2 ⁿ ) In the page memory access control device for storing the image data consisting of a number of pieces of data in the tail, and accessing and reading the image data from an arbitrary line number L in the image data, 2 ^n-1 <Number of pixels per line X <2 ⁿ Numerical value 2 ⁿ And the least common multiple M to N of the number of pixels per line X
First calculation means for obtaining (= M / X), and 1 + N (K) ≦ line number L <1 for which an access request is made.
Numerical value 1 + N (K) or 1 that satisfies + N (K + 1)
Second calculation means for obtaining + N (K + 1) (where K =
0, 1, 2, ...) and reading image data from the page memory with the numerical value 1 + N (K) or 1 + N (K + 1) as an access start address. 2. The numerical value 1 + N (K) or 1 + N (K +
2. The page memory access control device according to claim 1, wherein, in 1), an access start address is closer to a line number L for which an access request is made.