JPH0666119B2 - Sample hold circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit suitable for application to a signal having a blanking period at every predetermined cycle such as a video signal.

Background Art and its Problems For example, as a circuit for sampling and holding a video signal, there is a circuit as shown in FIG. In the figure, the signal supplied to the input terminal (1) is supplied to the gate MOS transistor (2), and this transistor (2) is turned on by the sampling pulse φs from the terminal (3). The signal from the transistor (2) is supplied to the holding capacitor (4). The signal from the capacitor (4) is supplied to the gate of the buffer MOS transistor (5). The drain of the transistor (5) is supplied with the power supply V _CC from the power supply terminal (6), and the source is grounded through the constant current source (7). Then, the signal obtained at the source of the transistor (5) is taken out at the output terminal (8).

However, in this circuit, a buffer circuit using a source follower is provided at the output stage. For this reason, the signal of each part becomes as shown in FIG. 2, for example, and V _GS is reduced in the output as shown by the following equation.

Here, Vth is the threshold value of the transistor (5), μ is the mobility, Cox is the gate capacitance per unit area, W is the channel width, L is the channel length, and Io is the current value of the constant current source (7).

Therefore, DC potential fluctuation between input and output due to Vth variation, Io drift, etc. The problem of noise arises.

Also, when a large number of sample-hold circuits are connected in series, V _GS is reduced in each stage, so that the final output causes a large DC change with the input.

SUMMARY OF THE INVENTION In view of the above points, the present invention aims to prevent a decrease in V _GS between input and output.

SUMMARY OF THE INVENTION According to the present invention, an input signal from an input terminal (1) is sampled through a gate circuit (2) driven by a clock signal φs, held by a holding means (4), and a buffer circuit of an emitter follower or a source follower. In the sample hold circuit configured to output via (5), a capacitor (11) is provided between the holding means and the base or gate of the buffer circuit, and the output side of the buffer circuit is connected to the first switch means ( 12) is connected to the holding means side of the capacitor, the input terminal is connected to the buffer circuit side of the capacitor via the second switch means (13), and the first and second switch means are connected. are turned on during a period phi _BLK is not performed the sampling, the base-emitter voltage or gate-source of the buffer circuit to the capacitor Is charged with a voltage V _GS, a sample and hold circuit, characterized in that to obtain an output voltage of said holding means side and the same potential, between the input and the output, according to this
No decrease in V _GS will occur.

Embodiment In FIG. 3, a capacitor (11) is provided between the connection point between the transistor (2) and the capacitor (4) and the gate of the transistor (5). The source of the transistor (5) and the capacitor (4) of the capacitor (11)
A switching transistor (12) is provided between the switch and the side. Further, a switching transistor (13) is provided between the input terminal (1) and the gate side of the transistor (5) of the capacitor (11). Others are the same as in FIG.

A pulse φ _BLK corresponding to the blanking period of the input signal from the terminal (14) is supplied to the gates of the transistors (12) and (13).

In this circuit, the signal of each part is as shown in FIG. 4, for example.

That is, when the voltage at the input terminals (1) and () is V _SO ,
When the pulse φ _BLK is supplied, the transistors (12), (1
3) is turned on, the potential of the gate () of the transistor (5) is V _SO , and the potential of the source () is the transistor (5).
Is reduced by V _GS to V _SO −V _GS , and the potential of the connection point () between the transistor (2) and the capacitor (4) is V
Become _SO- V _GS . Therefore, at this time, an electric charge corresponding to the potential difference V _SO − (V _SO −V _GS ) = V _GS is stored in the capacitor (11).

In this state, the transistors (12) and (13) are turned off and the sampling pulse φs is supplied. Then, assuming that the potential when the _first pulse φs ₁ is applied is Vs ₁ , the potential of also becomes Vs ₁ . There is a capacitor (11) between and and this capacitor (11) has V _GS
Since the electric charge corresponding to is accumulated, the potential of is V _S1
It becomes + V _GS . Therefore, the potential becomes (V _S1 + V _GS ) −V _GS = V _{S1 and} becomes equal to the potential of the input terminals (1) and ().

Similarly, when the potential of when the second pulse .phi.s ₂ was added and Vs _2, is of V _S2 + V _GS, the potential by the charge possessed by the potential Vs _2, the potential capacitor (11) (V _S2 + V _GS ) -V _GS = V _S2 , and the input and output potentials become equal.

This occurs at every sampling, and as a result, the sampled potential appears at the output as it is, and the V _GS does not decrease due to the buffer.

It should be noted that the timing (φ _BLK ) for accumulating the charge of V _{GS on} the capacitor (11) may be any period during which no sampling is performed, and may be performed between samplings or when the input signal is a video signal, for example. It may be performed in a blanking period or the like for each horizontal period.

Although the sample and hold is performed in this manner, this circuit can cancel the decrease in V _GS due to the buffer such as the source follower, so that the change in the DC potential between the input and the output can be eliminated. In addition, V _GS variations and temperature drift, which are especially problematic for MOS transistors, It is possible to suppress the influence of noise and the like.

Further, FIG. 5 shows an example of the concrete circuit of FIG. In the figure, the transistor (21) is It is turned on by the pulse of, and is for neutralizing the jump of the pulse φs via the gate-drain capacitance of the transistor (2).

In the figure, the capacitor (11) is a MOS transistor (2
The capacitor (3) is formed between the source and drain and the gate, and the capacitor (4) is formed between the source and drain and the substrate. In this case, the transistor (23) is composed of an enhancement type if the source follower transistor (5) is an enhancement type and a depletion type if the source follower is a depletion type.

Furthermore, the stray capacitance at the point must be minimized. Therefore, as the transistors (5) and (12), asymmetric MOS transistors having a small gate-drain capacitance are used.

When the circuit has a well structure, the source of the transistor (5) is connected to the substrate.

Note that the capacitor (11) may be a capacitance of another type instead of the MOS transistor.

Further, the above-mentioned circuit has been described in the case of the MOS transistor, but it can be applied to the bipolar transistor.
That is, FIG. 6 shows a circuit for that purpose. In the bipolar transistor, a current source (25) is provided at the base of the transistor (5) in order to compensate the base current I _B.

Application Example FIG. 7 shows an example of a delay circuit in which the above-described sample and hold circuits are connected in two stages. In this example, the circuit of FIG. 3 is connected in two stages, and the reduction of V _GS is canceled at each stage. Figure 8 shows the timing of φ _BLK and φ _S1 , φ _S2 .

Also, FIG. 9 shows an example of a delay circuit in which sample and hold circuits are connected in two stages. In this example, a capacitor (11) is provided only in the first stage, and the output of the last stage is connected via a transistor (12) to a capacitor ( Return to the input side of 11).
In this circuit, the sampling pulse φ _S2 is made high even when φ _BLK is high as shown in FIG. As a result, the capacitor (11) accumulates the decrease due to V _{GS in} both the first-stage and last-stage buffer circuits, and equalizes the potential between the input and output.

As shown in FIG. 7 or FIG. 9, more stages can be connected.

Further, FIG. 11 shows an example of a synchronizing circuit using the sample-hold circuit of the two-stage connection described above. FIG. 12 is a diagram showing the operation. In the figure, the signals continuously supplied to the input terminal (31) are φ _S1 , φ _S2 , and φ _S3.
1 ), (32 ₂ ) and (32 ₃ ) are sequentially sampled and held,
Furthermore, with φ _S3 , the final stage hold circuit (33 ₁ ), (33 ₂ ),
It is synchronized with (33 ₃ ), sampled and held, and output to output terminals (34 ₁ ), (34 ₂ ), and (34 ₃ ).

In this circuit, in the case of using the conventional sample hold circuit due to variations in V _GS, the output terminal (34 _1),
Although a DC change was generated in the signals of (34 ₂ ) and (34 ₃ ), the DC change can be eliminated by using the sample hold circuit of the present invention described above.

EFFECTS OF THE INVENTION According to the present invention, it is possible to prevent a decrease in V _GS between input and output in the sample hold circuit.

[Brief description of drawings]

1 and 2 are diagrams for explaining a conventional circuit, FIG. 3 is a configuration diagram of an example of the present invention, FIGS. 4 and 5 are diagrams for explaining the same, and FIG. 6 is another diagram. FIG. 7 to FIG. 12 are diagrams for explaining an application example. (2) is a gate transistor, (4) is a holding capacitor, (5) is a buffer transistor, (11) is a capacitor, and (12) and (13) are switch transistors.

Claims (1)

[Claims] 1. A sample-hold circuit in which an input signal from an input terminal is sampled through a gate circuit driven by a clock signal, held by a holding means, and output through a buffer circuit of an emitter follower or a source follower. A capacitor is provided between the holding means and the base or gate of the buffer circuit, the output side of the buffer circuit is connected to the holding means side of the capacitor through the first switch means, and the input terminal is connected to the second side. Is connected to the buffer circuit side of the capacitor via the switch means, and the first and second switch means are turned on during the period in which the sampling is not performed, and the capacitor is connected to the base-emitter voltage of the buffer circuit or Charge the gate-source voltage to obtain an output voltage of the same potential as the holding means Sample-and-hold circuit, characterized in that there was Unishi.