JPH0617280Y2 - Sample-hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a sample and hold circuit suitable for application to a signal having a blanking period at every predetermined period such as a video signal, and particularly to a source follower or the like. This is to obtain an output signal which does not cause a difference in offset voltage between the gate and the source caused by the buffer.

[Outline of device]

This invention, for example, in a sample-hold circuit using a MOS transistor, in order to cancel the offset voltage between the gate and the source, which is generated by a buffer such as a source follower in the output stage, charges corresponding to the offset voltage are applied to the capacitor during the blanking period. By accumulating,
The output voltage is prevented from having an offset voltage difference with respect to the input voltage.

[Conventional technology]

For example, a circuit as shown in FIG. 8 is known as a circuit for sampling and holding a video signal. Input terminal 101
The signal supplied to the gate is the MOS transistor 10 for gate.
8 are supplied. This MOS transistor 108 is turned on by a sampling pulse from the terminal 103. This M
The signal from the OS transistor 108 is supplied to the holding capacitor 111. The signal from the capacitor 111 is supplied to the gate of the buffer MOS transistor 109. A power supply voltage from the power supply terminal 105 is supplied to the drain of the MOS transistor 109, and the source is grounded through the constant current source 113. And this MOS
The signal obtained at the source of the transistor 109 is taken out at the output terminal 106.

However, in this circuit, a buffer circuit using a source follower is provided at the output stage. Therefore, when the sampling pulse shown in FIG. 9B is supplied from the terminal 103, the signals of the respective parts become those shown in FIG. 9A, for example. In FIG. 9A, the waveform indicated by the solid line is the input terminal 10
The input voltage supplied to 1 (point), the waveform indicated by the one-dot chain line is the voltage of the gate (point) of the MOS transistor 109, and the waveform indicated by the broken line is the output voltage generated at the output terminal 106 (point). As is clear from FIG. 9A,
V _GS (offset voltage) as shown in the following formula
Will be reduced.

Here, V _th is a threshold voltage of the MOS transistor 109, μ is mobility, C _0X is a gate capacitance per unit area, W is a channel width, L is a channel length, and I ₀ is a current value of the constant current source 113. .

Therefore, there arise problems of variations in V _th , fluctuations in DC potential between input and output due to drift of I ₀ , and so-called 1 / f noise.

Further, when the sample-hold circuits are connected in series in multiple stages, V _GS is reduced in each stage, so that the final output causes a large direct current change with the input.

For this reason, the applicant has previously proposed a circuit as shown in FIG. In FIG. 10, 121 is an input terminal, 123 is a terminal to which a blanking pulse φ _BLK is supplied, and 124 is a sampling pulse φ _S.
Is a terminal to be supplied.

The drain of the gate MOS transistor indicated by 127 is connected to the input terminal 121, and the MOS transistor 12
The gate of 7 is connected to terminal 124. The source of the MOS transistor 127 is connected to the gate of the output enhancement type MOS transistor 129 via the capacitor 131, grounded via the capacitor 132, and further connected to the drain of the gate MOS transistor 130. MOS transistor 1 for gate
The drain of 28 is connected to the input terminal 121, the gate of the MOS transistor 128 is connected to the terminal 123, and M
The source of the OS transistor 128 is the transistor 129.
Connected to the gate. The gate of the gate MOS transistor 130 is connected to the terminal 123, and the source thereof is the output enhanced-men type MOS transistor 129.
Connected to the source of. The drain of the output enhancement type MOS transistor 129 is the power supply terminal 125.
The constant current source 133 is connected to its source, and its source is led out as the output terminal 126.

In the sample hold circuit shown in FIG.
The blanking pulse φ _BLK shown in FIG.
3 and the sampling pulse φ shown in FIG. 11C.
_{When S} is supplied to the terminal 124, the signal of each part becomes as shown in FIG. 11A, for example. In FIG. 11A,
The solid line is the input voltage supplied to the input terminal 121, and the broken line is the output voltage generated at the output terminal 126.

That is, when the blanking pulse φ _BLK is supplied when the voltage of the input terminal 121 is V _S0 , the transistors 128, 1
30 is turned on, the potential of the gate of the MOS transistor 129 is V _S0 , and the potential of the source (output terminal 126) is MOS.
The transistor 129 lowers V _GS to V _S0 -V _GS , and the potential at the connection point between the MOS transistor 130 and the capacitor 132 becomes V _S0 -V _GS . Therefore, at this time, the electric charge corresponding to the potential difference V _S0 − (V _S0 −V _GS ) = V _GS between the gate potential of the MOS transistor 129 and the source potential of the MOS transistor 129 is accumulated in the capacitor 131.

In this state, the MOS transistors 128 and 130 are turned off, and the sampling pulse φ _S is supplied. And first, the input terminal 12 when the first pulse φ _S1 is applied
When the first potential and V _S1, the potential at the connection point between the transistor 127 and the capacitor 132 also becomes V _S1. Here, since the electric charge corresponding to V _GS is accumulated in the capacitor 131 by the blanking pulse φ _BLK , the capacitor 13
The potential at the connection point between 1 and the transistor 129 becomes V _S1 + V _GS . Therefore, the potential of the output terminal 126 becomes (V _S1 + V _GS ) −V _GS = V _S1 , which is equal to the potential of the input terminal 121.

This occurs at every sampling, and as a result the sampled potential appears at the output as it is without the buffer decreasing V _GS .

[Problems to be solved by the invention]

However, in the sample hold circuit shown in FIG. 10 described above, since the enhancement type MOS transistor 129 is used in the output stage, the level of the input signal is
At a minimum, the threshold voltage V _{th of} the MOS transistor 129 or higher is required. Therefore, the dynamic range of the circuit is required to have a dynamic range D _{1 which} is larger than the original signal dynamic range (for example, D ₀ ) by the offset voltage V _GS .

In addition, due to the Early effect, the MOS changes as the operating point changes.
The change in the offset voltage V _GS of the transistor 129 occurs. Accordingly, blanking and V _GS of the ranking period is held in the capacitor 131, there is a problem that a difference occurs in the V _GS of the actual MOS transistor 129 when the non-blanking period.

Therefore, the object of the present invention is to accurately cancel the V _GS (offset voltage between the gate and the source) of the output stage and to obtain the output voltage without _causing a voltage difference of V _GS with respect to the input voltage. Another object is to provide a sample hold circuit that can reduce the dynamic range.

[Means for solving problems]

According to this invention, an input signal is supplied to one end of a first capacitor 12 via a first gate element 7, the other end of the first capacitor 12 is AC grounded, and one end of the first capacitor 12 is grounded. The gate (or base) of the source (or emitter) follower transistor 9 via the second capacitor 11
And the output is obtained from the source (or emitter) of the transistor 9, and the source (or emitter) is connected to one end of the first capacitor 12 via the second gate element 10, and the gate of the transistor 9 (or 3rd base)
Is connected to a direct current voltage source having a predetermined voltage value via the gate element 8 of FIG. 1 to turn on the second and third gate elements 8 and 10 for the first period of the input signal, and the second capacitor 11 is connected to the transistor. A voltage corresponding to the gate-source (or base-emitter) offset voltage of 9 is accumulated, the first gate element 7 is turned on in the second period of the input signal, and a signal having the same level as the input signal is obtained at the output. This is a sample and hold circuit.

[Action]

A bias voltage V _B is supplied to the drain of the MOS transistor 8 via the terminal 2, and the blanking pulse φ _{BLK is applied} to the MOS transistor 8 during the blanking period of the input signal.
And 10 are turned on, and the capacitor 11 is connected to the output stage MO.
A charge corresponding to the offset voltage V _GS of the S transistor 9 is accumulated. When the MOS transistor 7 is turned on by the sampling pulse φ _S and the input voltage is held in the capacitor 12, the held input voltage and the voltage corresponding to V _{GS held} in the capacitor 11 are added and the MOS transistor 9 in the output stage is added. Is supplied to the gate. The voltage output from the source of the MOS transistor 9 is equal to the input voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.
In FIG. 1, reference numeral 1 is an input terminal to which a video signal is supplied, for example.

The drain of the gate MOS transistor 7 is connected to the input terminal 1, and its gate is connected to the terminal 4 to which the sampling pulse φ _S is supplied. MOS transistor 7
Is connected to the gate of the output enhancement type MOS transistor 9 via the capacitor 11, the connection point between the source of the MOS transistor 7 and the capacitor 11 is grounded via the capacitor 12, and
It is connected to the drain of the gate MOS transistor 10.

The drain of the gate MOS transistor 8 is connected to the terminal 2 to which the bias voltage V _B is supplied, and its gate is connected to the terminal 3 to which the blanking pulse φ _BLK is supplied. The source of the MOS transistor 8 is connected to the gate of the output MOS transistor 9. The gate of the MOS transistor 10 for gate is connected to the terminal 3 to which the blanking pulse φ _BLK is supplied, and its source is connected to the source of the MOS transistor 9.

The drain of the output MOS transistor 9 is the power supply terminal 5
The constant current source 13 is connected to the source, and the output terminal 6 is derived from the source.

The terminal 2 is supplied with a predetermined bias voltage V _{B which} is an almost average level of the input signal, and the terminal 3 is supplied with the blanking pulse φ _BLK shown in FIG. Is supplied with the sampling pulse φ _S shown in FIG. 2C.

In this circuit, the signal of each part is as shown in FIG. 2A, for example.

That is, when the blanking pulse φ _BLK is supplied, the transistors 8 and 10 are turned on, and the potential of (the point of) the gate of the MOS transistor 9 is V _B , the source as shown by the one-dot chain line in FIG. 2A. The potential of (point) is shown in Fig. 2A.
As shown by the broken line in FIG. 5, V _{GS is} reduced by the MOS transistor 9 and V _B −V _GS causes the potential at the connection point (the point) between the MOS transistor 10 and the capacitor 12 to be V.
It becomes _B- V _GS . Therefore, at this time, the electric charge corresponding to the potential difference V _B − (V _B −V _GS ) = V _{GS from the} capacitor 11 is accumulated.

In this state, the MOS transistors 8 and 10 are turned off and the sampling pulse φ _S is supplied. First, _assuming that the potential of the input terminal 1 () when the first pulse φ _S1 is applied is V _S1 , the potential of V _S1 also becomes. Since the electric charge corresponding to V _GS is accumulated by the blanking pulse φ _{BLK in} the capacitor 11 between and, the potential of V _S1 + V _GS becomes. Therefore, the potential of is (V _S1 + V _GS ) −V _GS = V _S1 and is equal to the potential of the input terminal 1 ().

This occurs at every sampling, and as a result the sampled potential appears at the output as it is without the buffer decreasing V _GS .

When the embodiment of the present invention is used as a buffer circuit, for example, a pulse held at a high level is applied to the terminal 4 as shown in FIG. 3B for the input video signal shown in FIG. 3A. Supply. The MOS is generated by the blanking pulse shown in FIG. 3C every blanking period of the video signal.
The offset voltage V _GS of the transistor 9 is applied to the capacitor 11
It should be stored in.

FIG. 4 shows another embodiment in which the present invention is applied to an analog delay circuit. One embodiment shown in FIG.
Stages and cascade connection.

The first sample-hold circuit is constituted by the MOS transistors 27, 28, 30 for gates, the capacitors 31, 32, the MOS transistor 29 for output, and the constant current source 33 in the same manner as in the above-described embodiment. Also, M for gate
OS transistors 37, 38, 40, a capacitor 41,
42, output MOS transistor 39 and constant current source 4
The second sample and hold circuit is constituted by 3 as in the first embodiment.

In FIG. 4, the input terminal 21 is connected to the drain of the MOS transistor 27,
The gate of 7 is connected to the terminal 24 to which the first sampling pulse φ _S1 is supplied. The terminal 22 to which the bias voltage V _B is supplied is connected to the drain of the MOS transistor 28 and the drain of the MOS transistor 38. The terminal 23 to which the blanking pulse φ _BLK is supplied is connected to the gates of the MOS transistors 28, 30, 38 and 40. The source of the output MOS transistor 29 is a MOS
It is connected to the drain of the transistor 37. The gate of the MOS transistor 37 is the second sampling pulse φ _S2
Is connected to a terminal 34 to which is supplied. The power supply terminal 25 is connected to the drains of the output MOS transistors 29 and 39, and the output terminal 36 is derived from the source of the output MOS transistor 39.

The blanking pulse φ shown in FIG.
_BLK is supplied, and the offset voltage V of the output MOS transistors 29 and 39 is supplied to the capacitors 31 and 41, respectively.
_GS is accumulated. A sampling hold output of the input signal is generated from the source of the MOS transistor 29 by φ _S1 of the first sampling pulse shown in FIG. 5B. This sampling hold output is supplied to the drain of the MOS transistor 37, and as shown in FIG. 5C, the second sampling pulse φ _S2 delayed by a certain phase from the first sampling pulse φ _S1 is supplied to the terminal 34. The sampling hold output of the previous stage is sampled by this sampling pulse φ _S2 . Therefore, the sampling hold output delayed by the time of the phase delay between the first sampling pulse φ _S1 and the second sampling pulse φ _S2 is taken out to the output terminal 36.

FIG. 6 shows an embodiment in which the present invention is applied to an analog-serial / parallel conversion circuit, and it has a configuration in which two other embodiments of the present invention shown in FIG. 4 are connected in parallel.

MOS transistors 57, 58, 60, 6 for gates
7, 68, 70, capacitors 61, 62, 71, 72,
Output MOS transistors 59 and 69 and constant current source 6
3, 73 form a first delay circuit having the same configuration as in FIG. Also, the gate MOS transistor 7
7, 78, 80, 87, 88, 90, capacitor 81,
82, 91, 92, output MOS transistor 79,
89 and the constant current sources 83 and 93 form a second delay circuit having the same configuration as in FIG.

In FIG. 6, the input terminal indicated by 51 is connected to the drain of the MOS transistor 57 and the drain of the MOS transistor 77. The gate of the MOS transistor 57 is connected to the terminal 54 to which the first sampling pulse φ _S1 is supplied. The terminal 52 to which the bias voltage V _B is supplied is connected to the drain of the MOS transistor 58 and the drain of the MOS transistor 68.
The terminal 53 to which the blanking pulse φ _BLK is supplied is MO
It is connected to the respective gates of S transistors 58, 60, 68, 70. The power supply terminal 55 has the drain of the output MOS transistor 59 and the output MOS transistor 6
9 drain. The first output terminal 66 is derived from the source of the output MOS transistor 69.

74 is supplied with the second sampling pulse φ _{S2 and} is MO
It is connected to the respective gates of S transistors 67, 77 and 87. The terminal 76 to which the bias voltage V _B is supplied is MO
It is connected to the drain of the S transistor 78 and the drain of the MOS transistor 88. Blanking pulse φ
_The terminal 53 to which _BLK is supplied is a MOS transistor 78,
It is connected to the respective gates of 80, 88 and 90. The power supply terminal 75 is connected to the drain of the output MOS transistor 79 and the drain of the output MOS transistor 89. The second output terminal 86 is derived from the source of the output MOS transistor 89.

The blanking pulse φ shown in FIG.
_BLK is supplied, and the output MOS transistors 59, 69, 7 are supplied to the capacitors 61, 71, 81, 91, respectively.
An offset voltage V _{GS of} 9,89 is stored. Fig. 7B
A sampling hold output of the input signal (FIG. 7D) is generated from the source (point in FIG. 6) of the MOS transistor 59 by the first sampling pulse φ _S1 shown in FIG. This sampling hold output (Fig. 7E) is MO
It is supplied to the drain of the S transistor 67. As shown from the first sampling pulse phi _S1 in FIG. 7 C, and the second sampling pulses phi _S2 delayed predetermined phase is supplied to the terminal 74, the front stage of the sampling hold output by the sampling pulse phi _S2 (second 7E) is sampled. Therefore, the sampling hold output (FIG. 7G) delayed by the time of the phase delay between the first sampling pulse φ _S1 and the second sampling pulse φ _S2 is taken out to the output terminal 66.

Further, the input signal at this time is sampled by the sampling pulse φ _S2 , and the sampling hold output (7th
The source of the MOS transistor 79 (shown in FIG.
Occurs at points (in the figure). This sampling hold output (FIG. 7F) is taken out to the output terminal 86 via the MOS transistors 87 and 89. That is, as shown in FIGS. 7G and 7H, the input signals are parallelized and taken out from the output terminals 66 and 86.

Note that, unlike the above embodiment, a bipolar transistor may be used instead of the MOS transistor.

[Effect of the invention] This invention is held offset voltage V _GS of the MOS transistor of the output stage to the capacitor in the blanking period, and the offset voltage V _GS that is held in the input voltage and the capacitor is sampled and held by the sampling pulse Is added to the gate of the MOS transistor in the output stage. Therefore, the output voltage can be obtained without causing a difference in the offset voltage with respect to the input voltage.

Further, since the bias voltage V _B is supplied with a voltage at an almost average level of the input signal, the offset voltage sampled and held by the blanking pulse and the offset voltage when the input signal is sampled and held should be well matched. It is possible to reduce the dynamic range.

[Brief description of drawings]

FIG. 1 is a connection diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram used for explaining the operation of one embodiment of the present invention, and FIG. 3 is an explanation when one embodiment of the present invention is used for a buffer circuit. FIG. 4 is a connection diagram of another embodiment of the present invention, FIG. 5 is a waveform diagram used to explain the operation of another embodiment of the present invention, and FIG. 6 is still another embodiment of the present invention. Connection diagram of the embodiment,
FIG. 7 is a waveform diagram used for explaining the operation of still another embodiment of the present invention, FIGS. 8 and 10 are connection diagrams of a conventional sample hold circuit, and FIGS. 9 and 11 are conventional sample hold circuits. 3 is a waveform diagram used for explaining the operation of FIG. Description of main symbols in the drawings 1: Input terminal, 2: Bias voltage supply terminal, 3: Blanking pulse supply terminal, 4: Sampling pulse supply terminal, 5: Power supply terminal, 6: Output terminal, 7, 8 , 1
0: MOS transistor for gate, 9: MO for output
S transistors, 11, 12: capacitors, 13: constant current source.

Claims (1)

[Scope of utility model registration request] 1. An input terminal is connected to one end of a first transistor forming a gate circuit, the other end of the first transistor is connected to one end of a first capacitor, and the other end of the first capacitor is connected. Is grounded in an alternating current, and one end of the first capacitor is connected to the gate (or base) of the second transistor of the source follower (or the emitter follower) via the second capacitor, The output terminal is derived from the source (or emitter), and the source (or emitter) of the second transistor is connected to one end of the first capacitor and the second capacitor through a third transistor that forms a gate circuit. The gate circuit (or base) of the second transistor of the source follower (or emitter follower) is connected to the connection point with one end of the gate circuit. The first signal of the input signal input to the input terminal is connected to one end of a fourth transistor that constitutes the second input terminal, and the other end of the fourth transistor is connected to an input terminal of a DC voltage source having a predetermined voltage value. In the period of
A third transistor and a fourth transistor which form the gate circuit.
Is turned on, and a voltage corresponding to the gate-source (or base-emitter) offset voltage of the second transistor of the source follower (or emitter follower) is stored in the second capacitor, In the second period, the first transistor forming the gate circuit is turned on, the input signal level is stored in the first capacitor, and the level of the first capacitor and the level of the second capacitor are added. A sample and hold circuit adapted to supply a signal having a level equal to that of the input signal to the output by supplying the level to the gate (or the base) of the second transistor of the source follower (or the emitter follower).