JPH0667624A - Image display method for electrooptic device - Google Patents

Abstract

PURPOSE:To reduce a flicker and to make a detailed gradational display by eliminating the asymmetry of VLC with reansfer gate type circuit constitution using NTFT and PTFT. CONSTITUTION:Matrix-shaped electric conductors are formed with N signal lines X1, X2...XN and M signal lines Y1, Y2...YM, intersecting them orthogonally with a substrate. An N channel thin film transistor(TR) 63 and a P channel film TR 64 form a transfer gate element in the intersection area of each matrix. When a pulse applied to an optional signal line XN has the positive polarity, signals applied to the signal lines Y1, Y2...YM are negative or '0' and when the pulse applied to the optional signal line XN has the negative polarity, the signals applied to the signal lines Y1, Y2...YM are positive or '0'. Thus, the pulse is inverted while matching the polarity of the drain of the TFT to make a jump voltage symmetrical.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display method in a liquid crystal electro-optical device using a thin film transistor (hereinafter referred to as TFT) as a switching element for driving, and particularly for obtaining rich expression of intermediate tones and shades The present invention relates to a key display method.

[0002]

2. Description of the Related Art Liquid crystal compositions have different permittivities in the horizontal and vertical directions with respect to the molecular axis because of their material properties, and therefore they can be aligned horizontally or vertically with respect to an external electric field. It can be done easily. The liquid crystal electro-optical device utilizes the anisotropy of the dielectric constant to control the amount of transmitted light or the amount of scattered light, thereby performing ON / OFF, that is, bright / dark display. Known liquid crystal materials include materials called TN (twinsteady nematic) liquid crystal, STN (super twinned nematic) liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, polymer liquid crystal or dispersion type liquid crystal. There is.

Among electro-optical devices using liquid crystals, the one which can obtain the most excellent image quality is one using the active matrix system. In a conventional active matrix type liquid crystal electro-optical device, a thin film transistor (TFT) is used as an active element, an amorphous or polycrystalline semiconductor is used for the TFT, and P is used for one pixel.
The TFT of only one of the N type and the N type was used. That is, in general, N-channel TFT
(Referred to as NTFT) is connected in series to the pixel. Then, a signal voltage is applied to the signal lines of the matrix, and when signals are applied from both sides to the TFTs provided at the orthogonal positions of the respective signal lines, the TFTs are turned on. It was to control OFF individually. By controlling the pixels by such a method, a liquid crystal electro-optical device having a large contrast can be realized.

[0004]

However, in such an active matrix system, it is extremely difficult to perform gradation display such as brightness and color tone. Conventionally, a method of utilizing the fact that the light transmittance of the liquid crystal changes depending on the magnitude of the applied voltage has been studied for gradation display. This is, for example, the source of the TFT in the matrix
By supplying an appropriate voltage from the peripheral circuit between the drains and applying a signal voltage to the gate electrode in that state,
It was intended to apply a voltage of that magnitude to the liquid crystal pixels.

However, in such a method, the voltage applied to the liquid crystal pixel actually varies from pixel to pixel by at least several percent due to, for example, the non-uniformity of the TFT and the non-uniformity of the matrix wiring. Oops. On the other hand, for example, the voltage dependence of the light transmittance of liquid crystal is extremely non-linear, and the light transmittance changes abruptly at a certain voltage. It could be significantly different. For example, in TN liquid crystal which is a typical liquid crystal material, an intermediate light transmission state from an OFF state with no light transmission to an ON state where light transmission is saturated has a voltage width of 1.2V. There is nothing. Therefore, 1
To achieve 6 gradations, the voltage applied to the liquid crystal is 75m
It was necessary to control with the accuracy of V. Therefore, actually, it was a limit to achieve 16 gradations.

The difficulty of gradation display is extremely disadvantageous in that the liquid crystal display device competes with the CRT (cathode ray tube) which is a conventional general display device. An object of the present invention is to propose a completely new method for realizing gradation display which has been difficult in the past.

In the conventional liquid crystal display device, the voltage cannot be applied to the liquid crystal pixels with good reproducibility in order to obtain intermediate color tone and light and shade, for the following reason.
FIG. 3 shows a drive signal of a conventional TFT liquid crystal display device and a circuit diagram for one pixel.

In the circuit diagram of FIG. 3, the liquid crystal pixel itself functions as a capacitor and has a capacitance C _LC . Further, usually, a configuration is adopted in which a capacitor is inserted in parallel with a liquid crystal pixel. The capacity of this condenser is C '. The reason why the capacitor is inserted in this way is that there is a parasitic capacitance C _TFT generated between the gate electrode of the TFT and the source region (defined as an impurity region on the liquid crystal side of the TFT; the same applies hereinafter).

A normal liquid crystal drive signal is T as shown in FIG.
To the FT, a signal, such as V _D, whose polarity is inverted every screen is applied to the drain, and V _G is applied to the gate electrode.
A pulse signal is periodically added as shown in. TFT is N
A positive pulse signal is used in the case of MOS, and a negative pulse signal is used in the case of PNOS. Further, V _D includes an image signal. This signal is usually an analog signal. In the following example, for simplicity of explanation, it is assumed that a constant voltage is always applied to the screen and the liquid crystal is applied with a drive signal so that the entire surface shows the same color.

The reason V _D is a signal whose polarity is inverted for each screen is because it is necessary to add a signal whose polarity is inverted for each screen to the liquid crystal by doing so. That is, if the liquid crystal is continuously applied with a DC voltage for a long time, the liquid crystal undergoes electrolysis and its characteristics are deteriorated. The operation of constantly reversing the voltage applied to the liquid crystal is called alternating current. This exchange may be performed not only for each screen, but also for a plurality of screens.

When a drive signal is externally applied to the TFT in this way, a voltage such as V _LC is applied to the liquid crystal. Then, since this _VLC is greatly different from the ideal one, it becomes difficult to perform the halftone display as described above.

First, since a signal is applied to the drain and then a signal to the gate, the TFT is turned on and the liquid crystal is charged. Then, since the gate signal is turned off while the signal is continuously applied to the drain, ideally, the voltage initially applied to the drain remains in the liquid crystal, and thereafter, the leak current (OFF current) of the TFT. It is expected that it will gradually become smaller as a result. However, when the gate signal is cut off, the voltage applied to the liquid crystal is reduced by ΔV. To be exact, −Δ
A voltage of V is applied.

[0013] It is through the parasitic capacitance C _TFT of the gate electrode shown above, and because the liquid crystal of the pixel electrode and the gate line are capacitively coupled, in theory, ΔV = C _TFT · V _G / (C _TFT + C _LC + C '), Such voltage fluctuations are referred to as “dive voltage”.
Say. Furthermore, when the next screen is formed, the jump voltage acts to apply a negative voltage of ΔV to the negatively charged liquid crystal pixel, which is caused by the gate electrode. This is because the voltage drops from positive to zero, while the drain and liquid crystal pixel voltages are in a negative state.

The operation of the TFT also differs depending on whether the drain voltage is positive or negative. The current drive capability of the TFT increases as the difference between the gate voltage and the drain voltage increases. Therefore, when the drain voltage is positive and the gate voltage is also positive, the current driving capability is smaller than when the drain voltage is negative and the gate voltage is positive, and therefore, the liquid crystal pixel cannot be sufficiently charged. Occurs. In particular, when the scale of the matrix becomes large, the width of the pulse applied to the gate electrode becomes short, and the ON time of the TFT becomes as short as several tens of microseconds or less, and mobility such as amorphous silicon is small. A TFT using a material may not be able to perform sufficient switching in some cases. As a result, as shown in FIG. 3, the absolute value of the voltage charged in the liquid crystal varies depending on the polarity of V _D , which causes a phenomenon that the liquid crystal is not symmetrical. In addition, since the jump voltage ΔV is the same regardless of the polarity of V _D , the asymmetry is further emphasized.

Since the liquid crystal itself, particularly the TN liquid crystal and the STN liquid crystal, changes the light transmissivity according to the magnitude of the absolute value, not the polarity of the voltage, application of such an asymmetric voltage is As a result, I intend to display "black" but display gray. In addition, since the asymmetry of V _LC is that the DC component is superposed on the AC component, there is no meaning of AC conversion and deterioration of the liquid crystal may be caused.

Further, for example, if the cycle of one screen is about 30 μsec as in the case of a normal television, it is 30 μs.
Every ec, the screen becomes dark (V _D is positive) and bright (V _{D is}
Flickering (flickering)
Cause of. Such flicker becomes a problem especially when using a halftone display. If only black and white display is required, a large voltage may be applied in anticipation of the asymmetry of V _LC , so there is no visual problem. However, in the halftone display, it is not possible to visually cheat by adding a large voltage,
Since it is unavoidable to apply a voltage near the threshold voltage of the liquid crystal, a slight deviation of V _LC causes white and black to appear alternately.

If C _TFT is made small and (C _LC + C ') is made large, ΔV can be made small and specific symmetry can also be made small.
C a _TFT to reduce, for example, by self-alignment method, it is possible to reduce the geometric overlap of the gate electrode and the source region. However, for example, amorphous silicon TFTs and aluminum gate TFTs have an inverted stagger type structure due to manufacturing problems, and it is extremely difficult to adopt the self-alignment method.

In addition, increasing _C'and C _LC results in an increase in the amount of current flowing through the matrix, which leads to an increase in power consumption, and of course, in order to cope with this, the drive capability of the TFT must be increased. For that purpose, for example, a TFT having a high mobility such as a polysilicon TFT.
It is required to change the matrix manufacturing method and the design specifications such as using a matrix, reducing the channel length, and increasing the channel width. In reality,
Even if the ΔV is reduced by the above method, the polysilicon TFT is 0.1 V, the amorphous silicon T
In FT, ΔV of 1 to several V is observed.

Even if the problem of ΔV is solved, it is still difficult to solve that the absolute value of V _LC differs depending on the polarity of V _D. For example, a method of changing the magnitude of V _G according to the polarity of V _D can be considered.
That is, when V _G is -5V is the V _G + 10V and, when V _G is + 5V, by to a V _G + 20V, is a method of substantially constant V _G -V _D.
However, as is clear from the above example, it is necessary to apply a high voltage of up to 20 V to the gate, and the voltage of the gate drive signal fluctuates by 10 V, resulting in low voltage and low power consumption. Does not meet the current demand for. Furthermore, ΔV is proportional to V _G , so it does not solve the problem as a whole. It is also possible to change the pulse width of V _G according to the polarity of V _D.
In this case, the entire matrix must also be considered. For example, the matrix has 400 rows and 60 rows per second.
When the screen is configured, the maximum pulse width of V _G is 40 μsec. Current drivability when V _D is positive is, if one-half of the current driving capability in the case of negative, when V _D is positive, the pulse width of the V _G is 40μse
When c and V _D are negative, the pulse width is changed to 20 μsec. In this case, as a matter of course, when V _D is negative, the pulse width falls to about half of that when the pulse width is 40 μsec. That is, it is unavoidable to use it in a state where it does not exert its full potential.

[0020]

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate, for example, the asymmetry of V _LC clarified in the above description, thereby reducing flicker and obtaining fine gradation display. .

[0021]

[Means for Solving the Problem] It can be said that the above-mentioned difficulties are caused by the asymmetry of the TFT. In the present invention, one NTFT or PT as in the prior art is used.
It is not an asymmetric circuit using only FT, but FIG.
As shown in FIG. 5, the asymmetric V _LC is solved by using a so-called transfer gate type circuit by using NTFT and PTFT.

1A and 1B show examples of drive signals applied in the circuit of the present invention. In this example, the polarity of the pulse applied to the gate does not change with one pulse, but the jump voltage can be generated symmetrically by reversing the pulse according to the polarity of V _D. Also, paying attention to the difference between V _G and V _D , it is constantly constant regardless of the polarity of V _D ,
Therefore, the absolute value of V _LC immediately after charging does not depend on the polarity of V _D.

In FIG. 1A, the polarities of V _G and V _D are the same, and in FIG. 1B, the polarities of V _G and V _D are opposite. Therefore, the current drive capacity of the TFT is
(B) having a large difference between V _G and V _D is larger. However, no matter which method is adopted, V _LC remains symmetrical.

FIG. 2 shows another example of the present invention. Here, as the pulse applied to the gate, a bipolar pulse in which a positive polarity pulse and a negative polarity pulse are integrated is applied. By applying such a pulse, the current driving capability can be increased as compared with the case of applying a unipolar pulse as shown in FIG.

In FIG. 2A, if the polarity of V _D is positive, the bipolar pulse is first a positive pulse followed by a negative pulse. However, if the polarity of V _D is negative, the bipolar pulse will have a negative pulse first, followed by a positive pulse. In addition, FIG. 2 (B)
If the polarity of V _D is positive, the bipolar pulse has a negative pulse first, followed by a positive pulse, and if the polarity of V _D is negative, the bipolar pulse is , There may be a positive pulse first, followed by a negative pulse. It should be noted that in either method, the bipolar pulse has its polarity order reversed according to the polarity of V _D. By performing the driving symmetrically in this way, the symmetry of the jump-in voltage can be obtained as in the case of FIG.

Further, even if either method of FIG. 2 is adopted, there is almost no difference in current driving capability as in the case of FIG.

In the above example, the mobility of the NMOS and that of the PMOS are treated as the same, but, for example, polysilicon T
In FT, the mobility of the PMOS is a fraction of the mobility of the NMOS, and the PMOS has the same shape as the NMOS.
If pulses with the same height and width are applied, the PMO
The current flowing through S is a fraction of that of NMOS.
In that case, the above-mentioned symmetry cannot be maintained.

Therefore, for example, it is necessary to take measures such as reducing the channel length of the PMOS to a fraction, multiplying the channel width to several times, or multiplying the pulse height and width of the pulse to several times. . However, changing the pulse height is not desirable because it puts a burden on the drive circuit, as shown in the NMOS example.

For example, when using bipolar pulses, the width of the positive pulse can be adjusted by a fraction of the width of the negative pulse. In this case, once the circuit is manufactured, the drive pulse may be adjusted after confirming the difference in mobility between the NMOS and the PMOS.
Easy to operate. Moreover, since the sum of the width of the positive pulse and the width of the negative pulse can be made constant, there is no problem even when the driving of the entire matrix is considered. For example,
If the driving capability of NMOS is three times that of PMOS,
The width of the positive pulse is 10 μsec, and the width of the negative pulse is 30 μsec.
If the driving capability of the NMOS is 4 times that of the PMOS, the width of the positive pulse is 8 μsec, and the width of the negative pulse is 3 μsec.
If it is set to 2 μsec, the duration of the entire pulse can be kept at 40 μm in any case.

Although the mobility of TFT is not so different on the same liquid crystal display, it may be greatly different between different displays. This happens even under the same manufacturing conditions, and it is considered that the cause is an extremely small difference in parameters. Therefore, NMOS
Even if the difference in the characteristics of the PMOS and the PMOS is folded in advance to produce a display, a slight difference may occur between lots. In such a case, a method of finely adjusting the pulse width as described above Is effective.

In the above example, the case of performing analog halftone display has been described, but the present invention is also applied to, for example, digital grayscale display.
The digital gradation display is to obtain an intermediate color tone / shade by controlling the ratio of the time when the ON state and the OFF state of the liquid crystal appear.
_{When LC} symmetry exists, the desired gradation display cannot be obtained.

For example, it is assumed that 6V is applied to the liquid crystal for half the time and no voltage is applied to the liquid crystal for the other half time. Effectively, the voltage of 3V was applied during this time. It is known that the light transmissivity of liquid crystal is determined by the effective voltage.
It is in the transition (intermediate gradation) region of the N liquid crystal, and it looks like an intermediate brightness visually.

However, it is assumed that V _LC is shifted by 1 V to the negative side due to the plunge voltage and other factors. That is, in the first one screen, the voltage of 5V is half, the voltage of -1V is half, and the voltage of 2V is effectively applied. On the other hand, in the next one screen, -7V and -1V
Is applied half by half, effectively 4V voltage is applied. In this way, 2V and 4V for each screen
Voltage is applied to the liquid crystal, but both voltages are outside the transition region, and the liquid crystal itself repeats black and white, and visually appears as a flickering gray.

However, according to the present invention, since V _LC maintains symmetry, it is as described above that this problem is solved.

As described above, according to the present invention, the symmetry of V _LC can be maintained even if the jump voltage ΔV is large. The advantages of another aspect of the invention will now be described. As described above, an effective method such as a self-alignment method is known to reduce ΔV. However, in the self-alignment method, impurities are diffused after the gate electrode is formed. Therefore, the gate electrode must be formed of a heat resistant material such as doped silicon. However, in a large-screen liquid crystal display, a low resistance material such as aluminum is desired for the purpose of reducing the resistance of the gate wiring. Of course, the use of a heat-resistant metal such as molybdenum has been investigated, but it has not been put into practical use due to the problem of adhesion with the gate oxide film (silicon oxide). The good compatibility between aluminum and the gate oxide film has been proved by the past aluminum gate MOS, so that it is desirable to use aluminum as the gate electrode.

However, as long as aluminum is used, the self-alignment method cannot be adopted. The present invention provides one solution to this contradiction. In other words, even an aluminum gate TFT manufactured by the non-self-alignment method can perform halftone display with extremely high accuracy and no flicker problem.

That is, if the parasitic capacitances of the gate electrode and the source region are “designed” in advance and the display is manufactured by the non-self-alignment method, the value of ΔV can also be calculated. Therefore, gradation display should be performed accordingly. The required drive signal can be added. At this time, each TF
It is necessary to make it so that the variation of the parasitic capacitance for each T is small. In the case where the parasitic capacitance C _TFT is manufactured by the non-self-alignment method, if the gate insulating film has a thickness of 100 nm, the channel width is 10 μm, and the overlap between the gate electrode and the source region is 10 μm, the manufacturing error is also taken into consideration. , (40
± 2) fF. On the other hand, C _LC and C'are 40 in total
0fF is possible, and C _TFT is 10% of (C _LC + C ')
It is a degree. If V _G is 10 V, ΔV is C
Considering the variation of _TFT , the voltage control of (1 ± 0.05) V, which is a condition for displaying 16 gradations, of 75 mV or less is sufficiently possible.

When the present invention is not used, V _LC is in a state where a voltage of -1 V is always superimposed on the signal voltage, and V _D is set to about 3 V which is the threshold voltage of the TN liquid crystal. If so, _VLC repeats 2V and 4V for each screen, but both voltages are in the transition region of the liquid crystal (substantially different depending on the material, but a typical value of TN liquid crystal is 2.4V to 3.6V). It's outside of, so it's a repetition of black and white, and in the end it just looks like a flickering gray. Further, even if V _D is set to 3.25 V, V _LC repeats between 2.25 V and 4.25 V, and in this case also, white and black repeat. After all, without using the present invention,
It can be seen that it is difficult to perform fine halftone display when ΔV is large. Of course, it will be apparent that the present invention is effective even in a circuit in which the _CTFT is made sufficiently small in advance by the self-alignment method or the like.

To carry out the present invention, TN liquid crystal, STN liquid crystal, ferroelectric liquid crystal, and dispersion type (polymer) liquid crystal are suitable as the liquid crystal material. Further, if the present invention is implemented, it is necessary to build a matrix circuit using a TFT as shown in FIG. The circuit shown in FIG.
640 × 48, which is a matrix of (C).
It is 0 dots. Hereinafter, the TF necessary for carrying out the present invention
An example of a method of manufacturing T will be shown.

[0040]

【Example】

[Embodiment 1] In this embodiment, a matrix circuit of a liquid crystal display device having a circuit configuration as shown in FIG. Further, the TFT at that time was made of polycrystalline silicon using laser annealing.

FIG. 5 shows an actual arrangement of electrodes and the like corresponding to this circuit structure for four pixels. First, a method for manufacturing a liquid crystal panel used in this example will be described with reference to FIGS. In FIG. 6A, a silicon oxide film as a blocking layer 51 is formed by a magnetron RF (radio frequency) sputtering method on a glass 50 that has heat resistance and can withstand heat treatment at 700 ° C. or lower, for example, about 600 ° C.
000 to 3000 Å is produced. Process conditions are 100% oxygen atmosphere, film formation temperature 15 ° C., output 400 to 8
The pressure was 00 W and the pressure was 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target is 30-100Å /
It was a minute.

A silicon film 5 is formed on this by a plasma CVD method.
2 was produced. The film forming temperature was 250 ° C. to 350 ° C., and in this embodiment, it was 320 ° C., and monosilane (SiH ₄ ) was used.
Not limited to monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into the PCVD apparatus at a pressure of 3 Pa, and high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.02
~0.10W / cm ² are suitable, 0 in this embodiment.
055 W / cm ² was used. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the film formation rate at that time was about 120.
It was Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. . Further, not only the plasma CVD but also the sputtering method or the low pressure CVD method may be used for forming the silicon layer to be the channel region of the TFT. The method will be briefly described below.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with 20% to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When forming by the reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 5
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to a CVD apparatus at 30 ° C. to form a film. The reactor pressure is 30 ~
It was set to 300 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and that of the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

The film formed by these methods is
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, the oxygen concentration is 7 × 10 ¹⁹ cm ^-3 or less,
It is preferable that the size is 1 × 10 ¹⁹ cm ^-3 or less,
If the amount is too small, the leak current in the off state increases due to the backlight, so this concentration was selected. If the oxygen concentration is high, it is difficult to crystallize, and the laser annealing temperature must be high or the laser annealing time must be long. Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon is 4 × 10 ²²
It was 1 atom% when compared as cm ^-3 .

In order to further promote crystallization of the source and drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ^-3 or less, preferably 1 × 10 ¹⁹ cm ^-3 or less, and the TF for forming a pixel is set.
Oxygen may be added only to the channel forming region of T by the ion implantation method so as to have a concentration of 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ .
By the above method, an amorphous silicon film is formed into 500
The film was formed to a thickness of ˜5000 Å, 1000 Å in this example.

After that, a pattern in which only the source / drain regions were opened was formed using the photoresist 53 as a mask. A silicon film 54, which will be an n-type active layer, was formed thereon by a plasma CVD method. Deposition temperature is 250 ° C ~
It is carried out at 350 ° C., and in this embodiment 320 ° C., monosilane (SiH ₄ ) and monosilane-based phosphine (PH ₃ ).
A 3% concentration was used. These are 5P in PCVD equipment
It was introduced at a pressure of a, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to 0.
20 W / cm ² is suitable, and 0.120 in this embodiment.
W / cm ² was used.

The specific conductivity of the n-type silicon layer produced by this method was about 2 × 10 ^-1 [Ωcm ^-1 ]. The film thickness was 50Å. After that, the lift-off method is used to remove the resist 53, and the source / drain regions 5 are removed.
5, 56 were formed. Further, a p-type active layer was formed using the same process. The gas introduced at this time was monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) 5
% Concentration was used. These are 4P in the PCVD equipment.
It was introduced at a pressure of a, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high frequency power is 0.05 to 0.
20 W / cm ² is suitable, and 0.120 in this embodiment.
W / cm ² was used. P created by this method
The specific conductivity of the type silicon layer was about 5 × 10 ^-2 [Ωcm ^-1 ]. The film thickness was 50Å. Thus, FIG. 6 (B)
Got

After that, the source / drain regions 59 and 60 were formed by using the lift-off method similarly to the N-type region. After that, the silicon film 52 is removed by etching using a mask, and the N-channel type thin film transistor island region 6 is formed.
3 and island region 6 for P-channel thin film transistor
4 was formed.

After that, as shown in FIG. 6C, XeCl
Using an excimer laser, the source / drain / channel regions were laser-annealed and simultaneously the active layer was laser-doped. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required for melting the entire film thickness. However, when the energy of 220 mJ / cm ² or more is applied from the beginning, the hydrogen contained in the film is rapidly released, so that the film is broken. Therefore, it is necessary to first drive out hydrogen with low energy and then melt it. After performing the flush hydrogen in the first 150 mJ / cm ² in the present embodiment was subjected to crystallization at 230 mJ / cm ^2.

On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000Å, for example 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

Thereafter, an aluminum film having a thickness of 0.5 μm is formed on the upper side of this, and this is patterned by a fourth photomask to perform gate electrode 66 for NTFT and PTF.
A gate electrode 67 for T was formed. As the size of the gate electrode, for example, a channel length of 7 μm and a channel width of 10
Micron was used. Thus, FIG. 6D was obtained. at the same time,
As shown in FIG. 7A, the gate wiring 65 and the wiring 68 arranged in parallel therewith were also patterned.

In this way, a C / TFT can be manufactured without applying a temperature above 400 ° C. in all steps. Therefore, an expensive substrate such as quartz does not have to be used as the substrate material, and it can be said that the process is extremely suitable for the large-screen liquid crystal display device of the present invention.

Further, the inter-layer insulator 69 was formed as a silicon oxide film by the above-mentioned sputtering method. The silicon oxide film may be formed by using the LPCVD method, the photo CVD method, or the atmospheric pressure CVD method. For example, it is formed to a thickness of 0.2 to 0.6 μm, and then a window 79 for an electrode is formed using a fifth photomask. After that, aluminum was further formed on the entire surface by sputtering to a thickness of 0.3 μm, and a lead 74 and contacts 73 and 75 were formed using a sixth photomask. Thus, FIG. 6E was obtained. The plane is as shown in FIG. 7 (B).

After that, an organic resin 77 for flattening the surface was applied and formed, for example, a translucent polyimide resin, and re-drilling of electrodes was performed using a seventh photomask. Further, ITO (Indium Tin Oxide) is formed on the whole of the above to have a thickness of 0.1 μm by the sputtering method, and the pixel electrode 71 is formed using the eighth photomask. This ITO is room temperature to 150
The film was formed at a temperature of 200 ° C., and the film was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere. Thus, FIG. 6F was obtained.
The plan view is as shown in FIG.

FIG. 7D is a sectional view taken along the line AA 'of FIG. 7C.
Shown in. Actually, a counter electrode is provided on top of this with a liquid crystal material interposed therebetween, and as shown in the figure, a capacitance is generated between the counter electrode and the electrode 71. At the same time, the wiring 68 and the electrode 7
Capacitance also occurs during the period 1. Then, by keeping the wiring 68 at the same potential as the counter electrode, it is possible to form a circuit in which a capacitance is inserted in parallel with the liquid crystal pixel as shown in FIG. Particularly, by arranging as in this embodiment, the wiring 68 is parallel to the gate wiring 65, and
The parasitic capacitance between the wirings is small, and therefore, there is an effect of reducing the attenuation and delay of the signal transmitted through the gate wiring. The electrical characteristics of the TFT obtained as described above are PTFT, mobility is 40 (cm ² / Vs), Vth is -5.9 (V), and NT
By FT, the mobility was 80 (cm ² / Vs) and Vth was 5.0 (V).

A matrix circuit for a liquid crystal display device manufactured according to the method as described above could be obtained. FIG. 5 shows how electrodes and the like of this liquid crystal display device are arranged.
An N-channel type thin film transistor and a P-channel type thin film transistor are provided at the intersections of the signal lines Y ₁ and Y ₂ . A matrix structure using such C / TFT is provided. By repeating this structure horizontally and vertically, a liquid crystal display device with large pixels of 640 × 480 and 1280 × 960 can be obtained. In this embodiment, 1
It was set to 920 × 400.

[Embodiment 2] In this embodiment, a matrix circuit for a liquid crystal display device having a circuit configuration as shown in FIG. 4 is manufactured, which will be described. Moreover, the TFT at that time
Is polycrystalline silicon produced by a low temperature recrystallization process.

In the following, a method of manufacturing the TFT portion will be described with reference to FIG. In FIG. 8 (A), magnetron RF (high frequency) is provided on glass 100 that has heat resistance and can withstand heat treatment at 700 ° C. or lower, for example, about 600 ° C.
A silicon oxide film as the blocking layer 101 is formed with a thickness of 1000 to 3000 Å by using the sputtering method.

On top of this, a silicon film 1 is formed by a plasma CVD method.
02 was produced. This plasma CVD is used to form a silicon layer.
Alternatively, a sputtering method or a low pressure CVD method may be used. The silicon film is 500 to 5000 Å, and 100 in this embodiment.
A film was formed to a thickness of 0Å.

Then, a pattern was formed by using the photoresist 103 as a mask and opening only the regions to be the source / drain regions of the NTFT. Then, using the resist 103 as a mask, phosphorus ions are ion-implanted by 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 1.
^Implanting only 0 ¹⁶ cm ^-2 to form the n-type impurity region 104. After that, the resist 103 was removed.

Similarly, a resist 105 was applied, and a mask was used to form a pattern in which only the regions to be the source / drain regions of the PTFT were opened. Then, the p-type impurity region 106 was formed using the resist 105 as a mask. As the impurity, boroso was used, and the ion implantation method was also used to introduce the impurity in an amount of 2 × 10 ^{14 to} 5 × 10 ¹⁶ cm ⁻² , preferably 2 × 10 ¹⁶ cm ⁻² . In this way. 8B is obtained.

After that, a thickness of 50 to 3 is formed on the silicon film 102.
00 nm, for example, 100 nm of silicon oxide film 107
Was formed by the RF sputtering method described above. And
A temperature of 450 to 700 ° C, preferably 550 to 600 ° C
At a temperature of 12 to 70 hours, for example 24 hours, in a non-oxidizing atmosphere, for example, a hydrogen or nitrogen atmosphere. After the heat treatment, the silicon oxide film 107 was removed.

After that, island-shaped NTFT regions 111 and PTFT regions 112 were formed by a photomask. A silicon oxide film 108 is formed thereon as a gate insulating film with a thickness of 500 to 2000Å, for example, 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of fluorine may be added to immobilize sodium ions.

After this, an aluminum film having a thickness of 0.5 μm was formed on the upper side. This is patterned by a fourth photomask to form a gate electrode 109 for NTFT,
A gate electrode 110 for PTFT was formed. The size of the gate electrode is, for example, 3 μm for PMOS and NMOS.
Was set to 7 μm, and the channel widths were both set to 10 μm. Although not shown in the drawing, a gate wiring and a wiring parallel to the gate wiring were formed as in the case of the first embodiment. Thus, FIG. 8D was obtained.

In FIG. 8E, the inter-layer insulator 113 was formed as a silicon oxide film by the above-mentioned sputtering method. This silicon oxide film is formed by LPCVD method, photo CVD method.
Method, atmospheric pressure CVD method may be used. For example, 0.2-0.
It was formed to a thickness of 6 μm, and then a window 117 for an electrode was formed using a fifth photomask. After that, aluminum is further formed on the entire surface to a thickness of 0.3 μm by a sputtering method, a lead 116 and contacts 114 and 115 are formed using a sixth photomask, and then an organic resin 119 for planarizing the surface is formed. For example, a translucent polyimide resin was applied and formed, and the electrode holes were re-drilled with the seventh photomask. In addition, ITO is
(Indium tin oxide) is formed to a thickness of 0.1 μm by a sputtering method, and the pixel electrode 1 is formed by using an eighth photomask.
18 was formed. This ITO was formed into a film at room temperature to 150 ° C. and accomplished by oxygen at 200 to 400 ° C. or an anneal in the atmosphere.

The electric characteristics of the obtained TFT are PTFT.
The mobility is 35 (cm ² / Vs), Vth is -5.9 (V),
Mobility is 90 (cm ² / Vs) and Vth is 4.8 with NTFT
(V). A matrix circuit for a liquid crystal display device was obtained according to the method as described above.

[0068]

According to the present invention, due to the application of a DC voltage to the liquid crystal due to the superposition of the jump voltage, the drain voltage dependence of the TFT current drive characteristics, and the jump voltage, which have been problems in the conventional TFT liquid crystal display device. Problems such as flickering, flicker, and difficulty in gradation were solved.

In particular, according to the present invention, it is shown that the above problem can be solved without reducing the parasitic capacitance C _TFT by the self-alignment method or the like, and the aluminum gate TFT can be manufactured by the non-self-alignment method. It was suggested that a liquid crystal display could be used. Of course, when the present invention is used in a display manufactured by a self-aligned method, a similar effect can be obtained, and the present invention is not limited to the display manufactured by the non-self-aligned method. In particular, by implementing the present invention, it is possible to solve the problem that the current drive capability of the TFT depends on the polarity of V _D , even if the display is manufactured by the non-self-alignment method, or by the self-alignment method. It will be clear that the same is true for the display produced.

Although the present invention has been described with the analog 16 gradations in mind, it is effective to use the present invention even for digital gradations, as mentioned a little in the text. In digital gradation, higher gradation display of 64 gradations or more is possible, and since fine control of the effective voltage is also required for that purpose, the present invention has little fluctuation in the effective voltage due to alternating current. Is effectively used.

Further, although a direct-view type liquid crystal display device has been particularly described in the present text, the present invention is also applied to an optical switch such as a liquid crystal matrix circuit used as an optical switch in a projection type display device, an optical shutter, and the like. It will be clear that the invention works well. Further, it is obvious that the present invention can be implemented as long as it is an active circuit using not only the liquid crystal but also a material whose optical characteristics are changed by the effect of an electric field or an electric field. Further, it is obvious that the present invention can also be used for an active element of an electro-optical pixel, which uses not a TFT but a monolithic IC formed on a single crystal semiconductor substrate.

In the embodiment of the present invention, T using silicon is used.
I explained mainly about FT, but T using germanium
FT can be used as well. In particular, single crystal germanium has an electron mobility of 3600 cm ² / Vs and a hole mobility of 1800 cm ² / Vs, which is the value of single crystal silicon (electron mobility is 1350 cm ² / Vs, hole mobility is 480 c).
Since it exceeds the characteristic of m ² / Vs), it is an extremely excellent material for carrying out the present invention which requires high-speed operation. Further, germanium has a lower transition temperature from an amorphous state to a crystalline state than silicon, and is suitable for a low temperature process. Further, the nucleus generation rate during crystal growth is small, and therefore, generally, large crystals are obtained when polycrystal growth is performed. Thus, germanium has characteristics comparable to those of silicon.

[Brief description of drawings]

FIG. 1 shows an example of a circuit of the present invention and a drive waveform.

FIG. 2 shows an example of a circuit of the present invention and a drive waveform.

FIG. 3 shows an example of a conventional circuit and a drive waveform.

FIG. 4 shows an example of a matrix configuration according to the present invention.

FIG. 5 shows a planar structure of a device according to an example.

FIG. 6 shows a process of a TFT according to an example.

FIG. 7 shows a process of a TFT according to an example.

FIG. 8 shows a process of a TFT according to an example.

Claims (4)

[Claims] 1. N signal lines X _1, X _{2 ,} .. X _n, .. on a substrate.
X _N and M signal lines Y _1, Y _2, ..Y _m, ..
Y _M in the form of a matrix, and at the intersection region of each matrix, at least one transfer gate element formed of an N-channel type thin film transistor and a P-channel type thin film transistor, and an intersection of each signal line. Pixels Z _11, provided in the area
Z ₁₂ , ... Z _mn , ... Z _MN , the output terminal of each transfer gate element is connected to one of the electrodes of the electrostatic device forming each pixel, In the electro-optical device in which the control electrodes are connected to the signal lines X _1, X ₂ , ..X _n, ..X _N and the input terminals are connected to the signal lines Y _1, Y _2, ..Y _m, ..Y _M , When the pulse applied to any signal line X _n has a positive polarity, the polarity of the signal applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M is negative or zero, Arbitrary signal line X _n
When the pulse applied to the negative polarity has a negative polarity, the signal line Y _1,
An image display method for an electro-optical device, wherein the polarities of signals applied to Y _2, ..Y _m, ..Y _M are positive or zero. 2. N signal lines X _1, X _{2 ,} .. X _n, .. on the substrate.
X _N and M signal lines Y _1, Y _2, ..Y _m, ..
Y _M in the form of a matrix, and at the intersection region of each matrix, at least one transfer gate element formed of an N-channel type thin film transistor and a P-channel type thin film transistor, and an intersection of each signal line. Pixels Z _11, provided in the area
Z ₁₂ , ... Z _mn , ... Z _MN , the output terminal of each transfer gate element is connected to one of the electrodes of the electrostatic device forming each pixel, In the electro-optical device in which the control electrodes are connected to the signal lines X _1, X ₂ , ..X _n, ..X _N and the input terminals are connected to the signal lines Y _1, Y _2, ..Y _m, ..Y _M When the pulse applied to any signal line X _n has a positive polarity, the polarity of the signal applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M is positive or zero, Arbitrary signal line X _n
When the pulse applied to the negative polarity has a negative polarity, the signal line Y _1,
An image display method for an electro-optical device, wherein the polarities of signals applied to Y _2, ..Y _m, ..Y _M are negative or zero. 3. N signal lines X _1, X _2, ..X _n, ..
X _N and M signal lines Y _1, Y _2, ..Y _m, ..
Y _M in the form of a matrix, and at the intersection region of each matrix, at least one transfer gate element formed of an N-channel type thin film transistor and a P-channel type thin film transistor, and an intersection of each signal line. Pixels Z _11, provided in the area
Z ₁₂ , ... Z _mn , ... Z _MN , the output terminal of each transfer gate element is connected to one of the electrodes of the electrostatic device forming each pixel, In the electro-optical device in which the control electrodes are connected to the signal lines X _1, X ₂ , ..X _n, ..X _N and the input terminals are connected to the signal lines Y _1, Y _2, ..Y _m, ..Y _M , When a bipolar pulse is applied to the signal lines X _1, X ₂ , ..X _n, ..X _N , the bipolar pulse applied to an arbitrary signal line X _n starts with a positive polarity. In this case, the polarity of the signal applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M is negative or zero, and the bipolar pulse applied to any signal line X _n is negative. If you start with the polarity of
An image display method for an electro-optical device, wherein the polarities of the signals applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M are positive or zero. 4. N signal lines X _1, X _{2 ,} .. X _n, .. on the substrate.
X _N and M signal lines Y _1, Y _2, ..Y _m, ..
Y _M in the form of a matrix, and at the intersection region of each matrix, at least one transfer gate element formed of an N-channel type thin film transistor and a P-channel type thin film transistor, and an intersection of each signal line. Pixels Z _11, provided in the area
Z ₁₂ , ... Z _mn , ... Z _MN , the output terminal of each transfer gate element is connected to one of the electrodes of the electrostatic device forming each pixel, In the electro-optical device in which the control electrodes are connected to the signal lines X _1, X ₂ , ..X _n, ..X _N and the input terminals are connected to the signal lines Y _1, Y _2, ..Y _m, ..Y _M , When a bipolar pulse is applied to the signal lines X _1, X ₂ , ..X _n, ..X _N , the bipolar pulse applied to any signal line X _n starts with a negative polarity. In some cases, the polarity of the signal applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M is negative or zero, and the bipolar pulse applied to any signal line X _n is positive. If you start with the polarity of
An image display method for an electro-optical device, wherein the polarities of signals applied to the signal lines Y _1, Y _2, ..Y _m, ..Y _M are positive or zero.