JPH0667977A - Faulty system memory data transfer control system - Google Patents

Abstract

PURPOSE:To transfer data which must be written back in a cache to another system memory at high speed even when a processor bus fault is generated. CONSTITUTION:In a system which must keep the contents of MM3 of both systems in same condition, EDU6 switches SL9 by the instruction of software or hardware to send a write back instruction signal to a write back control circuit. The write back control circuit checks write back display an all the blocks of a cache memory circuit. Only the address/data of the block needing write back is sent to SL9 and transferred to another memory. When all the blocks are completed, a write back completion information is sent to EDU6 to start interruption in software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a faulty memory data transfer control system.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional faulty memory data transfer control system, which is a system for guaranteeing the identity of memory contents by performing a write-through cache control. This system uses a microprocessor (hereinafter CPU) 1 for executing a program, a cache control circuit (hereinafter CMU) 2, a main memory (hereinafter MM) 3, a memory control circuit (hereinafter MMU) 4, and a dual writing circuit. (Hereinafter D
WU) 5, failure detection circuit (hereinafter EDU) 6, input / output control circuit (IOC) 7, and input / output device (hereinafter IO)
8 and.

The DWU 5 collects the address / data at the time of the memory write access of the MMU 4 at the time of act, and the other system D
It has a function of transferring to WU or receiving address / data from other system DWU during standby, writing to MM3 via the memory bus, and keeping the same memory contents. IOC
Reference numeral 7 has a function of relaying data transmission / reception between the I / O 8 and MM3. The CMU 2 has a function of storing cache data and directory information and controlling a cache memory that supports a write-through cache. The EDU 6 collects fault information in the own system device and notifies the CPU 1 of interruption.

Next, the operation of this example will be described. In the fault memory data transfer control method of this example, only one CPU executes the program. CPU1 or IOC7
Makes a write access to the memory, DWU 5 sends the address and data to the DWU of the other system. In the other system, this information is stored in the processing queue in the DWU, and F
Writing to the own system memory is performed according to the principle of irst In First Out. At the time of read access, only the own system memory is accessed and the data is read. By such control, the identities of the memories of both systems are maintained, and if the system is switched at the time of failure, the memory can be restarted.

[0005]

In this conventional faulty memory data transfer control method, when a cache of copyback control is supported in order to improve the processing capacity, the copy of which the identity of the memory data cannot be instantaneously guaranteed. Due to the characteristics of back, if some kind of failure occurs in the act system, data that must be written back will always occur in the cache, so data will be lost or memory cannot be switched instantaneously. There is a problem that such data cannot be placed in the cache area.

[0006]

The faulty memory data transfer control system of the present invention is a faulty system in a processor system in which a duplicated central processing unit of the 0-system and 1-system secures the sameness of memory data of both systems. In the memory data transfer control method, a microprocessor for executing a program, a cache control circuit, a main memory, a dual write circuit for double writing to this main memory, and a fault detection for detecting a fault in the own system. A selector circuit for selecting the address / data from the cache control circuit and the address / data from the double write circuit and outputting the selected address / data to the interface section with the other system memory.

The fault detection circuit instructs write back by activating software or hardware,
A write-back instruction means for displaying, a switching instruction means for instructing switching to the selector circuit, a write-back completion notifying means for notifying the microprocessor of write-back completion, and a failure of its own system in case of failure by monitoring the write-back operation. Failure notification means for notifying the other system, and the cache control circuit autonomously writes back only the data that has been different from the contents of the memory because the cache data was updated when the write-back instruction was received. A write-back control circuit and a cache memory circuit that stores the cache data and directory information and supports a copy-back cache are provided.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of a faulty memory data transfer control system of the present invention, FIGS. 2 and 3 are block diagrams showing an example of internal configurations of a cache control circuit and a fault detection circuit in FIG. 1, and FIG. FIG. 5 is a first and a second partial diagram of the process flow chart when system switching is performed in the present embodiment, and the connection symbols of both diagrams are connected to form one flow chart. In FIG. 1, the same or similar components as those in the conventional example are designated by the same reference numerals as those in FIG.

In this embodiment, as shown in FIG. 1, a CPU 1 for executing a program, a CMU 2 adopting a copy back control system, an MM 3, an MMU 4, a DWU 5, an E
DU6, IOC7, IO8, DWU of the other system interface / data and DW from CMU2
It is composed of a selector circuit (hereinafter referred to as SL) 9 which selects and outputs the address / data from U5.

Further, as shown in FIG. 2, the CMU 2 stores cache data and directory information, and a cache memory circuit (hereinafter referred to as CM) 11 that supports copyback cache and a writeback control circuit (controls writeback). WBC) 10 and the EDU
As shown in FIG. 3, reference numeral 6 indicates a failure detection / collection of failure information in the own system device, and a write back instruction if necessary.
It is composed of a collection means (hereinafter ED) 13 and a processor interface control circuit (hereinafter CPI) 12 which interfaces with the CPU 1 and gives an interrupt notification and a write-back instruction for software activation.

Next, the operation of this embodiment will be described with reference to FIGS.
Will be described together.

First, when the EDU 6 detects a failure in its own system and system switching is activated by autonomous operation of hardware, or when instructed by software processing (generally, register write from the processor bus is performed. Cache access is prohibited, and the operation of transferring the transaction data in the cache to the other system memory is activated (step S1).

The activation request from the ED 13 and the CPI 12 inside the EDU 6 is logically ORed by the OR 14 and FF15.
Ignite As a result, the switching signal of the selector circuit of the memory intersection interface section is transmitted, and the CMU is generated at the intersection.
The address / data information from 2 is changed so that it is transferred to another system. At the same time, the watchdog timer that monitors the transfer operation is activated, and the write-back instruction signal is sent to the CMU 2. When the watchdog timer overflows (OVF), the transfer data cannot be trusted because the autonomous transfer circuit itself has failed. Therefore, the emergency signal is sent to the other system, and the other system emergency circuit is notified that the restart of the memory is stopped and the file load is started (S2).

When the CMU 2 receives the write-back instruction signal, in the case of the n-way set associative cache system, the WBC 10 sends out a way selection signal for each way. Only the way receiving the way selection signal becomes operable (S3, S4).

In each block, 1 bit of write-back display is provided independently of directories and data. This is part of the cache state of the directory. When the block selection signal is sent (S5, S6),
The write back (WB) indication bit of the block is WB
It is read by C10 and checked.

If the write-back display bit is set, it indicates that write-back is required (S7). The write-back reset signal is valid only in the block to which the way selection signal and the block selection signal are sent, and the CM 11 sends data and tag information to the bus by resetting this bit. Do this for all blocks,
When all blocks are completed in S6 and all ways are completed in S4, a write-back completion notification is transmitted, and the EDU 6 resets the watchdog timer and the write-back display by this signal (S9) and notifies the software of an interrupt. The software receives this and completes the system switching process (S
10).

[0017]

As described above, according to the present invention, when the cache of the copy-back control is supported, even if some failure occurs in the act system, the data that must be written back in the cache is hardware-protected. Since the data is autonomously transferred to another system, the memory can be switched in a very short time, and the memory can be restarted. Further, since the transfer path is exclusively provided, the transfer operation is guaranteed even when the processor bus fails, and the reliability is significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a faulty memory data transfer control system of the present invention.

2 is a block diagram showing an example of an internal configuration of a cache control circuit in FIG.

3 is a block diagram showing an example of an internal configuration of a fault detection circuit in FIG.

FIG. 4 is a first partial diagram of a processing flow chart when system switching is performed in the present embodiment.

FIG. 5 is a second partial diagram of a processing flowchart when system switching is performed in the present embodiment.

FIG. 6 is a block diagram showing an example of a conventional faulty memory data transfer control system.

[Explanation of symbols]

 1 Microprocessor (CPU) 2 Cache Control Circuit (CMU) 3 Main Memory (MM) 4 Memory Control Circuit (MMU) 5 Double Write Circuit (DWU) 6 Fault Detection Circuit (EDU) 7 Input / Output Control Circuit (IOC) 8 input / output device (IO) 9 selector circuit (SL) 10 write-back control circuit (WBC) 11 cache memory circuit (CM) 12 processor interface control circuit (CPI) 13 fault detection / collection means (ED) 14 OR circuit (OR) ) 15 flip-flops (FF)

Claims (2)

[Claims] 1. In a faulty memory data transfer control method in a processor system in which a duplicated central processing unit of 0-system and 1-system secures the sameness of memory data of both systems, a microprocessor for executing a program and a cache. A control circuit, a main memory, a dual write circuit for writing double to the main memory, a fault detection circuit for detecting a fault in the own system, an address / data from the cache control circuit, and the duplicate Address from write circuit /
A failure memory data transfer control method, comprising: a selector circuit for selecting data and outputting it to an interface section with another system memory. 2. The fault detection circuit, writeback instructing means for instructing and displaying writeback by activating software or hardware, switching instructing means for instructing switching to the selector circuit, and writeback completion to the microprocessor. Write back completion notifying means for notifying,
A failure notification means for monitoring the write-back operation and notifying the failure of its own system to the other system when there is a failure, and the cache control circuit updates the cache data when the write-back instruction is received, so that the contents of the memory 2. A write-back control circuit for autonomously writing back only data different from the above, and a cache memory circuit for storing the cache data and directory information and supporting a copy-back cache. Faulty memory data transfer control method.