JPH0669070B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0669070B2 JPH0669070B2 JP60171519A JP17151985A JPH0669070B2 JP H0669070 B2 JPH0669070 B2 JP H0669070B2 JP 60171519 A JP60171519 A JP 60171519A JP 17151985 A JP17151985 A JP 17151985A JP H0669070 B2 JPH0669070 B2 JP H0669070B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode wiring
- wiring layer
- recess
- layer
- lower electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は高速・高周波動作の可能な半導体装置、特には
多層配線を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of high-speed and high-frequency operation, and particularly to a semiconductor device having multi-layer wiring.
従来の技術 導体装置の動作速度の向上に伴い、半導体装置を構成す
る半導体素子間を結ぶ電極配線による伝搬速度の遅延が
問題となってきている。特に半導体素子のパターンの微
細化に伴って、半導体素子のゲート容量と多層電極配線
相互の層間容量とが同程度になりつつあり、層間容量に
基因する伝搬速度の遅延の問題が顕著になっている。2. Description of the Related Art With the increase in operating speed of conductor devices, delay in propagation speed due to electrode wiring connecting semiconductor elements forming a semiconductor device has become a problem. In particular, with the miniaturization of the pattern of the semiconductor element, the gate capacitance of the semiconductor element and the inter-layer capacitance between the multilayer electrode wirings are becoming approximately the same, and the problem of the delay of the propagation speed due to the inter-layer capacitance becomes remarkable. There is.
層間容量を減少する方法としては、多層電極配線間の層
間絶縁膜として誘電率の小さい絶縁膜たとえばポリイミ
ド樹脂を用いる方法、層間絶縁膜を厚くする方法などが
検討されている。最近では層間容量をさらに減少するた
めに、層間絶縁膜として誘電率ε＝１の空気を用いたエ
アーブリッジ法が検討されている。As a method of reducing the interlayer capacitance, a method of using an insulating film having a small dielectric constant, for example, a polyimide resin as an interlayer insulating film between the multilayer electrode wirings, a method of thickening the interlayer insulating film, and the like are being studied. Recently, in order to further reduce the interlayer capacitance, an air bridge method using air having a dielectric constant ε = 1 as an interlayer insulating film has been studied.
第３図に従来のエアーブリッジ法を示す。11はGaAs半導
体基板、12は１層目の電極配線、13はSi3N4膜、14は１
層目の電極配線12と２層目の電極配線15との接続用のコ
ンタクト電極である。１層目の電極配線12と２層目の電
極配線15との間の層間絶縁膜としては空気が用いられて
おり、またそれらの間隔はコンタクト電極14の厚さによ
って規定されている。従来のエアーブリッジ法では層間
絶縁膜として空気を用いているので層間容量が小さく、
したがって半導体装置の高速動作が可能となる。FIG. 3 shows a conventional air bridge method. 11 is a GaAs semiconductor substrate, 12 is the electrode wiring of the first layer, 13 is a Si 3 N 4 film, and 14 is 1.
It is a contact electrode for connecting the electrode wiring 12 of the second layer and the electrode wiring 15 of the second layer. Air is used as an interlayer insulating film between the first-layer electrode wiring 12 and the second-layer electrode wiring 15, and the distance between them is defined by the thickness of the contact electrode 14. In the conventional air bridge method, since air is used as the interlayer insulating film, the interlayer capacitance is small,
Therefore, the semiconductor device can operate at high speed.
発明が解決しようとする問題点 第３図に示した従来のエアーブリッジ法においては、２
層目の電極配線15が層間部でGaAs基板11から離れて中空
に浮いて形成されているため以下に示すような問題点が
生じる。まず第１の問題点は１層目の電極配線と２層目
の電居配線の短絡が発生し易いことである。機械的振動
あるいは熱的な影響などにより２層目の電極配線がたれ
下がってきて、１層目の電極配線と接触とし電気的に短
絡する。Problems to be Solved by the Invention In the conventional air bridge method shown in FIG.
Since the electrode wiring 15 of the layer is formed so as to be separated from the GaAs substrate 11 and float in the air in the interlayer portion, the following problems occur. First, the first problem is that a short circuit between the electrode wiring of the first layer and the live wiring of the second layer is likely to occur. The electrode wiring of the second layer hangs down due to mechanical vibration, thermal influence, or the like, making contact with the electrode wiring of the first layer and electrically short-circuiting.
２番目の問題点はチップ面積が大きくなることである。
前述したように機械的振動あるいは熱的な影響などによ
り１層目の電極配線と２層目の電極配線との短絡が生じ
る。この短絡は２層目の電極配線のブリッジ部分が長い
程顕著に生じる。短絡の発生を軽減するため第３図に示
しているようにブリッジ部分の所定の長さごとにポスト
となるコンタクト電極14を形成することが考えられてい
る。このようにするとブリッジ部分の長さを所定の長さ
（通常は20〜30μｍ程度）以下にしつつ、全体のブリツ
ジの長さを任意に長くすることができ、しかも短絡の発
生を軽減することができる。しかし20〜30μｍおきにポ
ストを設けなければならずチップ面積が約50％増加す
る。The second problem is that the chip area becomes large.
As described above, a short circuit occurs between the first-layer electrode wiring and the second-layer electrode wiring due to mechanical vibration or thermal influence. This short circuit is more remarkable as the bridge portion of the second-layer electrode wiring is longer. In order to reduce the occurrence of short circuit, it has been considered to form a contact electrode 14 to be a post for each predetermined length of the bridge portion as shown in FIG. By doing so, the length of the bridge portion can be set to a predetermined length (usually about 20 to 30 μm) or less, and the length of the entire bridge can be arbitrarily increased, and the occurrence of short circuit can be reduced. it can. However, posts must be provided every 20 to 30 μm, which increases the chip area by about 50%.
３番目の問題点は半導体基板の裏面のラッピング後およ
びチップ分割後の歩留まりが極めて悪いことである。ダ
イヤモンドスクライバーを用いて半導体基板をチップ状
に分割しクラッキングする際、半導体基板の表面に圧力
が加わりそれにより２層目の電極配線が１層目の電極配
線に短絡しチップ歩留まりは数％であった。また半導体
基板の裏面のラッピングの際にも同様に短絡が発生しチ
ップ歩留まりは数％であった。したがって良品のチップ
を含む半導体基板を前述のような後工程処理を行なった
後はチップ歩留まりはほぼ０％であり、良品のチップを
得るのは非常に困難であった。The third problem is that the yield after lapping the back surface of the semiconductor substrate and after chip division is extremely low. When the semiconductor substrate is divided into chips using a diamond scriber and cracked, pressure is applied to the surface of the semiconductor substrate, which shorts the electrode wiring of the second layer to the electrode wiring of the first layer, resulting in a chip yield of several percent. It was Similarly, a short circuit occurred when lapping the back surface of the semiconductor substrate, and the chip yield was several percent. Therefore, after subjecting the semiconductor substrate including the non-defective chip to the above-mentioned post-process, the chip yield was almost 0%, and it was very difficult to obtain the non-defective chip.
問題点を解決するための手段 本発明は前述の問題点を解決するためになされたもので
あり、本発明の半導体装置は、半導体基板と、半導体基
板の主面に少なくとも２層以上の多層電極配線層と、半
導体基板の主面の電極配線層の交差部に対向した一対の
メサ形状面と対向した一対の逆メサ形状面とからなる凹
部とを有し、半導体基板の主面から交差部のメサ形状面
と凹部の底面にわたって下層電極配線層が形成されてお
り、下層電極配線層と交差するように逆メサ形状面の上
部の半導体基板の主面から凹部の上面を横切って上層電
極配線層が形成されており、凹部に形成された下層電極
配線層と上層電極配線層とが少なくとも気体あるいは真
空によって絶縁されている構成よりなる半導体装置であ
る。Means for Solving the Problems The present invention has been made in order to solve the above-mentioned problems, and a semiconductor device of the present invention has a semiconductor substrate and a multilayer electrode having at least two layers on the main surface of the semiconductor substrate. The wiring layer and a recess having a pair of mesa-shaped surfaces facing the intersection of the electrode wiring layer on the main surface of the semiconductor substrate and a pair of opposite mesa-shaped surfaces facing each other are provided, and the intersection from the main surface of the semiconductor substrate. The lower electrode wiring layer is formed across the mesa-shaped surface and the bottom surface of the recess, and the upper-layer electrode wiring is crossed from the main surface of the semiconductor substrate above the reverse mesa-shaped surface to the upper surface of the recess so as to intersect with the lower electrode wiring layer. The semiconductor device has a layer formed, and the lower electrode wiring layer and the upper electrode wiring layer formed in the recess are insulated at least by gas or vacuum.
作 用 本発明の半導体装置においては多層電極配線層の交差部
に一対のメサ形状と一対の逆メサ形状を有する凹部を有
し、そのメサ形状を通って凹部の底面にわたって下層電
極配線層が形成されており、下層電極配線層に交差する
ように半導体基板の表面には凹部の上を横切って上層電
極配線層が形成されている。下層電極配線層は凹部の底
面に、上層電極配線層は凹部の表面に形成されており、
しかも上層電極配線層が横切る凹部の幅はその断面形状
が逆メサ形状となっているため狭く、したがって機械的
振動あるいは熱的影響などにより上層電極配線層がたれ
下がるということはない。また下層電極配線層はメサ形
状面および凹部の底面に形成されているため、下層電極
配線層の断線も生じない。Operation In the semiconductor device of the present invention, a recess having a pair of mesa shapes and a pair of inverted mesa shapes is formed at the intersection of the multilayer electrode wiring layers, and the lower electrode wiring layer is formed through the mesa shape and over the bottom surface of the recesses. An upper electrode wiring layer is formed on the surface of the semiconductor substrate so as to cross the lower electrode wiring layer and across the recess. The lower electrode wiring layer is formed on the bottom surface of the recess, and the upper electrode wiring layer is formed on the surface of the recess.
Moreover, the width of the recess traversed by the upper electrode wiring layer is narrow because the cross-sectional shape is an inverted mesa shape, and therefore the upper electrode wiring layer does not sag due to mechanical vibration or thermal influence. Further, since the lower electrode wiring layer is formed on the mesa-shaped surface and the bottom surface of the concave portion, disconnection of the lower electrode wiring layer does not occur.
本発明の半導体装置においては上層電極配線層が横切る
電極配線層の交差部の凹部の幅は下層電極配線層の幅と
同程で良く、しかもその幅はたとえば３μｍ程度と狭い
ので従来のエアーブリッジ法で示したようなポストは設
ける必要がない。また凹部をたとえば３μｍのくり返し
で複数形成することができ、その際にもポストは必要で
ないので従来のエアーブリッジ法を用いない半導体装置
と同一のチップ面積にすることができ、従来のエアーブ
リッジ法を用いた場合と比較してチップ面積を約30％減
少することができる。In the semiconductor device of the present invention, the width of the recess at the intersection of the electrode wiring layers traversed by the upper electrode wiring layer may be as large as the width of the lower electrode wiring layer, and the width is narrow, for example, about 3 μm. It is not necessary to provide a post as indicated by law. Further, it is possible to form a plurality of recesses by repeating 3 μm, for example, and no post is required at that time, so that the chip area can be made the same as that of the semiconductor device not using the conventional air bridge method. The chip area can be reduced by about 30% as compared with the case of using.
さらに本発明の半導体装置では凹部の上に形成されてい
る上層電極配線層は平坦な構造となっているため、半導
体基板の裏面のラッピング工程およびスクライブ工程に
おいても、半導体基板の表面からの圧力などによって上
層電極配線層が凹部内にたれ下がって、凹部底面に形成
されている下層電極配線層と接触し、短絡を起こすとい
うこともない。Further, in the semiconductor device of the present invention, since the upper electrode wiring layer formed on the concave portion has a flat structure, even in the lapping step and the scribing step of the back surface of the semiconductor substrate, pressure from the front surface of the semiconductor substrate, etc. Therefore, the upper electrode wiring layer does not hang down in the recess and contact with the lower electrode wiring layer formed on the bottom surface of the recess to cause a short circuit.
上層電極配線層と下層電極配線層とは凹部で交差してお
り、その層間絶縁物としては空気，窒素，アルゴンなど
の気体あるいは真空であるのでその層間容量は非常に小
さく、したがって高速・高周波動作の可能な半導体装置
が信頼性高く、また歩留まり良く実現できる。The upper electrode wiring layer and the lower electrode wiring layer intersect at a recess, and the interlayer insulator is a gas such as air, nitrogen, or argon, or a vacuum, so that the interlayer capacitance is very small, and therefore high-speed / high-frequency operation is possible. It is possible to realize a semiconductor device having high reliability and high yield.
実施例 以下実施例を用いて本発明を詳細に説明する。第１図は
本発明の第１の実施例における半導体装置の平面図ａお
よび断面図b,cである。第１図ａで21はGaAs半導体基
板、22は多層電極配線層の交差部に設けられた深さ１μ
ｍの凹部、23は凹部の〔０〕方向の辺、24は〔０
１〕方向の辺を表わしている。25は〔０〕方向に形
成されている電源配線，接地配線として用いた３μｍ幅
の下層電極配線層、26は〔０１〕方向に形成されてい
る信号配線として用いた３μｍ幅の上層電極配線層であ
る。凹部22で下層電極配線層25と上層電極配線層26とは
交差している。第１図ｂはａのＡ−Ａ′方向の断面図を
示しており、凹部22の側面には（111）面のメサ形状28
が形成されている。下層電極配線層25はGaAs半導体基板
21の表面27からメサ形状28を通って、さらに凹部の底面
29、メサ形状28′を通って配線されている。一方上層電
極配線層26は凹部22の上に間隔をあけて形成されてい
る。EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 1 is a plan view a and sectional views b and c of a semiconductor device according to a first embodiment of the present invention. In FIG. 1a, 21 is a GaAs semiconductor substrate, 22 is a depth of 1 μ provided at the intersection of the multilayer electrode wiring layers.
m is a concave portion, 23 is a side of the concave portion in the [0] direction, and 24 is a [0] side.
1] represents the side of the direction. Reference numeral 25 is a lower electrode wiring layer having a width of 3 μm used as a power supply wiring and ground wiring formed in the [0] direction, and 26 is an upper electrode wiring layer having a width of 3 μm used as a signal wiring formed in a [01] direction. Is. In the recess 22, the lower electrode wiring layer 25 and the upper electrode wiring layer 26 intersect. FIG. 1b is a sectional view taken along the line AA 'in FIG. 1a, in which the (111) plane mesa shape 28 is formed on the side surface of the recess 22.
Are formed. The lower electrode wiring layer 25 is a GaAs semiconductor substrate
From the surface 27 of 21 through the mesa shape 28 to the bottom of the recess
It is wired through 29 and the mesa shape 28 '. On the other hand, the upper electrode wiring layer 26 is formed on the recess 22 with a space.
第１図ｃはａのＢ−Ｂ′方向の断面図であり、凹部22の
側面は逆メサ形状30となっている。凹部のＢ−Ｂ′〔０
１〕方向のパターン幅は本実施例では５μｍとしてい
るが、３μｍと下層電極配線層25のパターン幅と同一寸
法にしても良い。第１図a,bおよびｃより明らかなよう
に上層電極配線層26が凹部22を横切る幅は狭く、また上
層電極配線層26はほぼ同一平面上に平坦に形成されてい
るため上層電極配線層と下層電極配線層との電気的短絡
はなく、さらに凹部の〔０〕方向の辺の長さは下層電
極配線層のパターン幅と同程度にすることができるので
チップ面積の減少が図れ、また後工程処理などによるチ
ップ歩留まりの減少がなくしたがって歩留まりの向上が
図れる。第１の実施例で半導体装置としてGaAsゲートア
レーを製作した結果、後工程処理による歩留まりの低下
はなく、ゲートアレーのチップ歩留まりは80％であっ
た。さらに、下層電極配線層は上層電極配線との交差部
分では基板表面よりも下側に位置しているものの、その
他の部分では基板表面上にあるため、容易にその後の表
面配線層との電気的接合を行うことができる。また、下
層電極配線層と表面配線層との接合工程のための領域を
省略することができる。FIG. 1c is a sectional view taken along the line BB 'of FIG. BB '[0 of the recess
The pattern width in the 1] direction is 5 μm in this embodiment, but may be 3 μm, which is the same as the pattern width of the lower electrode wiring layer 25. As is clear from FIGS. 1A, 1B and 1C, the width of the upper electrode wiring layer 26 across the recess 22 is narrow, and the upper electrode wiring layer 26 is formed flat on substantially the same plane. There is no electrical short circuit between the lower electrode wiring layer and the lower electrode wiring layer, and the length of the side of the recess in the [0] direction can be made approximately the same as the pattern width of the lower electrode wiring layer, so that the chip area can be reduced. There is no reduction in the chip yield due to post-processes, and therefore the yield can be improved. As a result of manufacturing a GaAs gate array as a semiconductor device in the first embodiment, the yield of the gate array did not decrease due to the post-process, and the chip yield of the gate array was 80%. Further, the lower electrode wiring layer is located below the substrate surface at the intersection with the upper electrode wiring, but is located on the substrate surface at other portions, so that the electrical connection with the surface wiring layer after that is easily performed. Bonding can be done. Further, the region for the step of joining the lower electrode wiring layer and the surface wiring layer can be omitted.
第２図は本発明の第２の実施例を示す図である。第２の
実施例では上層電極配線層を３本（26a,26b,26c）と
し、ひとつの凹部で３本の信号配線用上層電極配線層と
電源配線，接地配線用の下層電極配線層が交差する構成
とした。第１図と同一箇所は同一の番号で示している。
第２の実施例では３μｍ幅の３本の信号配線用上層電極
配線層26a,26b,26cが５μｍの間隔をおいて凹部の上に
形成されている。凹部の〔０１〕方向の幅は５μｍで
あり、ひとつの凹部を横切って複数の上層電極配線層を
形成することが可能である。第２の実施例でも第１の実
施例と同様な効果が得られ、第１の実施例よりさらにチ
ップ面積の減少が図れた。FIG. 2 is a diagram showing a second embodiment of the present invention. In the second embodiment, the upper electrode wiring layers are three (26a, 26b, 26c), and one recess crosses three upper wiring layers for signal wiring and lower wiring layers for power wiring and ground wiring. It was configured to do. The same parts as those in FIG. 1 are indicated by the same numbers.
In the second embodiment, three signal wiring upper electrode wiring layers 26a, 26b and 26c having a width of 3 .mu.m are formed on the recesses at intervals of 5 .mu.m. The width of the recess in the [01] direction is 5 μm, and it is possible to form a plurality of upper electrode wiring layers across one recess. In the second embodiment, the same effect as in the first embodiment was obtained, and the chip area was further reduced as compared with the first embodiment.
以上の第１および第２の実施例では基板としてGaAs半導
体基板を用いたが、何ら限定されるものではなくSi半導
体基板でも良く、また他の化合物半導体基板でも良い。
また下層電極配線層を電源配線，接地配線として、上層
電極配線層を信号配線として用いたが、回路素子のレイ
アウト上前記実施例のようにした方が一般的にはチップ
面積が小さくなるので好ましい。しかしながら種々の回
路においては上層の信号配線と下層の電源配線・信号配
線の電極配線層を逆にした方が良い場合もあり、また混
在した方が良い場合もあり特に限定されるものではな
い。Although the GaAs semiconductor substrate is used as the substrate in the above first and second embodiments, it is not limited at all and may be a Si semiconductor substrate or another compound semiconductor substrate.
Although the lower electrode wiring layer is used as the power wiring and the ground wiring and the upper electrode wiring layer is used as the signal wiring, it is generally preferable to use the above-mentioned embodiment in view of the layout of the circuit element because the chip area becomes smaller. . However, in various circuits, it may be better to reverse the electrode wiring layers of the upper-layer signal wiring and the lower-layer power supply wiring / signal wiring, and it may be better to mix them, and there is no particular limitation.
凹部を〔０１〕方向に並行して複数本形成することに
より複数本の下層電極配線層と複数本の上層電極配線層
の交差を面積効率良く形成することができる。By forming a plurality of recesses in parallel in the [01] direction, the intersections of the plurality of lower electrode wiring layers and the plurality of upper electrode wiring layers can be formed with high area efficiency.
凹部の形状としては下層電極配線層が〔０〕方向に
形成され、〔０〕方向にメサ形状面を形成しておく
必要があるため、〔０〕方向の辺の長さが〔０
１〕方向の辺の長さより長い長方形の形状をしている方
が好ましい。前述の辺の長さを等しくすると凹部の上を
横切る上層電極配線層の凹部上での長さが長くなり、そ
の分だけ信頼性が低下すると考えられる。As for the shape of the recess, the lower electrode wiring layer is formed in the [0] direction, and it is necessary to form the mesa-shaped surface in the [0] direction. Therefore, the length of the side in the [0] direction is [0].
1) It is preferable that the shape of the rectangle is longer than the length of the side. If the lengths of the aforementioned sides are made equal, the length of the upper electrode wiring layer that traverses over the recess becomes longer on the recess, and it is considered that the reliability decreases accordingly.
また前述の実施例では上層と下層の電極配線層の２層構
造のみを示したが、一般的には２層以上からなる多層配
線層に本発明を適用することができる。複数の上層電極
配線層を複数の層からなる複数の電極配線層とすると、
たとえばゲートアレイなどを構成する場合上層の電極配
線層のフォトマスクを変えるのみで容易にゲートアレイ
を構成できるのでロジックの変更が容易となる。Further, in the above-mentioned embodiments, only the two-layer structure of the upper and lower electrode wiring layers is shown, but the present invention can be applied to a multilayer wiring layer which is generally composed of two or more layers. If the upper electrode wiring layers are a plurality of electrode wiring layers composed of a plurality of layers,
For example, when a gate array or the like is formed, the gate array can be easily formed only by changing the photomask of the upper electrode wiring layer, so that the logic can be easily changed.
さらに実施例では上層電極配線層と、下層電極配線層と
が直交している例を示したが、これも何ら限定されるも
のではなく下層電極配線層に対して上層電極配線層が、
あるいはその一部が斜めに交差しても良い。Furthermore, in the embodiment, the upper electrode wiring layer and the lower electrode wiring layer are shown as being orthogonal to each other, but the present invention is not limited to this, and the upper electrode wiring layer is lower than the lower electrode wiring layer.
Alternatively, some of them may cross at an angle.
発明の効果 以上の実施例より明らかなように、本発明の半導体装置
では下層電極配線層を半導体基板内の凹部に形成し、そ
の凹部の上を上層電極配線層が同一平面上に平坦に形成
されている。それ故機械的振動あるいは熱的影響などに
より上層電極配線層が下層電極配線層と短絡することが
なく、チップ面積の減少も図れる。また、下層電極配線
層は上層電極配線との交差部分では基板表面よりも下側
に位置しているが、その他の部分では基板表面上にある
ため、容易にその後の表面配線層との電気的接合を行う
ことができる。また、下層電極配線層と表面配線層との
接合工程のための領域を省略することができる。さらに
後工程等による歩留まりの低下もなく、したがって高速
・高周波動作に適した半導体装置を信頼性高く、また歩
留まり良く実現することができる。EFFECTS OF THE INVENTION As is clear from the above examples, in the semiconductor device of the present invention, the lower electrode wiring layer is formed in the concave portion in the semiconductor substrate, and the upper electrode wiring layer is formed flat on the same plane above the concave portion. Has been done. Therefore, the upper electrode wiring layer does not short-circuit with the lower electrode wiring layer due to mechanical vibration or thermal influence, and the chip area can be reduced. Also, the lower electrode wiring layer is located below the substrate surface at the intersection with the upper electrode wiring, but it is on the substrate surface at other portions, so that it is easy to electrically connect with the surface wiring layer after that. Bonding can be done. Further, the region for the step of joining the lower electrode wiring layer and the surface wiring layer can be omitted. Further, there is no decrease in yield due to post-processes, etc. Therefore, a semiconductor device suitable for high-speed / high-frequency operation can be realized with high reliability and high yield.
第１図ａは本発明の第１の実施例における半導体装置の
平面図、第１図ｂは第１図ａのＡ−Ａ′線断面図、第１
図ｃは第１図ａのＢ−Ｂ′線断面図、第２図ａは本発明
の第２の実施例における半導体装置の平面図、第２図ｂ
は第２図ａのＡ−Ａ′線断面図、第２図ｃは第２図ａの
Ｂ−Ｂ′線断面図、第３図は従来のエアーブリッジ法を
説明するための半導体装置の断面図である。 21……GaAs半導体基板、22……凹部、25……下層電極配
線層、26……上層電極配線層。1a is a plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1b is a sectional view taken along the line AA 'of FIG. 1a.
FIG. C is a sectional view taken along the line BB ′ of FIG. 1a, FIG. 2a is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 2b.
2A is a sectional view taken along the line AA ′ in FIG. 2A, FIG. 2C is a sectional view taken along the line BB ′ in FIG. 2A, and FIG. 3 is a sectional view of a semiconductor device for explaining the conventional air bridge method. It is a figure. 21 ... GaAs semiconductor substrate, 22 ... recess, 25 ... lower electrode wiring layer, 26 ... upper electrode wiring layer.
Claims (10)
なくとも２層以上の多層電極配線層と、前記半導体基板
の主面の電極配線層の交差部に対向した一対のメサ形状
面と対向した一対の逆メサ形状面とからなる凹部とを備
え、前記半導体基板の主面から前記交差部の前記メサ形
状面と前記凹部の底面にわたって下層電極配線層が形成
されており、前記下層電極配線層と交差するように前記
逆メサ形状面の上部の半導体基板の主面から前記凹部の
上面を横切って前記下層配線層よりも少なくとも上層の
上層電極配線層が形成されており、前記凹部の前記下層
電極配線層と前記上層電極配線層とが少なくとも気体あ
るいは真空によって絶縁されている半導体装置。1. A semiconductor substrate, at least two or more multi-layer electrode wiring layers on the main surface of the semiconductor substrate, and a pair of mesa-shaped surfaces facing the intersection of the electrode wiring layers on the main surface of the semiconductor substrate. A pair of reverse mesa-shaped surfaces, and a lower electrode wiring layer is formed from the main surface of the semiconductor substrate to the mesa-shaped surface at the intersection and the bottom surface of the recess. An upper electrode wiring layer at least above the lower wiring layer is formed across the upper surface of the recess from the main surface of the semiconductor substrate above the inverted mesa-shaped surface so as to intersect the layer, and the recess of the recess is formed. A semiconductor device in which the lower electrode wiring layer and the upper electrode wiring layer are insulated from each other by at least gas or vacuum.
置配線として用いられ、上層電極配線層が少なくとも信
号配線として用いられている特許請求の範囲第１項記載
の半導体装置。2. The semiconductor device according to claim 1, wherein the lower electrode wiring layer of the recess is used as an electrode wiring and an installation wiring, and the upper electrode wiring layer is used as at least a signal wiring.
上の電極配線層よりなる特許請求の範囲第１項記載の半
導体装置。3. The semiconductor device according to claim 1, wherein the upper electrode wiring layer of the recess is made up of at least two electrode wiring layers.
り上層の少なくとも２層以上の複数の電極配線層よりな
る特許請求の範囲第１項記載の半導体装置。4. The semiconductor device according to claim 1, wherein the upper electrode wiring layer of the recess comprises a plurality of electrode wiring layers of at least two layers above the lower electrode wiring layer.
（100）面に少なくとも２層以上の多層電極配線層と、
前記半導体基板の主面の電極配線層の交差部に〔０
〕方向と〔０１〕方向とよりなる凹部との備え、前
記凹部の〔０〕方向には少なくとも（111）面より
なるメサ形状面を、前記凹部の〔０１〕方向には少な
くとも（111）面よりなる逆メサ形状面を、前記凹部の
底面には（100）面とを有し、前記半導体基板の主面か
ら前記交差部の前記メサ形状面と前記凹部の底面にわた
って略〔０〕方向に下層電極配線層が形成されてお
り、前記下層電極配線層と交差するように前記逆メサ形
状面の上部の半導体基板の主面から前記凹部の上面を横
切って前記下層電極配線層よりも少なくとも上層の上層
電極配線層が形成されており、前記凹部の前記下層電極
配線層と前記上層電極配線層とが少なくとも気体あるい
は真空によって絶縁されている半導体装置。5. A semiconductor substrate, and at least two or more multi-layer electrode wiring layers on the (100) plane of the main surface of the semiconductor substrate,
At the intersection of the electrode wiring layers on the main surface of the semiconductor substrate, [0
] And a [01] direction are provided, and a mesa-shaped surface having at least a (111) plane is formed in the [0] direction of the depression and at least a (111) plane is formed in the [01] direction of the depression. A bottom surface of the recess having a (100) surface, and extending in an approximately [0] direction from the main surface of the semiconductor substrate to the mesa surface of the intersection and the bottom surface of the recess. A lower electrode wiring layer is formed, and the lower electrode wiring layer is formed so as to cross the lower electrode wiring layer and across the upper surface of the recessed portion from the main surface of the semiconductor substrate above the inverted mesa-shaped surface to at least an upper layer than the lower electrode wiring layer. A semiconductor device in which an upper electrode wiring layer is formed, and the lower electrode wiring layer in the recess is insulated from the upper electrode wiring layer by at least gas or vacuum.
が〔０１〕方向の辺の長さより長い長方形の形状を有
している特許請求の範囲第５項記載の半導体装置。6. The semiconductor device according to claim 5, wherein the recess has a rectangular shape in which the length of the side in the [0] direction of the recess is longer than the length of the side in the [01] direction.
地配線として用いられ、上層電極配線層が少なくとも信
号配線として用いられている特許請求の範囲第５項記載
の半導体装置。7. The semiconductor device according to claim 5, wherein the lower electrode wiring layer of the recess is used as a power wiring and a ground wiring, and the upper electrode wiring layer is used as at least a signal wiring.
電極配線層よりなる特許請求の範囲第５項記載の半導体
装置。8. The semiconductor device according to claim 5, wherein the upper wiring layer of the concave portion is composed of at least two electrode wiring layers.
り上層の少なくとも２層以上の複数の電極配線層よりな
る特許請求の範囲第５項記載の半導体装置。9. The semiconductor device according to claim 5, wherein the upper electrode wiring layer of the recess comprises a plurality of electrode wiring layers of at least two layers above the lower electrode wiring layer.
いて、さらに前記凹部に下層電極配線層が形成されてい
る特許請求の範囲第５項記載の半導体装置。10. The semiconductor device according to claim 5, wherein a plurality of recesses are formed in the [01] direction, and the lower electrode wiring layer is formed in the recesses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60171519A JPH0669070B2 (en) | 1985-08-02 | 1985-08-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60171519A JPH0669070B2 (en) | 1985-08-02 | 1985-08-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6231143A JPS6231143A (en) | 1987-02-10 |
| JPH0669070B2 true JPH0669070B2 (en) | 1994-08-31 |
Family
ID=15924619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60171519A Expired - Lifetime JPH0669070B2 (en) | 1985-08-02 | 1985-08-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669070B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2024202799A1 (en) * | 2023-03-31 | 2024-10-03 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS498192A (en) * | 1972-05-10 | 1974-01-24 | ||
| JPS6037149A (en) * | 1983-08-09 | 1985-02-26 | Fujitsu Ltd | Semiconductor device |
-
1985
- 1985-08-02 JP JP60171519A patent/JPH0669070B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6231143A (en) | 1987-02-10 |
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