JPH0669098B2 - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPH0669098B2 JPH0669098B2 JP61013105A JP1310586A JPH0669098B2 JP H0669098 B2 JPH0669098 B2 JP H0669098B2 JP 61013105 A JP61013105 A JP 61013105A JP 1310586 A JP1310586 A JP 1310586A JP H0669098 B2 JPH0669098 B2 JP H0669098B2
- Authority
- JP
- Japan
- Prior art keywords
- drain
- insulating film
- wiring
- transparent conductive
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 本発明は、半導体薄膜の形成方法に関し、特に透明導電
膜上に半導体薄膜を形成する方法に関する。The present invention relates to a method for forming a semiconductor thin film, and more particularly to a method for forming a semiconductor thin film on a transparent conductive film.
ITO等に代表される透明導電膜は、その可視光透過性、
低抵抗性の故、液晶ディスプレイ駆動用薄膜トランジス
タ、イメージセンサーなどの電極として用いられる。A transparent conductive film typified by ITO has a visible light transmittance,
Because of its low resistance, it is used as an electrode for liquid crystal display driving thin film transistors, image sensors and the like.
第３図は順スタガー型と呼ばれるアモルファスシリコン
（ａ−Siと以下略す）薄膜トランジスタ（以下TFTと略
す）の断面図を示しており、この薄膜トランジスタは以
下の工程によって作成される。ドレインおよびソース電
極（画素電極）となる透明導電膜１をガラス基板上に形
成し、次にオーミックコンタクトをとるためのｎ＋−ａ
−Ｓｉ層４を形成し、ドレイン・ソースのパターンニン
グの後、n+−ａ−Si層４および透明導電膜１のエッチン
グを行ってドレインおよびソース電極を形成し、次に活
性層となるｉ−ａ−Si層５、ゲート絶縁膜６、ゲート電
極７の成膜を行ない、ゲート電極７のパターンニングの
後、ゲート電極７、ゲート絶縁膜6,iおよびｎ＋ａ−Ｓ
ｉのエッチングを行なう。FIG. 3 is a cross-sectional view of an amorphous silicon (a-Si) TFT (hereinafter abbreviated as TFT) called a forward stagger type, which is manufactured by the following steps. A transparent conductive film 1 to be drain and source electrodes (pixel electrodes) is formed on a glass substrate, and then n + -a for making ohmic contact.
Forming a -S i layer 4, after the patterning of the drain-source, and a drain and source electrodes by etching of the n + -a-Si layer 4 and the transparent conductive film 1, then the active layer After the ia-Si layer 5, the gate insulating film 6 and the gate electrode 7 are formed and the gate electrode 7 is patterned, the gate electrode 7, the gate insulating films 6, i and n + a-S are formed.
i is etched.
このプロセスにおいて、ｎ＋−ａ−Ｓｉ4,i−ａ−Ｓ
ｉ5,ゲート絶縁膜６は基板として安価なソーダガラスを
用いられる様に、低温で薄膜形成が可能ナプラズマCVD
法によって形成される。In this process, n + -a-S i 4, i-a-S
i 5, The gate insulating film 6 can be formed into a thin film at low temperature just like cheap soda glass is used as a substrate. Na plasma CVD
Formed by the method.
上述した従来の薄膜トランジスタのドレイン・ソース電
極部は、一様に存在する透明導電膜上にｎ＋−ａ−Ｓｉ
層を形成するため、形成時に透明導電膜の構成原子であ
るIn,Snがプラズマのスパッタ作用により多量にｎ＋−
ａ−Ｓｉ層に取り込まれることが確認されており、デバ
イスの性能を劣化させる要因となる。Drain and source electrodes of the conventional thin film transistor described above, uniformly n + -a-S i on the transparent conductive film present
In order to form a layer, a large amount of In + Sn, which is a constituent atom of the transparent conductive film, is formed by the plasma sputtering action during formation.
It has been confirmed to be incorporated into the a- Si layer, which becomes a factor that deteriorates the performance of the device.
さらにｎ＋−ａ−Ｓｉ中にIn,Sn等が混入するとその度
合によりｎ＋−ａ−Ｓｉ層のエッチングレートが変化し
エッチングプロセスの制御性を低下させるという欠点が
ある。There is a disadvantage that further reduce In, the control of the etching rate changes and the etch process n + -a-S i layer by the degree the Sn or the like is mixed into the n + -a-S i.
本発明の薄膜半導体素子は、ガラス基板上のドレイン配
線及びソース配線を形成する透明導電膜と、少なくとも
透明導電膜を覆うようにガラス基板上の全面に被着した
絶縁膜と、絶縁膜上の真性アモルファスシリコン層を活
性層とし、活性層上にゲート酸化膜とゲート電極とを有
する薄膜半導体素子とを有し、ドレイン配線と活性層に
形成されたドレイン領域及びソース配線と活性層に形成
されたソース領域とは、絶縁膜のドレイン配線及びソー
ス配線上に設けた開口部で不純物を含んだアモルファス
シリコン層を介して各々接続され、ゲート電極がドレイ
ン配線及びソース配線を横切るように延在されているこ
とを特徴とする。The thin film semiconductor device of the present invention comprises a transparent conductive film forming a drain wiring and a source wiring on a glass substrate, an insulating film deposited on the entire surface of the glass substrate so as to cover at least the transparent conductive film, and an insulating film on the insulating film. An intrinsic amorphous silicon layer is used as an active layer, and a thin film semiconductor element having a gate oxide film and a gate electrode is formed on the active layer. The drain wiring and the drain region formed in the active layer and the source wiring and the active layer are formed. The drain region of the insulating film and the source region are connected to each other through an amorphous silicon layer containing impurities at an opening provided on the insulating film and the gate electrode extends so as to cross the drain line and the source line. It is characterized by
第１図は、本発明の一実施例の順スタガー型TFTの断面
図である。透明導電膜１の上に絶縁膜２が設けられてい
る。TFTのドレインおよびソース電極部には、絶縁膜２
にコンタクトホール３があけられており、絶縁膜２上に
ｎ＋−ａ−Ｓｉ層４が積層され、コンタクトホール３の
部分で透明導電膜１と電気的接触がとられる。FIG. 1 is a sectional view of a forward stagger type TFT according to an embodiment of the present invention. The insulating film 2 is provided on the transparent conductive film 1. An insulating film 2 is formed on the drain and source electrodes of the TFT.
The contact hole 3 is formed in the contact hole 3, the n + -a- Si layer 4 is laminated on the insulating film 2, and the transparent conductive film 1 is electrically contacted at the contact hole 3.
第２図はコンタクトホールの位置を示す平面図であり、
ドレイン配線部９およびソース配線部のうちTFTのドレ
インおよびソース電極部となる斜線部の位置にのみコン
タクトホールがもうけられている。FIG. 2 is a plan view showing the positions of contact holes,
A contact hole is provided only in the positions of the hatched portions that will be the drain and source electrode portions of the TFT in the drain wiring portion 9 and the source wiring portion.
以上説明したように本発明は、透明導電膜をもうけ電気
的な接触の必要な個所にコンタクトホールをあけ、その
後半導体膜を成膜することにより、半導体膜成膜時にプ
ラズマにさらされる透明導電膜の面積は、必要最少限に
抑えられるため、半導体膜中にとりこまれる不純物（I
n,Sn等）の量を少なくすることができる。INDUSTRIAL APPLICABILITY As described above, the present invention provides a transparent conductive film which is exposed to plasma at the time of forming a semiconductor film by providing a transparent conductive film and forming a contact hole at a position where electrical contact is required, and then forming a semiconductor film. Since the area of the
n, Sn, etc.) can be reduced.
従って前述した不純物混入による電気的特性の劣化、エ
ッチングプロセス制御性の低下等の問題を抑制すること
が可能となる。Therefore, it becomes possible to suppress the above-mentioned problems such as deterioration of electrical characteristics due to mixing of impurities and deterioration of controllability of etching process.
第１図は発明の一実施例による順スタガー型TFTの断面
図、第２図は第１図における絶縁層コンタクトホールの
平面図、第３図は従来の順スタガー型TFTの断面図。 １……透明導電膜、２……絶縁層、３……コンタクトホ
ール、４……ｎ＋−ａ−Ｓｉ層、５……ｉ−ａ−Ｓ
ｉ層、６……ゲート絶縁膜、７……ゲート電極、８……
ゲート配線部、９……ドレイン配線部、10……ソース配
線部。FIG. 1 is a sectional view of a forward stagger TFT according to an embodiment of the invention, FIG. 2 is a plan view of an insulating layer contact hole in FIG. 1, and FIG. 3 is a sectional view of a conventional forward stagger TFT. 1 ... Transparent conductive film, 2 ... Insulating layer, 3 ... Contact hole, 4 ... N + -a- Si layer, 5 ... I-a-S
i layer, 6 ... Gate insulating film, 7 ... Gate electrode, 8 ...
Gate wiring part, 9 ... Drain wiring part, 10 ... Source wiring part.
Claims (1)
線を形成する透明導電膜と、少なくとも前記透明導電膜
を覆うようにガラス基板上の全面に被着した絶縁膜
と、、該絶縁膜上の真性アモルファスシリコン層を活性
層とし、該活性層上にゲート酸化膜とゲート電極とを有
する薄膜半導体素子とを有し、前記ドレイン配線と前記
活性層に形成されたドレイン領域及び前記ソース配線と
前記活性層に形成されたソース領域とは、前記絶縁膜の
前記ドレイン配線及び前記ソース配線上に設けた開口部
で不純物を含んだアモルファスシリコン層を介して各々
接続され、前記ゲート電極が前記ドレイン配線及び前記
ソース配線を横切るように延在されていることを特徴と
する薄膜半導体素子。1. A transparent conductive film forming a drain wiring and a source wiring on a glass substrate, an insulating film deposited on the entire surface of the glass substrate so as to cover at least the transparent conductive film, and an insulating film on the insulating film. An intrinsic amorphous silicon layer is used as an active layer, and a thin film semiconductor element having a gate oxide film and a gate electrode is formed on the active layer, and the drain wiring, the drain region and the source wiring formed in the active layer, and the The source region formed in the active layer is connected to the drain wiring of the insulating film and an opening provided on the source wiring through an amorphous silicon layer containing impurities, and the gate electrode is connected to the drain wiring. And a thin film semiconductor element, which extends so as to cross the source wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61013105A JPH0669098B2 (en) | 1986-01-23 | 1986-01-23 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61013105A JPH0669098B2 (en) | 1986-01-23 | 1986-01-23 | Thin film semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62171161A JPS62171161A (en) | 1987-07-28 |
| JPH0669098B2 true JPH0669098B2 (en) | 1994-08-31 |
Family
ID=11823867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61013105A Expired - Fee Related JPH0669098B2 (en) | 1986-01-23 | 1986-01-23 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669098B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100351874B1 (en) | 1999-09-14 | 2002-09-12 | 엘지.필립스 엘시디 주식회사 | Thin film transistor liquid crystal display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893282A (en) * | 1981-11-30 | 1983-06-02 | Seiko Epson Corp | thin film semiconductor device |
| JPS5954269A (en) * | 1982-09-22 | 1984-03-29 | Seiko Epson Corp | Thin film semiconductor device |
| JPS60158670A (en) * | 1984-01-28 | 1985-08-20 | Seiko Instr & Electronics Ltd | Thin film transistor and its manufacturing method |
-
1986
- 1986-01-23 JP JP61013105A patent/JPH0669098B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62171161A (en) | 1987-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW482938B (en) | Display device and manufacturing method thereof | |
| EP0338822A2 (en) | A liquid crystal active-matrix display device | |
| US5981972A (en) | Actived matrix substrate having a transistor with multi-layered ohmic contact | |
| JPH061314B2 (en) | Thin film transistor array | |
| KR100322968B1 (en) | Method for manufacturing fringe field switching mode lcd | |
| JPH1041521A (en) | Method of manufacturing thin film transistor and structure of thin film transistor manufactured by the method | |
| JPH06295924A (en) | Manufacture of liquid crystal display device | |
| JPH0680685B2 (en) | Thin film transistor and manufacturing method thereof | |
| JPH1126768A (en) | Thin film transistor for liquid crystal display | |
| JPH1195256A (en) | Active matrix substrate | |
| JP2678044B2 (en) | Active matrix substrate manufacturing method | |
| KR100316072B1 (en) | Liquid crystal display and method of manufacturing the same | |
| JPH06204247A (en) | Manufacture of thin film transistor | |
| JPH0570156B2 (en) | ||
| JPH0543095B2 (en) | ||
| JPH0669098B2 (en) | Thin film semiconductor device | |
| JP4034376B2 (en) | Manufacturing method of active matrix type liquid crystal display device | |
| JP3603968B2 (en) | Thin film transistor and method for manufacturing the same | |
| JP2656555B2 (en) | Thin film transistor, active matrix circuit substrate using the same, and image display device | |
| JP2656554B2 (en) | Thin film transistor, active matrix circuit substrate using the same, and image display device | |
| JP3419073B2 (en) | Thin film transistor, method of manufacturing the same, and active matrix liquid crystal display device | |
| JP2506067B2 (en) | Transmissive liquid crystal display device | |
| JPH0822029A (en) | Liquid crystal display device and manufacturing method thereof | |
| KR0156180B1 (en) | Manufacturing method of liquid crystal display device | |
| JPH01282522A (en) | Active matrix circuit board, manufacturing method thereof, and image display device using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |