JPH0669349A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0669349A JPH0669349A JP21985392A JP21985392A JPH0669349A JP H0669349 A JPH0669349 A JP H0669349A JP 21985392 A JP21985392 A JP 21985392A JP 21985392 A JP21985392 A JP 21985392A JP H0669349 A JPH0669349 A JP H0669349A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- interlayer insulating
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title description 3
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 abstract description 28
- 238000005530 etching Methods 0.000 abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 6
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体集積回路の多層配線の形成工程におけ
る層間絶縁膜に形成したスルーホールの埋め込みに関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to filling a through hole formed in an interlayer insulating film in a process of forming a multi-layer wiring of a semiconductor integrated circuit.
【０００２】[0002]
【従来の技術】半導体集積回路の高集積化・高密度化に
より、内部回路を相互接続するため多層配線が用いられ
ているものが多い。2. Description of the Related Art Due to higher integration and higher density of semiconductor integrated circuits, multilayer wiring is often used for interconnecting internal circuits.
【０００３】従来の多層配線の形成方法について、図３
（ａ）〜（ｄ）を参照して説明する。FIG. 3 shows a conventional method for forming a multi-layer wiring.
This will be described with reference to (a) to (d).
【０００４】はじめに図３（ａ）に示すように、半導体
基板１上に層間絶縁膜２を形成したのち、厚さ０．５〜
１．０μｍの金属膜を堆積してからレジスト（図示せ
ず）をマスクとしてエッチングすることにより金属膜か
らなる下層配線１２を形成する。つぎに全面に厚さ０．
５〜１．０μｍの層間絶縁膜１３を堆積したのち、ＳＯ
Ｇ、ポリイミドおよびレジストのうち１つからなる塗布
膜１４を形成する。First, as shown in FIG. 3A, after forming an interlayer insulating film 2 on a semiconductor substrate 1, a thickness of 0.5 to
After depositing a metal film of 1.0 μm, etching is performed using a resist (not shown) as a mask to form the lower wiring 12 made of the metal film. Next, the thickness is 0.
After depositing the interlayer insulating film 13 of 5 to 1.0 μm,
A coating film 14 made of one of G, polyimide and resist is formed.
【０００５】つぎに図３（ｂ）に示すように、塗布膜１
４と層間絶縁膜１３とのエッチングレートがほぼ等しく
なる条件でエッチバックして層間絶縁膜１３を平坦化す
る。Next, as shown in FIG. 3B, the coating film 1
4 and the interlayer insulating film 13 are etched back under the condition that the etching rates of the interlayer insulating film 13 and the interlayer insulating film 13 are substantially equal to each other to flatten the interlayer insulating film 13.
【０００６】つぎに図３（ｃ）に示すように、厚さ０．
５〜１．０μｍの層間絶縁膜１５を堆積したのち、レジ
スト（図示せず）をマスクとしてエッチングして金属膜
１２に達するスルーホール１６を開口する。つぎに選択
ＣＶＤによりスルーホール１６にＷ（タングステン）な
どからなる金属膜１７を埋め込む。Next, as shown in FIG.
After depositing an interlayer insulating film 15 of 5 to 1.0 μm, a through hole 16 reaching the metal film 12 is opened by etching using a resist (not shown) as a mask. Next, a metal film 17 made of W (tungsten) or the like is embedded in the through hole 16 by selective CVD.
【０００７】つぎに図３（ｄ）に示すように上層配線１
８を形成する。Next, as shown in FIG. 3D, the upper layer wiring 1
8 is formed.
【０００８】[0008]
【発明が解決しようとする課題】従来の多層配線の形成
方法では、平坦化された層間絶縁膜上に上層配線を形成
したのち、塗布膜を用いて平坦化するので、つぎのよう
な問題が生じている。In the conventional method for forming a multi-layered wiring, since the upper layer wiring is formed on the flattened interlayer insulating film and then flattened by using the coating film, the following problems occur. Has occurred.
【０００９】図４（ａ）に示すように、孤立した下層配
線１２上の塗布膜１４は、大面積の下層配線上の塗布膜
よりも薄くなる。これは塗布膜を形成するとき表面張力
によって生じる現象である。As shown in FIG. 4A, the coating film 14 on the isolated lower layer wiring 12 becomes thinner than the coating film on the large area lower layer wiring. This is a phenomenon caused by surface tension when forming a coating film.
【００１０】そのあと図４（ｂ）に示すように、エッチ
バックを行なうと孤立した下層配線１２上の層間絶縁膜
１３は、大面積の下層配線上の層間絶縁膜よりも薄くな
る。Then, as shown in FIG. 4B, when the etch back is performed, the interlayer insulating film 13 on the isolated lower layer wiring 12 becomes thinner than the interlayer insulating film on the large area lower layer wiring.
【００１１】具体例を挙げると幅１〜２μｍの下層配線
と、幅１００μｍの下層配線とが並んでいるところに、
厚さ１．０μｍの層間絶縁膜を堆積したのち、塗布膜を
形成してからエッチバックを行なう。このとき幅１〜２
μｍの下層配線上の層間絶縁膜の残膜の厚さを２００〜
３００ｎｍとすると、幅１００μｍの下層配線上の残膜
の厚さは６００〜７００ｎｍとなる。As a specific example, a lower layer wiring having a width of 1 to 2 μm and a lower layer wiring having a width of 100 μm are lined up,
After depositing an interlayer insulating film having a thickness of 1.0 μm, a coating film is formed and then etch back is performed. Width 1-2 at this time
The thickness of the residual film of the interlayer insulating film on the lower wiring of
When the thickness is 300 nm, the thickness of the residual film on the lower layer wiring having a width of 100 μm is 600 to 700 nm.
【００１２】そのため図５に示すように、左側の配線の
ない領域と大面積の下層配線１２および上層配線１８が
重なった領域とでは配線の膜厚が加わり、その上の層間
絶縁膜１９表面に大きな高低差ｄを生じる。Therefore, as shown in FIG. 5, the thickness of the wiring is added to the area without wiring on the left side and the area where the large-area lower layer wiring 12 and the upper layer wiring 18 overlap, and the surface of the interlayer insulating film 19 on the wiring is added. A large height difference d occurs.
【００１３】焦点深度を越えた高低差ｄのあるところで
は、微細なレジストパターンを形成することができな
い。そのため配線ピッチ（間隔）を縮小することができ
ないので、半導体集積回路の高集積化を進めるうえでの
障害となっている。A fine resist pattern cannot be formed at a height difference d exceeding the depth of focus. Therefore, the wiring pitch (spacing) cannot be reduced, which is an obstacle to the high integration of semiconductor integrated circuits.
【００１４】[0014]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板の一主面上に層間絶縁膜を堆積し
たのち、前記層間絶縁膜に溝を形成する工程と、前記溝
の底面に第１の金属膜を形成する工程と、前記第１の金
属上に第２の金属膜を選択的に成長させて前記溝を埋め
込む工程とを含むものである。According to a method of manufacturing a semiconductor device of the present invention, a step of depositing an interlayer insulating film on one main surface of a semiconductor substrate and then forming a groove in the interlayer insulating film; The method includes a step of forming a first metal film on the bottom surface and a step of selectively growing a second metal film on the first metal to fill the groove.
【００１５】[0015]
【実施例】本発明の第１の実施例について、図１（ａ）
〜（ｄ）を参照して説明する。EXAMPLE FIG. 1A shows a first example of the present invention.
Description will be made with reference to (d).
【００１６】はじめに図１（ａ）に示すように、半導体
基板１上に厚さ１〜２μｍの酸化シリコンまたは窒化シ
リコンからなる層間絶縁膜２を形成したのち、レジスト
３をマスクとしてエッチングして深さ０．５〜１．０μ
ｍの溝４を形成してから全面に厚さ５０〜１００ｎｍの
Ｗ（タングステン）またはＴｉＮ（窒化チタン）などの
高融点金属からなる金属膜５を堆積する。First, as shown in FIG. 1A, an interlayer insulating film 2 made of silicon oxide or silicon nitride having a thickness of 1 to 2 μm is formed on a semiconductor substrate 1, and then a resist 3 is used as a mask for etching to form a deep layer. 0.5-1.0μ
After forming the groove 4 of m, a metal film 5 made of a refractory metal such as W (tungsten) or TiN (titanium nitride) having a thickness of 50 to 100 nm is deposited on the entire surface.
【００１７】このとき金属膜５が溝４のレジスト３と層
間絶縁膜２との間で段切れしていなければならない。そ
のため層間絶縁膜２に溝４を形成するとき、サイドエッ
チングが生じる条件でエッチングを行ない、レジスト３
の開口よりも層間絶縁膜２の溝４の幅を若干（５０〜１
００ｎｍ）拡げる。そのあとスパッタ法により金属膜５
を堆積すれば、層間絶縁膜２の溝４側面には金属膜５は
堆積しない。At this time, the metal film 5 must be discontinuous between the resist 3 in the groove 4 and the interlayer insulating film 2. Therefore, when the groove 4 is formed in the interlayer insulating film 2, etching is performed under the condition that side etching occurs, and the resist 3
The width of the groove 4 of the interlayer insulating film 2 is slightly smaller (50 to 1
00 nm) After that, the metal film 5 is formed by the sputtering method.
Is deposited, the metal film 5 is not deposited on the side surface of the groove 4 of the interlayer insulating film 2.
【００１８】つぎに図１（ｂ）に示すように、レジスト
３と共に不要の金属膜５を除去して溝４の底面のみに金
属膜５を残す。Next, as shown in FIG. 1B, the unnecessary metal film 5 is removed together with the resist 3 to leave the metal film 5 only on the bottom surface of the groove 4.
【００１９】つぎに図１（ｃ）に示すように、選択ＣＶ
Ｄ（気相成長）法により溝４にＡｌ（アルミニウム）系
金属を埋め込んで下層配線６を形成したのち、酸化シリ
コンまたは窒化シリコンからなる層間絶縁膜７を堆積す
る。つぎに層間絶縁膜７をエッチングして下層配線６に
達するスルーホール８を開口したのち、選択ＣＶＤ法に
よりタングステンなどの高融点金属からなる金属膜９を
埋め込む。Next, as shown in FIG. 1C, the selected CV
After the Al (aluminum) -based metal is buried in the groove 4 by the D (vapor phase growth) method to form the lower layer wiring 6, the interlayer insulating film 7 made of silicon oxide or silicon nitride is deposited. Next, the interlayer insulating film 7 is etched to open a through hole 8 reaching the lower layer wiring 6, and then a metal film 9 made of a refractory metal such as tungsten is buried by a selective CVD method.
【００２０】つぎに図１（ｄ）に示すように、再びレジ
スト（図示せず）をマスクとして層間絶縁膜７をエッチ
ングして溝を形成したのち、溝の底面にタングステンま
たは窒化チタンなどの高融点金属からなる金属膜１０を
形成してから、Ａｌ系金属からなる上層配線１１を形成
する。Next, as shown in FIG. 1D, the interlayer insulating film 7 is etched again using a resist (not shown) as a mask to form a groove, and then a tungsten or titanium nitride or the like is formed on the bottom surface of the groove. After forming the metal film 10 made of a melting point metal, the upper wiring 11 made of an Al-based metal is formed.
【００２１】つぎに本発明の第２の実施例について、図
２（ａ）〜（ｄ）を参照して説明する。Next, a second embodiment of the present invention will be described with reference to FIGS.
【００２２】はじめに図２（ａ）に示すように、半導体
基板１上に層間絶縁膜２を形成したのち、レジスト（図
示せず）をマスクとして層間絶縁膜２をエッチングして
溝４を形成してからレジストを除去する。つぎに全面に
厚さ３０〜５０ｎｍのタングステンまたは窒化チタンな
どの高融点金属からなる金属膜５を堆積したのち、ＳＯ
Ｇ、ポリイミドおよびレジストのうち１つからなる塗布
膜１４を形成する。First, as shown in FIG. 2A, after forming the interlayer insulating film 2 on the semiconductor substrate 1, the interlayer insulating film 2 is etched using a resist (not shown) as a mask to form a groove 4. And then remove the resist. Next, after depositing a metal film 5 made of a refractory metal such as tungsten or titanium nitride having a thickness of 30 to 50 nm on the entire surface, SO
A coating film 14 made of one of G, polyimide and resist is formed.
【００２３】つぎに図２（ｂ）に示すように、塗布膜１
４と金属膜５とのエッチングレートがほぼ等しくなる条
件でエッチバックして溝４を除く層間絶縁膜２上の金属
膜５を完全に除去する。Next, as shown in FIG. 2B, the coating film 1
4 and the metal film 5 are etched back under substantially the same etching rate to completely remove the metal film 5 on the interlayer insulating film 2 except the groove 4.
【００２４】つぎに図４（ｃ）に示すように、ウェット
エッチングにより溝４に残った塗布膜１４を除去して金
属膜５表面を露出させる。Next, as shown in FIG. 4C, the coating film 14 remaining in the groove 4 is removed by wet etching to expose the surface of the metal film 5.
【００２５】つぎに図２（ｄ）に示すように、選択ＣＶ
Ｄ法によりＡｌ系金属を埋め込んで下層配線６を形成す
る。このあと第１の実施例と同様にして上層配線（図示
せず）を形成することができる。Next, as shown in FIG. 2D, the selected CV
The lower layer wiring 6 is formed by embedding an Al-based metal by the D method. Thereafter, an upper layer wiring (not shown) can be formed in the same manner as in the first embodiment.
【００２６】[0026]
【発明の効果】層間絶縁膜に形成した溝に選択的に配線
を形成するので、配線による段差がなくなり完全に平坦
な層間絶縁膜を実現することができた。Since the wiring is selectively formed in the groove formed in the interlayer insulating film, it is possible to realize a completely flat interlayer insulating film without any step due to the wiring.
【００２７】その結果、段差による加工寸法の差がなく
なり、スルーホール深さの下地パターン依存性もなくな
った。総てのスルーホール深さを揃えることができ、容
易に微細寸法の多層配線を形成することができる。As a result, the difference in processing dimension due to the step difference disappeared, and the dependency of the through hole depth on the underlying pattern disappeared. It is possible to make all the depths of the through holes uniform, and it is possible to easily form a multilayer wiring having a fine dimension.
【図１】本発明の第１の実施例を工程順に示す断面図で
ある。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.
【図２】本発明の第２の実施例を工程順に示す断面図で
ある。FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.
【図３】従来の多層配線の形成方法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional method for forming multilayer wiring.
【図４】従来の多層配線の形成方法の問題点を示す断面
図である。FIG. 4 is a cross-sectional view showing a problem of a conventional method of forming a multilayer wiring.
【図５】従来の多層配線の問題点を示す断面図である。FIG. 5 is a cross-sectional view showing a problem of conventional multilayer wiring.
１ 半導体基板 ２ 層間絶縁膜 ３ レジスト ４ 溝 ５ 金属膜 ６ 下層配線 ７ 層間絶縁膜 ８ スルーホール ９ 金属膜 １０ 金属膜 １１ 上層配線 １２ 下層配線 １３ 層間絶縁膜 １４ 塗布膜 １５ 層間絶縁膜 １６ スルーホール １７ 金属膜 １８ 上層配線 ｄ 層間絶縁膜の高低差 1 semiconductor substrate 2 interlayer insulating film 3 resist 4 groove 5 metal film 6 lower layer wiring 7 interlayer insulating film 8 through hole 9 metal film 10 metal film 11 upper layer wiring 12 lower layer wiring 13 interlayer insulating film 14 coating film 15 interlayer insulating film 16 through hole 17 metal film 18 upper layer wiring d height difference of interlayer insulating film
Claims (1)
積したのち、前記層間絶縁膜に溝を形成する工程と、前
記溝の底面に第１の金属膜を形成する工程と、前記第１
の金属上に第２の金属膜を選択的に成長させて前記溝を
埋め込む工程とを含む半導体装置の製造方法。1. A step of depositing an interlayer insulating film on a main surface of a semiconductor substrate and then forming a groove in the interlayer insulating film; a step of forming a first metal film on a bottom surface of the groove; First
And a step of selectively growing a second metal film on the metal of claim 1 to fill the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21985392A JPH0669349A (en) | 1992-08-19 | 1992-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21985392A JPH0669349A (en) | 1992-08-19 | 1992-08-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0669349A true JPH0669349A (en) | 1994-03-11 |
Family
ID=16742091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21985392A Pending JPH0669349A (en) | 1992-08-19 | 1992-08-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669349A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09306994A (en) * | 1996-05-16 | 1997-11-28 | Lg Semicon Co Ltd | Method for forming wiring of semiconductor device |
-
1992
- 1992-08-19 JP JP21985392A patent/JPH0669349A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09306994A (en) * | 1996-05-16 | 1997-11-28 | Lg Semicon Co Ltd | Method for forming wiring of semiconductor device |
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