JPH0669783A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To constitute a logical stage with a single stage without regard to a fine number and to quicken operation by making wired logical constitution by connecting the emitters of plural power source voltage side output transistors of Bi-CMOS constitution. CONSTITUTION:P-channel type MOSFET Q1 and Q2 are parallelly connected and the respective gates of them are provided with input signals IN1 and IN2. On the other hand P-channel type MOSFET Q3 and Q4 are serially connected and the respective gates of them are provided with the input signals IN1 and IN2. The output of the AND gate circuit G1 is provided for the base of an output transistor T1 on the side of power source voltage. The NAND gate circuit G2 of CMOS constitution composed of MOSFET Q5 to Q8 is similarly provided in accordance with remaining two input signals IN3 and IN4 so as to drive an output transistor T2 on the side of power source voltage by its output signal. Then, the emitters of the transistors T1 and T2 are connected in common and set to be wired OR logical constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a bipolar CMOS (hereinafter abbreviated as Bi-CMOS) including a complementary push-pull output circuit and a CMOS logic circuit for driving it.
The present invention relates to a technique that is particularly effective when used for those including circuits.

[0002]

2. Description of the Related Art A complementary push-pull output circuit composed of an NPN transistor and a PNP transistor is used as a C
There is a Bi-CMOS circuit that is driven by a MOS logic circuit. Regarding such a Bi-CMOS circuit, for example, there are pages 27 and 65 to 68 of "Design of CMOS VLSI" published by Baifukan, edited by Tetsuya Iizuka.

[0003]

In the Bi-CMOS circuit, when the high load wiring is driven by the AND-OR logic, generally, as shown in FIG. 4, NAND gate circuits G1 and G2 by the CMOS circuit are used. Is provided in the preceding stage, and its output drives the 2-input NAND circuit. In this configuration, there is a problem that the number of logic stages increases and the operation speed becomes slow.

An object of the present invention is to provide a semiconductor integrated circuit device equipped with a Bi-CMOS circuit which has a high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the emitters of a plurality of output transistors on the power supply voltage side having a Bi-CMOS configuration are commonly connected to form a wired logic configuration, or the output transistors on the ground potential side of a plurality of Bi-CMOS configurations are commonly connected to form a collector dot configuration. Then, the other transistor is complementarily switch-controlled by the corresponding logic block.

[0006]

According to the above means, the C
Since the MOS logic stage can be configured by one stage, the operation speed can be increased accordingly.

[0007]

1 is a circuit diagram of an embodiment of a Bi-CMOS circuit according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known Bi-CMOS technique together with other circuit elements that realize a certain circuit function. In the circuit diagram, a MOSFET having an arrow on its channel (back gate) portion is a P-channel type and is distinguished from an N-channel MOSFET without an arrow.

In this embodiment, a total of four inputs of AND-
It is intended for Bi-CMOS circuits with OR logic function. The P-channel MOSFETs Q1 and Q2 are connected in parallel, and their gates have an input signal IN1.
And IN2 are supplied. In addition, N-channel type MOSF
ETQ3 and Q4 are formed in series, and the input signals IN1 and IN2 are supplied to their respective gates. That is, the input signal IN1 is applied to the gates of one of the P-channel type MOSFET Q1 and the N-channel type MOSFET Q3.
Are commonly supplied, and the other P-channel MOSFET
The gates of Q2 and N-channel MOSFET Q4 are
The input signal IN2 is commonly supplied. The output signal of the AND gate circuit G1 is supplied to the base of the output transistor T1 on the power supply voltage side.

A CMO comprising MOSFETs Q5 to Q8 similar to the above corresponding to the remaining two input signals IN3 and IN4.
A NAND gate circuit G2 having an S configuration is provided, and an output signal from the NAND gate circuit G2 drives the output transistor T2 on the power supply voltage side. Then, the emitters of these transistors T1 and T2 are commonly connected, in other words, have a wired OR logic configuration and are connected to the output terminal OUT.

An output transistor T3 on the ground potential side is provided commonly to the output transistors T1 and T2. Between the base of the transistor T3 and the collector connected to the output terminal OUT, a logic block including N-channel type MOSFETs Q9 to Q12 arranged in series and parallel is provided. That is, the input signal I corresponding to the P-channel type MOSFETs Q1 and Q2 in the above serial form
N1 and IN2 are MOSFETQs connected in parallel
Input signals IN3 and IN4, which are supplied to the gates of 9 and Q10 and correspond to the P-channel MOSFETs Q5 and Q6 arranged in series, are connected in parallel to each other.
It is supplied to the gates of ETQ11 and Q12. The pair of parallel MOSFETs are connected in series. An N-channel MOSFET Q13 is provided between the base of the output transistor T3 and the emitter connected to the ground potential of the circuit, and its gate is connected to the output terminal OUT.

When either one of the input signals IN1 or IN2 is at a high level, an N-channel type MOSFE
TQ3 or Q4 is turned on, turning off the transistor T1. At this time, the input signal IN3 or IN4
When any one of them is at the high level, the N-channel MOSFET Q7 or Q8 is turned on and the transistor T2 is turned off. Thus, when either one of the two sets of input signals is at a high level, both transistors T1 and T2 are turned off,
The combination of the input signals IN1 to IN4 makes it possible to
A current path is formed in the logic block of the FETs Q9 to Q12, and the high level of the output terminal OUT turns on the transistor T3 to bring the output terminal OUT to the low level.

When the input signals IN1 and IN2 both go low, the transistor T1 turns on and the parallel M
Both the OSFETs Q9 and Q10 are turned off, the base current path of the transistor T3 is cut off, the MOSFET Q13 is turned on according to the high level of the output signal OUT, and the base potential of the transistor T3 is pulled to the ground potential to turn it off. To do.

Alternatively, even when the input signals IN3 and IN4 both go low, the transistor T2 is turned on, the parallel MOSFETs Q11 and Q12 are turned off, and the base current path of the transistor T3 is cut off. The MOSFET Q13 is turned on in response to the high level of the output signal OUT, and the base potential of the transistor T3 is extracted to the ground potential to turn it off. In the logical operation as described above, the CMOS circuit side can be configured by one stage, so that the operation speed can be increased.

FIG. 3 shows a Bi-CMOS according to the present invention.
A circuit diagram of another embodiment of the circuit is shown. In this embodiment, an N-channel type M which constitutes an AND gate circuit which drives the output transistors T1 and T2 on the high level side.
The sources of the OSFETs Q3, Q4 and Q7, Q8 are shown in FIG.
Instead of being connected to the ground potential of the circuit as described above, they are connected to the emitters of the corresponding output transistors T1 and T2. In this configuration, when the N-channel MOSFET is turned on, the bases and emitters of the transistors T1 and T2 are short-circuited to be turned off. The other configuration is similar to that of FIG. 1, and thus its description is omitted.

FIG. 2 shows a Bi-CMOS according to the present invention.
A circuit diagram of another embodiment of the circuit is shown. In this embodiment, a collector dot configuration is used instead of wired OR logic.

N-channel MOSFETs Q3 and Q4 which receive the input signals IN1 and IN2 are connected in series and are provided between the collector and the base of the output transistor T2 on the ground potential side of the circuit. This transistor T2
A MOSFET Q5 is provided between the base and the emitter, and its gate is connected to the collector. Similarly, an N channel type MOSFE for receiving the input signals IN3 and IN4.
TQ9 and Q8 are connected in series and are provided between the collector and the base of the output transistor T3 on the ground potential side of the circuit. A MOSFET Q10 is provided between the base and the emitter of the transistor T3, and its gate is connected to the collector. The two sets of ground potential side output transistors T2 and T3 as described above are connected to the output terminal OUT in a collector dot configuration in which the collectors are commonly connected.

Corresponding to the ground potential side output transistors T2 and T3 having the collector dot configuration as described above,
The output transistor T1 on the power supply voltage side is commonly provided. Input signals IN1 and IN2 supplied to the gates of the series MOSFETs Q3 and Q4 are supplied to the gates of P-channel MOSFETs Q1 and Q2 in parallel form. Similarly, the input signals IN3 and IN4 supplied to the gates of the series MOSFETs Q8 and Q9 are supplied to the gates of P-channel MOSFETs Q6 and Q7 in parallel form. These pair of parallel MOSFETs Q1 and Q2 and Q6 and Q7
Are provided in series between the base of the transistor T1 and the collector supplied with the power supply voltage VCC.

When both the input signals IN1 and IN2 are high level, the MOSFETs Q3 and Q4 are turned on and the transistor T2 is turned on, so that a low level output signal is formed from the output terminal OUT. At this time, since the parallel MOSFETs Q1 and Q2 are in the off state, the base current supply path of the transistor T1 is cut off, so that the transistor T1 is in the off state. Alternatively, when the input signals IN3 and IN4 are both at the high level, the transistor T3 is turned on and the low-level output signal is similarly output.

When any one of the input signals IN1 and IN2 is at the low level and at least one of the input signals IN3 and IN4 is at the low level, the base current path of the transistors T1 and T2 is cut off, and this Instead, the base current path of the transistor T1 is formed, so that the transistor T1 is turned on and a high-level output signal is formed. In the above logic operation,
Since the CMOS circuit side can be configured by one stage, the operation speed can be increased.

In the Bi-CMOS circuit as described above, it suffices to provide an input transistor which is wired-OR connected corresponding to the increase in the number of inputs or increase the number of transistors having a collector dot configuration. Therefore, it is suitable for a decoder circuit that decodes an address signal composed of a large number of bits and forms a selection signal like various memory circuits.

Further, by utilizing the fact that the speedup is achieved as described above, and by utilizing it in the redundancy decoder circuit of the decoder circuits, the memory access time can be shortened. That is, in the redundant circuit, since the selection signal of the redundant circuit is formed again after the access to the defective address is detected, the number of signal transmission logic stages is increased and the selection signal of the redundant circuit is delayed. Therefore, the delay of the selection signal can be improved by using the high speed decoder circuit as described above.

The operational effects obtained from the above embodiment are as follows. That is, (1) the emitters of a plurality of output transistors on the power supply voltage side having a Bi-CMOS configuration are commonly connected to form a wired logic configuration, or the output transistors on the ground potential side having a plurality of Bi-CMOS configurations are commonly connected to make a collector. A CMOS logic stage can be configured by one stage regardless of the number of fan-ins by forming a dot configuration and complementarily controlling the switch of the other transistor by a corresponding logic block. Therefore, the operation speed can be increased accordingly. The effect that can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. Each CMO
The input of the S stage may be one input in addition to two inputs,
It may be three or more inputs. P depending on the number of these inputs
Channel type MOSFET and N channel type MOSFET
T is provided respectively. The output circuit may be used as an internal circuit for driving a high load line such as a word line forming a static RAM, or may be one that forms an output signal to be sent to the outside of the semiconductor integrated circuit device.

The Bi-CMOS circuit according to the present invention includes various memory circuits of the Bi-CMOS configuration as described above,
It can be used for various semiconductor integrated circuit devices such as digital circuits such as a gate array having a Bi-CMOS structure.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the emitters of the power supply voltage side output transistors of a plurality of Bi-CMOS configurations are commonly connected to form a wired logic configuration, or a plurality of Bi-CMOS configurations are used.
The output transistors on the ground potential side of the configuration are commonly connected to form a collector dot configuration, and the other transistor is complementarily switch-controlled by a corresponding logic block, so that one CMOS logic stage is provided regardless of the number of fan-ins. Since it can be configured by, the operation speed can be increased accordingly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a Bi-CMOS circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the Bi-CMOS circuit according to the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the Bi-CMOS circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional technique.

[Explanation of symbols]

Q1-Q13 ... MOSFET, T1-T3 ... Transistor, G1, G2 ... And gate circuit.

Claims (3)

[Claims] 1. An emitter follower transistor comprising a plurality of CMOS logic outputs respectively having emitters connected in common to form a high level output signal, and an input signal inputted to the plurality of CMOS logic gate circuits. And a logic block that forms a current path when all of the emitter follower transistors are off, and an output transistor that supplies a signal at an output terminal to the base through the logic block and forms a low-level output signal, A semiconductor integrated circuit device comprising a Bi-CMOS circuit provided between a base and an emitter of the output transistor and having a gate to which an output signal is supplied. 2. The semiconductor integrated circuit device according to claim 1, wherein the reference potential of the N-channel side circuit forming the CMOS logic output is connected to the emitter of the corresponding transistor. 3. A power supply voltage side output transistor, which receives a plurality of input signals and is supplied with a drive signal through a logic block of P-channel type MOSFETs connected in series and in parallel, and a P-channel type connected in parallel. Between a plurality of ground potential side output transistors whose collector voltages are supplied to the bases through N-channel MOSFETs in series which receive the input signals supplied to the gates of the MOSFETs, and the bases and emitters of the output transistors. N-channel MO whose gates are connected to the collectors of the corresponding transistors.
A semiconductor integrated circuit device comprising a Bi-CMOS circuit including an SFET.