JPH0670285A - MUSE decoder - Google Patents

Abstract

(57) [Abstract] [Purpose] The circuit of the MUSE decoder is configured so that the memory part is suitable for the attachment / detachment method, and the memory part is unitized and can be selected according to the price and performance. [Structure] The still image area processing unit 28 detects the still image area from the input of the memory 12 and the inter-frame interpolation circuit 11 that interpolates the MUSE image signal input and the signal delayed by one frame in the memory 12 between the frames. The signal is demodulated, and the 1-frame differential detection unit 30 detects a motion detection signal with a 1-frame difference from the memory 12 and the input of the inter-frame interpolation circuit 11.
And the signal input via the interframe interpolation circuit 11
From the memory 20 that delays the frame, the signal delayed by one field in the memory 20, and the input of the memory 21 that delays the signal input through the memory 20 by one field, the two-frame differential detection unit 31 detects a difference of two frames. Is detected and output, and the detection signals of the one-frame difference and the two-frame difference are mixed and the motion amount detection signal is output.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a MUSE decoder. In recent years, high-definition broadcasting using the MUSE system has started, but in order to popularize MUSE decoders for receiving high-definition broadcasting for home use, MUSE
Decoders need to be cheap and affordable. About 20 Mbit (4M
This requires a memory capacity of 5 bits dedicated image memory), which is one of the reasons for increasing the price of the MUSE decoder.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of a MUSE decoder. The moving image area processing circuit 4 and the still image are input to the MUSE image signal input which has been converted into a digital signal and subjected to input processing such as de-emphasis. The area processing circuit 6 performs pixel interpolation processing to restore the image signal of the moving image area and the image signal of the still image area and input them to the mixer 7, and the motion area detection circuit 5 detects the motion amount detection signal. Is input to the mixer 7, and the mixer 7 mixes the restored image signal of the moving image area and the restored image signal of the still image area according to the motion amount detection signal and outputs the mixed signal. The signal is decoded and output. In the conventional MUSE decoder, generally, two 4 M-bit image dedicated memories are used for inter-frame interpolation processing in the still image area processing circuit 6, and 4 M bits are used for inter-field interpolation processing.
One bit-only image memory is used, and two 4 M-bit image-only memories are used in order to detect the moving area by the continuous four-frame image signal in the moving area detection circuit 5.

[0003]

Therefore, there is a problem that the price of the MUSE decoder becomes high because many image dedicated memories are used. The present invention is based on MUSE
The MUSE decoder that has a decoder circuit with a structure suitable for a detachable system, has a memory unit as a unit, and has a small memory capacity to a large memory capacity that can be selected and used according to price and performance. The purpose is to provide.

[0004]

FIG. 1 is a block diagram of an electric circuit of a main part of a MUSE decoder showing an embodiment of the present invention. In the MUSE decoder shown in FIG.
The image signal input of E and the same image signal input are connected to the frame memory 1
The inter-frame interpolating circuit 11 that interpolates and outputs the signal delayed by one frame in 2 and the frame memory 12 that outputs the image signal interpolated by the inter-frame interpolating circuit 11 with one frame delay. And a still image to be output after reconstructing an image signal in a still image area by interposing inter-field interpolation with each other after frequency-converting by pass band limiting the input from the inter-frame interpolation circuit 11 and the input from the frame memory 12, respectively. A region processing unit 28 is provided, and the same output is input to the mixer 7 shown in FIG. 2 as an image signal of a still image region to perform signal processing.

Further, with respect to the input from the frame memory 12 and the input from the inter-frame interpolating circuit 11, after detecting a motion detection signal having a difference of one frame, the inter-field interpolating signals are output. 1-frame differential detecting section 30, a frame memory 20 for delaying and outputting the MUSE image signal input via the interframe interpolating circuit 11 by 1 frame, and input via the frame memory 20. A field memory 21 that delays and outputs a MUSE image signal by one field, an input from the inter-frame interpolation circuit 11 and an input from the frame memory 20 are inter-frame interpolated, and the frame memory 20 outputs 1
Field-delayed input and the field memory 21
2 frame differential detecting section 3 which interpolates the input from the frame and interpolates the both signals interpolated between the frames to detect a motion detection signal having a difference of 2 frames and outputs the detected signal.
1, and a mixer 25 that mixes the inputs from the 1-frame differential detection unit 30 and the 2-frame differential detection unit 31 and outputs a motion amount detection signal, and uses the same output as the motion amount detection signal. The signal is input to the mixer 7 shown in FIG. 2 for signal processing.

[0006]

According to the present invention, the frame memories 12 and 20 and the field memory 21 are arranged together in the preceding stage of the signal processing circuit of the MUSE decoder according to the above-mentioned configuration, and the memory portion is unitized to be a detachable type. It becomes possible.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, MUSE.
It is a principal part electric circuit block diagram of a decoder. Reference numeral 10 denotes an input terminal to which the MUSE image signal converted into a digital signal and input-processed is input from the input processing circuit 3 of FIG. Reference numeral 11 denotes an interframe interpolating circuit, which inputs the MUSE image signal input through the input terminal 10 to the frame memory 12 and delays the MUSE image signal input by the frame memory 12 by one frame. It is input to the interpolating circuit 11. The inter-frame interpolation circuit 11 interpolates the input MUSE image signal and the image signal delayed by one frame in the frame memory 12 into the inter-frame interpolation unit 28, and inputs the interpolated image signal to the still image area processing unit 28. The image signal interpolated by the insertion circuit 11 is delayed by one frame and input to the still image area processing unit 28.

The still image area processing unit 28 is a frequency conversion unit 1.
3 and 14 and an inter-field interpolating circuit 15. The output from the inter-frame interpolating circuit 11 is input to the frequency conversion unit 14, and the pass band is limited by the frequency conversion unit 14 so as to be folded. The frequency is converted and output, input to the inter-field interpolation circuit 15, the output from the frame memory 12 is input to the frequency conversion unit 13, and the same frequency conversion unit 13 performs pass band limitation and frequency conversion for output. Input to the inter-field interpolation circuit 15, and the inter-field interpolation circuit 15 uses the frequency conversion unit 13 and the frequency conversion unit 14.
2 is interpolated between fields, the image signal in the still image area is restored and output, and is input to the mixer 7 shown in FIG.

FIGS. 3A to 3D are pattern diagrams for explaining the pixel data processing of the present invention. FIG. 3A is a sampling pattern of a MUSE image signal input through the input terminal 10. It is a figure. In the MUSE signal, one frame image is used as an image signal of two frames, and each frame is composed of an image signal of two fields for transmission.
For example, if the white circle pixel data of the odd-numbered scanning lines is transmitted in the first field of the first frame, the white square pixel data of the even-numbered scanning lines is transmitted in the second field of the first frame. In the third field of the second frame, the pixel data of the black circles are transmitted so that they are located at the intermediate positions of the pixel data of the white circles of the first field. In the fourth field of the second frame, the pixel data of the white squares of the second field are transmitted. The pixel data of a black square is transmitted so that it is located at an intermediate position of the pixel data. In addition, A shown in FIG.
The sampling frequency of the / D converter 2 is about 16MHz
I am trying to use.

It is now assumed that the pixel data of the white circles of the odd-numbered scanning lines in the first field of the first frame is input to the interframe interpolation circuit 11 via the input terminal 10. The inter-frame interpolation circuit 11 uses a sampling frequency of about 32 MHz, reads the pixel data stored in the frame memory 12 and interpolates between frames, and as shown in FIG. The data is interpolated and output. In the frame memory 12,
As shown in (C), the image signal interpolated and input by the inter-frame interpolation circuit 11 is delayed by one frame, and, for example, the pixel data of the white square in the second field is added to the fourth field one frame before. And outputs an image signal in which the pixel data of the black squares are interpolated. The frequency conversion unit 13 and the frequency conversion unit 14 convert the sampling frequency of about 32 MHz to a sampling frequency of about 24 MHz, and the inter-field interpolation circuit 15 uses the sampling frequency of about 48 MHz. Interpolation is performed between fields of the image signal shown in FIG. 7C to interpolate the pixel data of the portion X that is not transmitted, and non-interlace of 1125 scanning lines as shown in FIG. The image signal of the still image area of the race is output.

Reference numeral 30 denotes a one-frame motion detector, which is composed of one-frame motion detectors 17 and 18 and an inter-field interpolation circuit 19 so as to detect a motion detection signal having a one-frame difference. 4 (A), (B) and (C) are pattern diagrams for explaining the pixel data processing of the present invention, and are explanatory diagrams showing the signal processing of the 1-frame motion detecting section 30. Referring to FIG. Will be described below. The interframe interpolation circuit 11 outputs the image signal shown in FIG.
In the 1-frame motion detection 18, for example, the pixel data of the preceding frame is subtracted from the value obtained by adding the image data of the current frame and dividing by 2 to obtain ' Is being detected. Similarly, the image signal shown in FIG.
In the same frame motion detection 17, in the same frame motion detection 17, for example, the pixel data of the previous frame is subtracted from the value obtained by adding the image data of the current frame and dividing by 2 The amount of pixel movement is detected. The inter-field interpolation circuit 19 uses the sampling frequency of about 32 MHz to interpolate the output from each of the 1-frame motion detections 18 and 17 and output the inter-field interpolation.
As shown in FIG. 6C, a motion detection signal having a difference of one frame is detected and input to the mixer 25 for all pixels in the non-interlaced still image area of 1125 scanning lines.

Reference numeral 31 denotes a two-frame motion detector, which includes interframe interpolating circuits 22 and 23 and interfield interpolating circuit 2.
4 to detect a motion detection signal having a difference of 2 frames. 5 (A) to 5 (G) are pattern diagrams for explaining the pixel data processing of the present invention, and are explanatory diagrams showing the signal processing of the two-frame motion detecting section 31. Referring to FIG. explain. In the inter-frame interpolation circuit 11, the image signal input from the frame memory 12 causes (A)
As shown in the figure, for example, the white circle pixel data of the first field of the current frame and 2 for the same pixel data
The motion amount of "pixel data is detected by inputting the difference from the white circle pixel data of the first field before the frame" and is input to the interframe interpolation circuit 22.

In the frame memory 20, the image signal input from the interframe interpolation circuit 11 causes
(B) As shown in FIG.
The pixel data of the white square of the field and the pixel data of the white square of the second field two frames before the same pixel data are differentiated to detect the "motion amount of the pixel data and input it to the interframe interpolation circuit 23. In addition, as shown in FIG. 7C, for example, the pixel data of the black circle in the third field one frame before the current frame and the pixel data of the black circle in the third field two frames before the same pixel data ' , And the pixel amount of motion of pixel data is detected and input to the interframe interpolation circuit 22.

In the field memory 21, as shown in FIG. 3D, for example, the pixel data of the black square in the fourth field of the current frame and 2 for the same pixel data are used according to the image signal input from the frame memory 20. The motion amount of "pixel data is detected by inputting it to the pixel data of the black square in the fourth field before the frame" and input to the interframe interpolation circuit 23. In the interframe interpolation circuit 22, about 32 MHz. Using the sampling frequency of
The image signal shown in (A) and the image signal shown in (C) are interpolated between frames and output as the image signal shown in (E) and input to the inter-field interpolating circuit 24. 23, using the sampling frequency of about 32 MHz, the image signal shown in FIG. 7B and the image signal shown in FIG. 7D are interpolated between frames and output as the image signal shown in FIG. It is input to the interpolation circuit 24.
The inter-field interpolation circuit 24 interpolates the both inputs between the fields, detects the motion detection signal of the difference of two frames of each pixel, outputs it, and inputs it to the mixer 25, as shown in FIG.

In the mixer 25, the motion detection signal detected by the one-frame difference from the one-frame motion detector 30 and the motion detection signal detected by the two-frame difference from the two-frame motion detector 31 are mixed, For example, arithmetic processing such as obtaining the maximum value for each pixel is performed and output as a motion amount detection signal and input to the frequency conversion unit 26, and the frequency conversion unit 26 converts the sampling frequency from about 32 MHz to about 48 MHz and outputs it. 2 is input to the mixer 7 shown in FIG. 2 via the frequency converter 26 and the input from the moving image region processing circuit 4 of FIG. 2 and the input from the still image region processing unit 28 are input from the frequency conversion unit 26. The MUSE image signal is decoded by mixing and outputting based on the input motion amount detection signal. Therefore, the frame memories 12 and 20 and the field memory 21 are arranged in a circuit so that they can be collectively arranged in the preceding stage of the signal processing circuit of the MUSE decoder. It becomes possible to do.

[0016]

As described above, according to the present invention,
By arranging the memory part collectively in the preceding stage of the signal processing circuit of the MUSE decoder, the memory part is unitized to be suitable for the attachment / detachment method. By providing the memory unit with a small memory capacity to a large memory capacity, We can provide a MUSE decoder that can be selected and used according to price and performance.
It greatly contributes to the spread of decoders.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential electric circuit of a MUSE decoder showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a MUSE decoder.

3A to 3D are pattern diagrams illustrating pixel data processing of the present invention.

FIGS. 4A, 4B and 4C are pattern diagrams illustrating pixel data processing of the present invention.

5A to 5G are pattern diagrams for explaining pixel data processing of the present invention.

[Explanation of symbols]

 1 Input Terminal 2 A / D Converter 3 Input Processing Circuit 4 Video Region Processing Circuit 5 Motion Region Detection Circuit 6 Still Image Region Processing Circuit 7 Mixer 8 Output Processing Circuit 9 Output Terminal 10 Input Terminal 11 Interframe Interpolation Circuit 12 Frames Memory 13 Frequency converter 14 Frequency converter 15 Inter-field interpolation circuit 16 Output terminal 17 1-frame motion detection 18 1-frame motion detection 19 Inter-field interpolation circuit 20 Frame memory 21 Field memory 22 Inter-frame interpolation circuit 23 Inter-frame interpolation Insertion circuit 24 Inter-field interpolation circuit 25 Mixer 26 Frequency converter 27 Output terminal 28 Still image area processor 29 Memory unit 30 1 frame motion detector 31 2 Frame motion detector

Claims (3)

[Claims] 1. A moving image region processing circuit and a still image region processing circuit perform pixel interpolation processing on an MUSE image signal input that has been converted into a digital signal and subjected to input processing such as de-emphasis to obtain a moving image region. The image signal and the image signal of the still image area are restored and input to the first mixer, the motion amount detection signal is detected by the motion area detection circuit, and the motion amount detection signal is input to the first mixer. In the MUSE decoder which mixes and outputs the restored image signal of the moving image area and the image signal of the still image area according to the motion amount detection signal, and decodes the MUSE signal based on the output,
A first interframe interpolation circuit that interpolates and outputs the image signal input of E and a signal obtained by delaying the same image signal input by one frame in the first frame memory, and the first interframe interpolation circuit The first frame memory for delaying and outputting the inserted image signal by one frame, the input from the first interframe interpolating circuit and the input from the first frame memory are respectively pass band limited and frequency-converted, And a still image region processing unit for interpolating between the fields to restore and outputting an image signal of the still image region, and inputting the output to the first mixer as an image signal of the still image region for signal processing. A MUSE decoder characterized by the fact that it does. 2. An input from the first frame memory,
A 1-frame differential detection unit that detects a motion detection signal having a 1-frame difference with respect to an input from the first inter-frame interpolating circuit and then interpolates and outputs the inter-field differential detection unit; MUSE input via interpolating circuit
Second frame memory for delaying and outputting the image signal of 1 frame by 1 frame, a field memory for delaying and outputting the image signal of MUSE input through the second frame memory by 1 field, and within the first frame. The input from the insertion circuit and the input from the second frame memory are interpolated between frames, the input delayed by one field in the second frame memory and the input from the field memory are interpolated between frames, and interpolated between frames. Input from the two-frame differential detector, the two-frame differential detector that detects and outputs a motion detection signal having a two-frame difference by interpolating both signals between fields. And a second mixer for mixing and outputting a motion amount detection signal, and inputting the output to the first mixer as a motion amount detection signal for signal processing. MUSE of claim 1, wherein
decoder. 3. The M according to claim 1, wherein the first frame memory, the second frame memory and the field memory are unitized and removable.
USE decoder.