JPH0671027B2 - Semiconductor element mounting method - Google Patents

Semiconductor element mounting method

Info

Publication number
JPH0671027B2
JPH0671027B2 JP63172108A JP17210888A JPH0671027B2 JP H0671027 B2 JPH0671027 B2 JP H0671027B2 JP 63172108 A JP63172108 A JP 63172108A JP 17210888 A JP17210888 A JP 17210888A JP H0671027 B2 JPH0671027 B2 JP H0671027B2
Authority
JP
Japan
Prior art keywords
semiconductor element
conductor wiring
electrode
insulating resin
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63172108A
Other languages
Japanese (ja)
Other versions
JPH0222834A (en
Inventor
博昭 藤本
賢造 畑田
岳雄 越智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63172108A priority Critical patent/JPH0671027B2/en
Publication of JPH0222834A publication Critical patent/JPH0222834A/en
Publication of JPH0671027B2 publication Critical patent/JPH0671027B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、マイクロコンピュータや、ゲートアレイ等の
多電極,狭ピッチのLSIチップなどの半導体素子の実装
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device such as a microcomputer, a multi-electrode such as a gate array, or a narrow pitch LSI chip.

従来の技術 従来の技術を第2図とともに説明する。Conventional Technology Conventional technology will be described with reference to FIG.

まず第2図aに示す様に、ガラスよりなる配線基板21の
導体配線22を有する面に、光硬化性樹脂23を塗布する。
導体配線22は、Cr-Au,Al,ITO等であり,光硬化性樹脂23
は、エポキシ,アクリル等である。次に、第2図bに示
す様に、Al,Au等よりなる突起電極25を有したLSIチップ
24を、突起電極25と導体配線22が一致する様に配線基板
21の光硬化性樹脂23を塗布された領域に設置し加圧ツー
ル26にてLSIチップ24を加圧する。この時、光硬化性樹
脂23は周囲に押し出され、LSIチップ24の突起電極25と
導体配線22は電気的に接触する。またこの時、LSIチッ
プ24は、加圧により、凹状に弾性変形する。次に、紫外
線27を配線基板21の裏面より照射し、光硬化性樹脂23を
硬化する。次に、第2図Cに示す様に加圧ツール26を解
除する。この時、LSIチップ24は、凹状に弾性変形した
状態で配線基板21に固着されている。
First, as shown in FIG. 2A, a photocurable resin 23 is applied to the surface of the wiring board 21 made of glass having the conductor wiring 22.
The conductor wiring 22 is made of Cr-Au, Al, ITO, etc.
Is epoxy, acrylic, or the like. Next, as shown in FIG. 2B, an LSI chip having a protruding electrode 25 made of Al, Au or the like.
24 so that the protruding electrode 25 and the conductor wiring 22 match.
The photocurable resin 23 of 21 is installed in the coated area, and the LSI chip 24 is pressed by the pressing tool 26. At this time, the photocurable resin 23 is pushed out to the surroundings, and the protruding electrode 25 of the LSI chip 24 and the conductor wiring 22 are electrically contacted. Further, at this time, the LSI chip 24 is elastically deformed into a concave shape by the pressure. Next, ultraviolet rays 27 are irradiated from the back surface of the wiring board 21 to cure the photocurable resin 23. Next, as shown in FIG. 2C, the pressure tool 26 is released. At this time, the LSI chip 24 is fixed to the wiring board 21 while being elastically deformed into a concave shape.

発明が解決しようとする課題 前述した従来の技術では、LSIチップが弾性変形した状
態で、配線基板に固着されている為、次に示す問題があ
る。
Problems to be Solved by the Invention In the above-described conventional technique, the LSI chip is elastically deformed and fixed to the wiring substrate, and therefore has the following problems.

(1)LSIチップが変形している為、素子の特性が変化
し、歩留りが低い。
(1) Since the LSI chip is deformed, the characteristics of the element change and the yield is low.

(2)LSIチップには、光硬化性樹脂から、常に剥離し
ようとする力が作用している為、高温高湿状態では、剥
離が発生し、信頼性が低い。
(2) Since the LSI chip is constantly subjected to the force of peeling from the photocurable resin, peeling occurs in a high temperature and high humidity state, and reliability is low.

課題を解決するための手段 本発明は、LSIチップの加圧時には、光硬化性樹脂のLSI
チップの電極周囲のみを硬化し、その後加圧を解除しLS
Iチップの弾性変形を、復帰させた状態で、未硬化部の
光硬化性樹脂を硬化するものである。
Means for Solving the Problems The present invention provides an LSI of a photo-curable resin when an LSI chip is pressed.
Only the area around the chip electrode is cured, then the pressure is released and LS
With the elastic deformation of the I-chip restored, the photo-curable resin in the uncured portion is cured.

すなわち、本発明は、導体配線を有する絶縁性基板の前
記導体配線に絶縁性樹脂を塗布する工程と、前記導体配
線と半導体素子の電極を一致させ前記半導体素子を前記
絶縁性基板の絶縁性樹脂を塗布した領域に設置し加圧
し、前記半導体素子の電極と前記導体配線を接触させる
工程と、前記半導体素子を、前記絶縁性基板に加圧した
状態で、前記絶縁性樹脂の前記半導体素子の電極の周囲
のみを硬化させ前記半導体素子の電極と前記導体配線を
電気的に接続する工程と、前記加圧を解除した後、前記
絶縁性樹脂の未硬化部分を硬化し前記半導体素子を前記
絶縁性基板に固着する工程よりなる半導体素子の実装方
法であり、また導体配線を有する絶縁性基板の前記導体
配線に絶縁性樹脂を塗布する工程と、前記導体配線と半
導体素子の電極を一致させ前記半導体素子を前記絶縁性
基板の絶縁性樹脂を塗布した領域に設置し加圧し、前記
半導体素子の電極と前記導体配線を接触させる工程と、
前記半導体素子を前記絶縁性基板に加圧した状態で、前
記絶縁性樹脂の前記半導体素子の電極の周囲のみを硬化
させ前記半導体素子の電極を前記導体配線を電気的に接
続する工程と、前記加圧を解除した後、前記半導体素子
の電極の周囲の前記絶縁性樹脂の硬化方法とは異る硬化
方法により、前記絶縁性樹脂の未硬化部分を硬化し前記
半導体素子を前記絶縁性基板に固着する工程よりなる半
導体素子の実装方法を提供するものである。
That is, according to the present invention, the step of applying an insulating resin to the conductor wiring of the insulating substrate having the conductor wiring, the conductor wiring and the electrode of the semiconductor element are aligned, Is placed in a coated area and pressed, and a step of bringing the electrodes of the semiconductor element into contact with the conductor wiring; and the semiconductor element in a state of being pressed against the insulating substrate, the semiconductor element of the insulating resin Insulating the semiconductor element by curing only the periphery of the electrode and electrically connecting the electrode of the semiconductor element and the conductor wiring, and curing the uncured portion of the insulating resin after releasing the pressure. A method of mounting a semiconductor element, the method comprising the steps of: fixing an insulating resin to the conductor wiring of an insulating substrate having a conductor wiring; Is not said semiconductor device is placed in an area where the insulating resin is applied to the insulating substrate pressed, the step of contacting an electrode with the conductor wiring of the semiconductor element,
A step of electrically connecting the conductor wiring to the electrode of the semiconductor element by curing only the periphery of the electrode of the semiconductor element of the insulating resin in a state where the semiconductor element is pressed against the insulating substrate; After releasing the pressure, by a curing method different from the curing method of the insulating resin around the electrodes of the semiconductor element, the uncured portion of the insulating resin is cured to form the semiconductor element on the insulating substrate. A method for mounting a semiconductor element, which includes a step of fixing the semiconductor element.

作用 LSIチップの変形がない状態で、LSIチップを配線基板に
固着することができるため、半導体素子の特性劣化がな
く、信頼性も高い。
Since the LSI chip can be fixed to the wiring board without deformation of the LSI chip, the characteristics of the semiconductor element are not deteriorated and the reliability is high.

実施例 本発明の一実施例を第1図とともに説明する。Embodiment An embodiment of the present invention will be described with reference to FIG.

まず第1図aに示す様に、ガラスよりなり、導体配線2
及び、紫外線遮断膜8を有した配線基板1の導体配線2
を含む領域に絶縁性樹脂3を塗布する。配線基板1の厚
みは、0.1〜2.0mm程度であり、導体配線2は、Cr-Au,A
l,ITO等でありその厚みは、0.1〜1.0μ程度である。紫
外線遮断膜8は、導体配線2が不透明であれば、導体配
線2形成時に同時に容易に形成できる。また、導体配線
2がITO等の透明な場合は、別途、蒸着,印刷等により
形成する。絶縁性樹脂3は、光硬化と常温硬化あるいは
光硬化と加熱硬化等の硬化方法によるものであり、主成
分は、エポキシ,アクリル,ウレタン等である。塗布方
法はディスペンサー,印刷等を用いる。また、絶縁性樹
脂3の塗布を、配線基板2に行ったが、後に、配線基板
1に搭載するLSIチップ4側に行ってもよい。
First, as shown in FIG. 1a, the conductor wiring 2 is made of glass.
And conductor wiring 2 of wiring board 1 having ultraviolet blocking film 8
Insulating resin 3 is applied to the region including. The thickness of the wiring board 1 is about 0.1 to 2.0 mm, and the conductor wiring 2 is made of Cr-Au, A
l, ITO, etc., and its thickness is about 0.1 to 1.0 μ. If the conductor wiring 2 is opaque, the ultraviolet blocking film 8 can be easily formed at the same time when the conductor wiring 2 is formed. When the conductor wiring 2 is transparent such as ITO, it is separately formed by vapor deposition, printing or the like. The insulating resin 3 is formed by a curing method such as photo-curing and room-temperature curing or photo-curing and heat curing, and its main component is epoxy, acrylic, urethane or the like. As a coating method, a dispenser, printing or the like is used. Further, although the insulating resin 3 is applied to the wiring board 2, it may be applied to the LSI chip 4 side mounted on the wiring board 1 later.

次に、第1図bに示す様に、Au等よりなる突起電極5を
有した、LSIチップ4を、突起電極5と導体配線2が一
致する様に配線基板1の絶縁性樹脂3が塗布された領域
に設置する。突起電極5の厚みは1〜10μm程度であ
り、その寸法は、3μ□〜50μ□程度である。
Next, as shown in FIG. 1b, the LSI chip 4 having the protruding electrode 5 made of Au or the like is coated with the insulating resin 3 of the wiring board 1 so that the protruding electrode 5 and the conductor wiring 2 are aligned with each other. Installed in the designated area. The thickness of the protruding electrode 5 is about 1 to 10 μm, and the size thereof is about 3 μ □ to 50 μ □.

次に、加圧ツール6にてLSIチップ1を加圧する。この
時、絶縁性樹脂3は周囲に押し出され、LSIチップ4の
突起電極5と導体配線2は電気的に接触する。また、こ
の時、LSIチップ4には、LSIチップ4の中心が最も低く
なる様な凹状のそりが生じる。そり量はLSIチップ4が1
0mm□の時、数μm程度である。次に、LSIチップ4を加
圧した状態で、紫外線7を照射し、絶縁性樹脂3を硬化
する。この時、LSIチップ4の中央に位置する絶縁性樹
脂3は、紫外線遮断膜8により硬化されず、突起電極5
の周囲のみの絶縁性樹脂3が硬化される。硬化時間は、
紫外線照度が500〜1000mW/cm2のとき、0.5〜1.0秒程度
である。
Next, the LSI chip 1 is pressed by the pressing tool 6. At this time, the insulating resin 3 is pushed out to the surroundings, and the protruding electrodes 5 of the LSI chip 4 and the conductor wirings 2 electrically contact each other. At this time, the LSI chip 4 has a concave warp such that the center of the LSI chip 4 is the lowest. The amount of warpage is 1 for LSI chip 4
When it is 0 mm □, it is about several μm. Next, while the LSI chip 4 is being pressed, ultraviolet rays 7 are irradiated to cure the insulating resin 3. At this time, the insulating resin 3 located in the center of the LSI chip 4 is not cured by the ultraviolet blocking film 8 and the protruding electrode 5
The insulating resin 3 only around the area is cured. The curing time is
When the UV illuminance is 500 to 1000 mW / cm 2 , it is about 0.5 to 1.0 seconds.

次に第1図cに示す様に、加圧ツール6を解除する。こ
の時、LSIチップ1の突起電極5と導体配線2は、突起
電極5の周囲のすでに硬化した絶縁性樹脂3aの硬化収縮
力により、電気的接続を保持した状態となる。また、LS
Iチップ4の中央部の絶縁性樹脂3bは未硬化である為、L
SIチップ4の加圧時に生じたLSIチップ4のそりはなく
なり、フラットな状態となる。次に、第1図dに示す様
に、未硬化部の絶縁性樹脂3bを、加熱硬化あるいは常温
硬化により硬化し、LSIチップ4を配線基板1に固着す
る。加熱硬化の場合は、80℃〜150℃で10分〜30分、常
温硬化の場合は、10分〜3時間程度で硬化する。
Next, as shown in FIG. 1c, the pressure tool 6 is released. At this time, the protruding electrodes 5 and the conductor wirings 2 of the LSI chip 1 are kept in electrical connection by the curing shrinkage force of the already cured insulating resin 3a around the protruding electrodes 5. Also, LS
Since the insulating resin 3b at the center of the I-chip 4 is uncured, L
The warpage of the LSI chip 4 generated when the SI chip 4 is pressed is eliminated, and the LSI chip 4 becomes flat. Next, as shown in FIG. 1D, the uncured insulating resin 3b is cured by heating or room temperature to fix the LSI chip 4 to the wiring board 1. In the case of heat curing, it is cured at 80 ° C to 150 ° C for 10 minutes to 30 minutes, and in the case of room temperature curing, it is cured in about 10 minutes to 3 hours.

なお、膜8として電子線遮断膜を用い、電子線を照射し
て樹脂3を硬化させてもよい。
Note that an electron beam blocking film may be used as the film 8 and the resin 3 may be cured by irradiation with an electron beam.

発明の効果 本発明では、LSIチップの加圧時、つまり、LSIチップに
そりが生じている段階では、LSIチップの突起電極の周
囲のみの絶縁性樹脂を硬化し、LSIチップの加圧を解除
し、そりをなくした状態で、全体の絶縁性樹脂を硬化す
る為、次に示す効果がある。
According to the present invention, when the LSI chip is pressed, that is, when the LSI chip is warped, the insulating resin around only the protruding electrodes of the LSI chip is cured to release the pressure on the LSI chip. However, since the entire insulating resin is cured with the warpage eliminated, the following effects are obtained.

(1)LSIチップにそりが生じていない為、素子特性の
変動がなく、歩留りが高い。
(1) Since the LSI chip does not warp, the element characteristics do not change and the yield is high.

(2)LSIチップの応力による絶縁性樹脂へのストレス
がない為、信頼性が高い。
(2) High reliability because there is no stress on the insulating resin due to the stress of the LSI chip.

(3)LSIチップ中央部の硬化前では接着力が非常に弱
くこの時点で電気検査を行うことにより、LSIチップの
交換が非常に容易となり、マルチチップ実装時の生産性
が高い。
(3) The adhesive strength is very weak before the central portion of the LSI chip is hardened, and by performing an electrical inspection at this point, it becomes very easy to replace the LSI chip and the productivity at the time of multi-chip mounting is high.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例方法の工程別断面図、第2図
は従来方法の工程別断面図である。 1……配線基板、2……導体配線、3……絶縁性樹脂、
4……LSIチップ、5……突起電極、6……加圧ツー
ル、7……紫外線、8……紫外線遮断膜。
FIG. 1 is a sectional view of each step of a method according to an embodiment of the present invention, and FIG. 2 is a sectional view of each step of a conventional method. 1 ... Wiring board, 2 ... Conductor wiring, 3 ... Insulating resin,
4 ... LSI chip, 5 ... protruding electrode, 6 ... pressing tool, 7 ... UV, 8 ... UV blocking film.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】導体配線を有する絶縁性基板の前記導体配
線に絶縁性樹脂を塗布する工程と、前記導体配線と半導
体素子の電極を一致させ前記半導体素子を前記絶縁性基
板の絶縁性樹脂を塗布した領域に設置し加圧し、前記半
導体素子の電極と前記導体配線を接触させる工程と、前
記半導体素子を、前記絶縁性基板に加圧した状態で、前
記絶縁性樹脂の前記半導体素子の電極の周囲のみを硬化
させ前記半導体素子の電極と前記導体配線を電気的に接
続する工程と、前記加圧を解除した後、前記絶縁性樹脂
の未硬化部分を硬化し前記半導体素子を前記絶縁性基板
に固着する工程よりなることを特徴とする半導体素子の
実装方法。
1. A step of applying an insulating resin to the conductor wiring of an insulating substrate having a conductor wiring, and aligning the conductor wiring with an electrode of a semiconductor element so that the semiconductor element is coated with the insulating resin of the insulating substrate. The step of placing in the applied area and applying pressure to bring the electrode of the semiconductor element into contact with the conductor wiring; and the step of applying the semiconductor element to the insulating substrate, the electrode of the semiconductor element of the insulating resin Of electrically connecting the electrodes of the semiconductor element to the conductor wiring by curing only the periphery of the semiconductor element, and after releasing the pressure, the uncured portion of the insulating resin is cured so that the semiconductor element is insulated. A method of mounting a semiconductor device, comprising the step of fixing to a substrate.
【請求項2】導体配線を有する絶縁性基板の前記導体配
線に絶縁性樹脂を塗布する工程と、前記導体配線と半導
体素子の電極を一致させ前記半導体素子を前記絶縁性基
板の絶縁性樹脂を塗布した領域に設置し加圧し、前記半
導体素子の電極と前記導体配線を接触させる工程と、前
記半導体素子を前記絶縁性基板に加圧した状態で、前記
絶縁性樹脂の前記半導体素子の電極の周囲のみを硬化さ
せ前記半導体素子の電極と前記導体配線を電気的に接続
する工程と、前記加圧を解除した後、前記半導体素子の
電極の周囲の前記絶縁性樹脂の硬化方法とは異る硬化方
法により、前記絶縁性樹脂の未硬化部分を硬化し前記半
導体素子を前記絶縁性基板に固着する工程よりなること
を特徴とする半導体素子の実装方法。
2. A step of applying an insulating resin to the conductor wiring of an insulating substrate having a conductor wiring, and a step of aligning the conductor wiring with an electrode of a semiconductor element so that the semiconductor element is coated with the insulating resin of the insulating substrate. The step of placing in the coated area and applying pressure to bring the electrode of the semiconductor element and the conductor wiring into contact with each other; and the step of applying pressure to the insulating substrate to the electrode of the semiconductor element of the insulating resin Different from the step of curing only the periphery to electrically connect the electrode of the semiconductor element and the conductor wiring, and the method of curing the insulating resin around the electrode of the semiconductor element after releasing the pressure. A method of mounting a semiconductor element, comprising the step of curing an uncured portion of the insulating resin by a curing method to fix the semiconductor element to the insulating substrate.
【請求項3】絶縁性基板として、透明絶縁基板の少くと
も一主面に、半導体素子の電極と相対する導体配線を有
し、前記半導体素子搭載領域の半導体素子の電極と相対
しない部分に、紫外線または電子線を遮断する膜を有し
ている配線基板を用いることを特徴とする特許請求の範
囲第1項又は第2項記載の半導体素子の実装方法。
3. An insulating substrate having a conductor wiring facing an electrode of a semiconductor element on at least one main surface of a transparent insulating substrate, and a portion not facing the electrode of the semiconductor element in the semiconductor element mounting region, The method of mounting a semiconductor element according to claim 1 or 2, wherein a wiring board having a film that blocks ultraviolet rays or electron beams is used.
JP63172108A 1988-07-11 1988-07-11 Semiconductor element mounting method Expired - Fee Related JPH0671027B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63172108A JPH0671027B2 (en) 1988-07-11 1988-07-11 Semiconductor element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63172108A JPH0671027B2 (en) 1988-07-11 1988-07-11 Semiconductor element mounting method

Publications (2)

Publication Number Publication Date
JPH0222834A JPH0222834A (en) 1990-01-25
JPH0671027B2 true JPH0671027B2 (en) 1994-09-07

Family

ID=15935701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63172108A Expired - Fee Related JPH0671027B2 (en) 1988-07-11 1988-07-11 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JPH0671027B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2547895B2 (en) * 1990-03-20 1996-10-23 シャープ株式会社 Semiconductor device mounting method
JPH0493146U (en) * 1990-12-25 1992-08-13
DE102005029407B4 (en) * 2005-06-24 2008-06-19 Mühlbauer Ag Method and apparatus for permanently connecting integrated circuits to a substrate

Also Published As

Publication number Publication date
JPH0222834A (en) 1990-01-25

Similar Documents

Publication Publication Date Title
JP2833326B2 (en) Electronic component mounted connector and method of manufacturing the same
JPH05144817A (en) Electronic part mounting/connecting body and manufacture thereof
JPH01160028A (en) Method of connecting electrode
JP2744476B2 (en) Semiconductor device and manufacturing method thereof
JPH0777227B2 (en) Method for manufacturing semiconductor device
JP2806348B2 (en) Semiconductor device mounting structure and method of manufacturing the same
JPH0671027B2 (en) Semiconductor element mounting method
JPH0682708B2 (en) Method for manufacturing semiconductor device
JPS62281360A (en) Manufacture of semiconductor device
JPH084101B2 (en) Method for manufacturing semiconductor device
JP2663649B2 (en) Multi-chip mounting method
JPS62252946A (en) Manufacture of semiconductor device
JPH012331A (en) Manufacturing method of semiconductor device
JP2780499B2 (en) Semiconductor device mounting method
JPH0671028B2 (en) Semiconductor element mounting method
JP3128816B2 (en) Method for manufacturing semiconductor device
JP2540963B2 (en) Method for manufacturing semiconductor device
JPS63240036A (en) Manufacture of semiconductor device
JP2712757B2 (en) Bonding tool
JP2827565B2 (en) Method for manufacturing semiconductor device
JPH0642502B2 (en) Method and device for manufacturing semiconductor device
JPH01160030A (en) Method of packaging semiconductor device
JP2523641B2 (en) Semiconductor device
JP2797669B2 (en) Method for manufacturing semiconductor device
JPH03290983A (en) Manufacture of led display element

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees