JPH0671069B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a cross-coupled PNPN memory cell having a lateral transistor.

[Conventional technology]

Recently, higher integration of ECL RAM with high-speed performance has been promoted. For this reason, introduction of a trench isolation technique and adoption of a lateral transistor load type memory cell with low power consumption have been attempted.

3 (a) and 3 (b) are a plan view and a sectional view taken along the line CC 'of an example of a conventional semiconductor memory device.

In this conventional example, n ^{+ is formed} on a p-type semiconductor substrate 1 partitioned by an element isolation region 4 formed by trench isolation.
N ⁺ -type collector 6 extending type n-type epitaxial layer 3 which is formed through the buried layer 2 of the buried layer 2 of n ⁺ -type, p ⁺ -type emitter 7 and p-type impurity region 8 ( A region that also serves as the collector of the pnp lateral transistor and the base of the npn vertical transistor) is provided, and the p ⁺ type base 9 and the n ⁺ type emitters 10a and 10b of the vertical transistor are provided in the impurity region 8 and further the insulating film is formed. Electrodes 12, 13, 14, 15a and 15b are provided in a contact window opened at 11.

This conventional example shows a circuit portion on one side of a cross-coupled PNPN memory cell.

FIG. 4 is a circuit diagram of an example of a conventional memory cell.

This circuit diagram shows a memory cell in which the collector and the base are connected to each other in a cross-coupled manner, the emitters E ₁ and E ₂ are connected to the bit line and, respectively, and the emitters E ₃ and E ₄ are connected to the current source. and T ₃ and T _4, connected in common to the emitter to the word line WT, is composed of a transistor T ₁ and T ₂ the collector and base respectively connected to the base and collector of the transistor T ₃ and T _4, transistors T ₁ And T ₂ and T ₃ and T ₄ correspond to the pnp lateral transistor and the npn vertical transistor shown in FIGS. 3 (a) and 3 (b), respectively.

[Problems to be solved by the invention]

In the conventional semiconductor memory device described above, the vertical transistor and the lateral transistor are configured as the memory transistor and the load thereof, respectively, so that it is excellent in terms of high integration and low power consumption, but the Schottky barrier diode is used as the load. There is a drawback in that the operation speed performance, especially the writing speed, is slower than that of the conventional one.

This is because it is determined by the current gain β of the lateral transistor of the load, and in particular, when β becomes large, the base current of the vertical transistor in the ON state becomes large, and the degree of saturation becomes high, which lowers the switching speed during writing. .

Therefore, in order to improve the writing speed, it is necessary to reduce the current gain of the lateral transistor.

However, it is possible to reduce the injection efficiency of the base by increasing the width of the lateral transistor base, but in this case, simply increasing the width of the lateral transistor base increases the device area and reduces the integration degree. There is a problem that it ends up.

An object of the present invention is to improve the high-speed performance of a semiconductor memory device including a cross-coupled pnpn memory cell by reducing the injection efficiency of the base of a lateral transistor and reducing the current gain without reducing the integration degree. Especially.

[Means for solving problems]

The semiconductor memory device of the present invention is based on an epitaxial layer of opposite conductivity type provided on a buried layer of opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type and divided by an element isolation region. In a semiconductor memory device including a cross-coupled PNPN memory cell having at least an emitter and a collector of a lateral transistor, the epitaxial layer between the emitter and the collector has a predetermined surface extending from the surface to at least a buried layer. An insulating region for reducing the base injection efficiency of the pattern is provided.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention.

In this embodiment, the crystal axis <111> and the resistivity 10 defined by the element isolation region 4 formed by trench isolation are used.
Omega · cm for p-type semiconductor substrate 1 on the n ⁺ -type buried layer 2 specific resistance 5 [Omega · formed through cm, the n-type epitaxial layer 3 having a thickness of 1 [mu] m, n ⁺ -type buried An n ⁺ type collector 6 reaching the layer 2, ap ⁺ type emitter 7 and a p type impurity region 8 (region which serves both as a collector of the pnp lateral transistor and a base of the npn vertical transistor) are provided respectively in the impurity region 8. an n ⁺ -type base 9, the n ⁺ -type emitter 10a and 10b provided, further, the lateral transistor of the memory cell provided with electrodes 12,13,14,15a, 15b in the contact window that opened in the insulating film 11 In the base (epitaxial layer 3 between the impurity region 8 and the emitter 7), an insulating region 5 having a width of 1 μm reaching the semiconductor substrate 1 is provided in a predetermined pattern similarly to the element isolation region 4. Here, in the element isolation region 4 and the insulating region 5, a groove reaching at least the buried layer 2 is formed in the epitaxial layer 3, and the surface of the groove is thermally oxidized at 1000 ° C. for 10 minutes to form an oxide film. In addition, the groove is filled with p ^- type polycrystalline silicon.

Therefore, in this embodiment, the cross-sectional area of the base of the lateral transistor is reduced, the base resistance is increased, and the current gain can be reduced without increasing the element area.

2A and 2B are a plan view and a sectional view taken along line BB 'of the second embodiment of the present invention.

In this embodiment, the width of the lateral transistor base is 1
By alternately providing the insulating regions 5 ′ of μm in a comb shape,
The effective gain is reduced by reducing the effective base cross section and increasing the base width. Here, it is desirable that the insulating regions 5'are provided so as to equally divide the base of the lateral transistor and be separated from each other by 3 μm or more.

〔The invention's effect〕

As described above, according to the present invention, by providing the insulating region by the trench isolation in the base of the lateral transistor, the injection efficiency of the base can be reduced and the current gain can be reduced, so that the operating speed can be increased without increasing the element area. There is an effect that the performance of can be significantly improved and the speed of the semiconductor memory device can be increased.

Of course, by adjusting the shape of the insulating region, the base resistance can be freely changed to optimize the operation speed.

[Brief description of drawings]

FIGS. 1 and 2 (a) and (b) are plan views of the first and second embodiments of the present invention, along with lines AA 'and BB'.
3A and 3B are a plan view of an example of a conventional semiconductor memory device and a sectional view taken along the line CC ', and FIG. 4 is a circuit diagram of an example of a conventional memory cell. 1 ... Semiconductor substrate, 2 ... Buried layer, 3 ... Epitaxial layer, 4 ... Element isolation region, 5, 5 '... Insulation region, 6 ...
... collector, 7 ... emitter, 8 ... impurity region, 9 ...
… Base, 10a, 10b …… Emitter, 11 …… Insulating film, 12,1
3,14,15a, 15b …… electrode, D, …… bit line, E ₁ , E ₂ , E ₃ , E
₄ …… Emitter, T ₁ , T ₂ , T ₃ , T ₄ …… Transistor, WT ……
Word line.

Claims (1)

[Claims] 1. An epitaxial layer of opposite conductivity type provided on a buried layer of opposite conductivity type formed on a surface of a semiconductor substrate of one conductivity type and divided by an element isolation region, and a lateral layer based on the epitaxial layer. Cross-coupled PN with at least transistor emitter and collector
In a semiconductor memory device including a PN memory cell, the epitaxial layer between the emitter and the collector is provided with an insulating region for reducing the base injection efficiency of a predetermined pattern from the surface to at least the buried layer. And semiconductor memory device.