JPH067552B2 - Method of forming bump metal and bump substrate used in the method - Google Patents
Method of forming bump metal and bump substrate used in the methodInfo
- Publication number
- JPH067552B2 JPH067552B2 JP59060994A JP6099484A JPH067552B2 JP H067552 B2 JPH067552 B2 JP H067552B2 JP 59060994 A JP59060994 A JP 59060994A JP 6099484 A JP6099484 A JP 6099484A JP H067552 B2 JPH067552 B2 JP H067552B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- film layer
- transparent conductive
- conductive film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は、IC,LSI等の半導体集積回路の高密度実
装構造体の製造に用いられるバンプ金属の形成方法およ
びその方法に用いるバンプ基板に関する。Description: TECHNICAL FIELD The present invention relates to a bump metal forming method used for manufacturing a high-density mounting structure of a semiconductor integrated circuit such as an IC and an LSI, and a bump substrate used for the method. .
(従来例の構成とその問題点) 従来、半導体素子の高密度実装法としてテープキヤリア
実装法がある。導実装法は第1図(A),(B)のように、半
導体チップ1の電極パッド2にバンプ金属3を形成し、
同バンプ金属3に対してテープキヤリア4のインナーリ
ード5をギヤングボンディング法で接続するものであ
る。(Constitution of conventional example and its problems) Conventionally, there is a tape carrier mounting method as a high-density mounting method of semiconductor elements. As shown in FIGS. 1 (A) and 1 (B), the conductive mounting method forms bump metal 3 on the electrode pad 2 of the semiconductor chip 1,
The inner lead 5 of the tape carrier 4 is connected to the bump metal 3 by a gearing bonding method.
一般的に、このテープキヤリア実装法の欠点はウエハー
状態の半導体チップに対して、一括してバンプ金属が直
接形成されるので、ウエハー内の半導体チップの一部に
不良が生じていても、この不良の半導体チップに対して
もバンプ金属を形成してしまうことであった。このこと
は、バンプ金属を不要に使用することであり、特に、バ
ンプ金属にAu等の貴金属を用いた場合、半導体チップ
の実装におけるトータルコストの上昇を招いていた。Generally, the disadvantage of this tape carrier mounting method is that bump metal is directly formed on the semiconductor chips in a wafer at once, so even if a part of the semiconductor chips in the wafer is defective, The problem is that bump metal is formed even on a defective semiconductor chip. This means that the bump metal is unnecessary, and in particular, when a precious metal such as Au is used as the bump metal, the total cost for mounting the semiconductor chip is increased.
この問題点に鑑みて第2図(A)〜第2図(C),第3図
(A),第3図(B)に示すような半導体素子の実装法および
その実装に用いる基板が用いられるようになった。以
下、図面を参照しながら説明する。第2図(A)〜第2図
(C)に示すように、半導体素子の実装法はバンプ基板6
上に電解メッキ法でバンプ金属3(例えば、Auメッキ
バンプ)を仮形成する第1工程と、同基板上のバンプ金
属3をテープキヤリア4のインナーリード5に圧着接合
する第2工程と、バンプ基板6より剥離させバンプ金属
3をインナーリード5に転写する第3工程と、バンプ金
属3をインナーリード5に転写したテープキヤリア4を
予め特性検査を終えた半導体チップ1の電極パッド2に
対してボンディングを行う第4工程とを有した実装法で
ある。また、第3図(A),第3図(B)に示すように、この
実装法に用いるバンプ基板6は、その主平面が平滑なバ
ンプメッキ基板7とメッキ電極となる透明導電膜層8と
絶縁保護膜層9とからなり、バンプメッキ基板7の上層
に透明導電膜層8を、透明導電膜層8の上層に絶縁保護
膜層9を有しているとともに、絶縁保護膜層9は選択的
に開孔部10を備えた構成である。In view of this problem, FIG. 2 (A) to FIG. 2 (C), FIG.
As shown in FIGS. 3A and 3B, a semiconductor element mounting method and a substrate used for the mounting have come to be used. Hereinafter, description will be given with reference to the drawings. Figure 2 (A) -Figure 2
As shown in (C), the mounting method of the semiconductor element is bump substrate 6
A first step of temporarily forming a bump metal 3 (for example, an Au-plated bump) on the upper surface by electrolytic plating, a second step of pressure-bonding the bump metal 3 on the same substrate to the inner lead 5 of the tape carrier 4, and a bump The third step of separating the bump metal 3 from the substrate 6 and transferring the bump metal 3 to the inner lead 5, and the tape carrier 4 having the bump metal 3 transferred to the inner lead 5 with respect to the electrode pad 2 of the semiconductor chip 1 that has undergone the characteristic inspection in advance. This is a mounting method having a fourth step of performing bonding. As shown in FIGS. 3 (A) and 3 (B), the bump substrate 6 used in this mounting method has a bump-plated substrate 7 having a smooth main surface and a transparent conductive film layer 8 serving as a plating electrode. And the insulating protective film layer 9, the transparent conductive film layer 8 is provided on the bump-plated substrate 7, and the insulating protective film layer 9 is provided on the transparent conductive film layer 8. This is a configuration in which an opening portion 10 is selectively provided.
以上のように構成された実装法およびそれに用いるバン
プ基板6について、以下その動作について説明する。ま
ず、実装法においては、バンプ金属3をバンプ基板6上
に電解メッキ法で仮形成し、仮形成したバンプ金属3を
テープキャリア4のインナーリード5に圧着接合して、
バンプ金属3をバンプ基板3より剥離させてインナーリ
ード5に転写する。その後、特性検査を終えた良品の半
導体チップ1の電極にボンディングを行う。このことよ
り、バンプ金属3を不良の半導体チップ1に形成するこ
とがなく、バンプ金属3の不要の使用を防止し、半導体
チップ1の実装におけるトータルコストを低下させるこ
とができる。The operation of the mounting method configured as above and the bump substrate 6 used for the mounting method will be described below. First, in the mounting method, the bump metal 3 is temporarily formed on the bump substrate 6 by electrolytic plating, and the temporarily formed bump metal 3 is pressure-bonded to the inner lead 5 of the tape carrier 4.
The bump metal 3 is peeled off from the bump substrate 3 and transferred to the inner lead 5. After that, the electrodes are bonded to the electrodes of the non-defective semiconductor chip 1 that has undergone the characteristic inspection. As a result, the bump metal 3 is not formed on the defective semiconductor chip 1, unnecessary use of the bump metal 3 can be prevented, and the total cost for mounting the semiconductor chip 1 can be reduced.
また、実装に用いるバンプ金属6においては、透明導電
膜層8が基板端部の外部接続用電極部11でメッキ用電源
に接続され電解メッキ処理を施されることにより、絶縁
保護膜層9の開孔部10において透明導電膜層8を陰極と
してその上にメッキ層が形成される。一般的にメッキ折
出法によるバンプ基板6では、透明導電膜層8はメッキ
時の陰極としての機能を有するとともに、バンプ基板6
に形成したバンプ金属3をインナーリード5へ圧着転写
する際に、バンプ金属3が容易に透明導電膜層8より剥
離する性質を備え、かつバンプ基板6の取扱時にはバン
プ金属3がバンプ基板6より剥離しない程度の接着力を
備えているものを用いる。このことより、バンプ基板6
にはテープキャリア4のインナーリード5へ圧着転写す
るバンプ金属3を形成することができる。しかし、この
とき、該バンプ基板6は第3図(B)に示すように、電解
メッキ処理によって絶縁保護膜層9の開孔部10にメッキ
層を形成するが、透明導電膜層8のシート抵抗により外
部接続用電極部11から遠ざかるにつれてメッキの折出量
が少なくなるので、バンプ基板6に折出されるメッキの
メッキ層の厚さの寸法均一性はあまり高精度ではないと
いう問題点を有していた。Further, in the bump metal 6 used for mounting, the transparent conductive film layer 8 is connected to the plating power source at the external connection electrode portion 11 at the end of the substrate and subjected to electrolytic plating treatment, whereby the insulating protective film layer 9 is formed. A plating layer is formed on the transparent conductive layer 8 as a cathode in the opening 10. Generally, in the bump substrate 6 formed by the plating method, the transparent conductive film layer 8 has a function as a cathode during plating, and
The bump metal 3 has a property of being easily separated from the transparent conductive film layer 8 when the bump metal 3 formed on the inner surface is pressure-transferred to the inner lead 5, and the bump metal 3 is removed from the bump substrate 6 when handling the bump substrate 6. Use one that has enough adhesive strength to prevent peeling. From this, the bump substrate 6
The bump metal 3 to be transferred by pressure bonding to the inner lead 5 of the tape carrier 4 can be formed thereon. However, at this time, as shown in FIG. 3 (B), the bump substrate 6 has a plating layer formed on the openings 10 of the insulating protective film layer 9 by electrolytic plating. Since the amount of protrusion of the plating decreases as the distance from the external connection electrode portion 11 increases due to the resistance, there is a problem that the dimensional uniformity of the thickness of the plating layer of the plating protruded on the bump substrate 6 is not very accurate. Was.
(発明の目的) 本発明は前述のバンプ金属形成における問題点に鑑み、
バンプ基板内に形成されるバンプ金属であるメッキ層の
厚さの高精度な均一化を図ることを目的としたバンプ金
属の形成方法およびその方法に用いるバンプ基板を提供
するものである。(Object of the Invention) In view of the above problems in the bump metal formation,
The present invention provides a bump metal forming method and a bump substrate used for the method for the purpose of achieving highly accurate and uniform thickness of a plating layer which is a bump metal formed in a bump substrate.
(発明の構成) 本発明は、バンプメッキ基板と透明導電膜層と絶縁保護
膜層と低抵抗金属層とからなり、前記絶縁保護膜層は所
望局部に開孔部を有し、前記低抵抗金属層はその形状が
前記開孔部より大きい開孔を備えた網目状のものであ
り、かつ前記開孔部と前記低抵抗金属層とまでの最短距
離が略同等であり、前記バンプメッキ基板の上層に透明
導電膜層を有し、前記透明導電膜層の上層に前記絶縁保
護膜層を有するとともに、前記低抵抗金属層を前記バン
プメッキ基板と前記透明導電膜層との間、または前記透
明導電膜層と前記絶縁保護膜層との間に有した構成によ
り、透明導電膜層の等価抵抗を低減させ、バンプ金属の
形成過程におけるメッキ層の金属折出速度の均一化を図
るとともに、メッキ層の層厚の均一化を図り、バンプ金
属の寸法精度を高めることができるものである。(Structure of the Invention) The present invention comprises a bump-plated substrate, a transparent conductive film layer, an insulating protective film layer, and a low-resistance metal layer, wherein the insulating protective film layer has an opening portion at a desired local portion, and has the low resistance. The metal layer has a mesh-like shape having openings larger than the openings, and the shortest distances between the openings and the low resistance metal layer are substantially equal to each other. A transparent conductive film layer as an upper layer, and the insulating protective film layer as an upper layer of the transparent conductive film layer, the low resistance metal layer between the bump plated substrate and the transparent conductive film layer, or With the structure provided between the transparent conductive film layer and the insulating protective film layer, the equivalent resistance of the transparent conductive film layer is reduced, and the metal protrusion speed of the plating layer in the process of forming the bump metal is made uniform, The thickness of the plating layer is made uniform and the bump metal The dimensional accuracy can be improved.
(実施例の説明) 以下、本発明の第1実施例について図面を参照しながら
説明する。第4図は本発明のバンプ基板を示す平面略
図、第5図は同局部拡大図、第6図は同断面拡大図、第
7図は他の構成の基板断面図、第8図はバンプ金属の形
成方法を示す工程図である。(Description of Embodiments) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a schematic plan view showing a bump substrate of the present invention, FIG. 5 is an enlarged view of the same portion, FIG. 6 is an enlarged view of the same cross section, FIG. 7 is a sectional view of a substrate of another structure, and FIG. 8 is a bump metal. FIG. 7 is a process drawing showing the method for forming the above.
第4図〜第6図に示すように、本発明の方法に用いるバ
ンプ基板は平面な面を有するガラス等からなるバンプメ
ッキ基板17の主平面全域に透明導電膜層18を均一に形成
し、同層18上には同層18とのオーミックコンタクト性を
有する低抵抗金属材料からなる電極金属配線網21を絶縁
保護膜層19の開孔部20の外周域を囲んだ形態となるよう
に形成してある。また、電極金属配線網21を含む透明導
電膜層18上には、SiO2膜域はホトレジスト膜の如き選択
開孔が可能な絶縁保護膜層19が全面を被覆せしめた構成
であり、絶縁保護膜層19は第5図、第6図のようにその
一部に開孔部20が形成してあり、同部位では前述の透明
導電膜層18の表面が露出した構成である。As shown in FIGS. 4 to 6, in the bump substrate used in the method of the present invention, the transparent conductive film layer 18 is uniformly formed on the entire main plane of the bump plating substrate 17 made of glass or the like having a flat surface. An electrode metal wiring network 21 made of a low resistance metal material having ohmic contact with the layer 18 is formed on the layer 18 so as to surround the outer peripheral area of the opening 20 of the insulating protective film layer 19. I am doing it. Further, on the transparent conductive film layer 18 including the electrode metal wiring network 21, the SiO2 film region has a structure in which the entire surface is covered with an insulating protective film layer 19 capable of selective opening such as a photoresist film. As shown in FIGS. 5 and 6, the layer 19 has an opening 20 formed in a part thereof, and the surface of the transparent conductive film layer 18 is exposed at the same portion.
さらに、透明導電膜層18と電極金属配線網21との構成
は、上述以外に第7図に示すような構造でもよい。すな
わち、バンプメッキ基板17の主面に対して予め電極金属
配線網21を形成した後、透明導電膜層18および絶縁保護
膜層19を順次被着せしめた構成である。Further, the structure of the transparent conductive film layer 18 and the electrode metal wiring network 21 may be the structure shown in FIG. 7 other than the above. That is, the electrode metal wiring network 21 is previously formed on the main surface of the bump-plated substrate 17, and then the transparent conductive film layer 18 and the insulating protective film layer 19 are sequentially applied.
以上のように構成されたバンプ基板について、以下その
動作について説明する。バンプ基板16の一端に設けた電
極金属配線網21からなる第4図に示した外部接続用電極
部22にメッキ用電源(図示せず)の陰極を接続し電解メ
ッキ(例えば、Au電解メッキ)処理を施した場合、メ
ッキはバンブ基板16の開孔部20で露出している透明導電
膜層18を陰極として同部位上に折出積層し、第8図(F)
に示したようなバンプ金属24が形成される。このとき、
バンプ基板16では低抵抗金属層による専用の電極金属配
線網21がバンプ金属形成用の開孔部20の周域に等距離で
形成されているので、透明導電膜層18の抵抗の影響を
あまり受けずにメッキを析出形成する。すなわち、バン
プ基板16上のあらゆる部位におけるメッキ条件の均一
化がなされ、メッキ速度の差異によるバンプ金属の寸法
精度のバラツキを抑制することができる。The operation of the bump substrate configured as described above will be described below. A cathode of a plating power source (not shown) is connected to the external connection electrode portion 22 shown in FIG. 4 formed of an electrode metal wiring network 21 provided at one end of the bump substrate 16 for electrolytic plating (eg, Au electrolytic plating). When the treatment is performed, plating is performed by stacking the transparent conductive film layer 18 exposed at the opening 20 of the bump substrate 16 as a cathode on the same portion as shown in FIG. 8 (F).
The bump metal 24 as shown in FIG. At this time,
In the bump substrate 16, a dedicated electrode metal wiring network 21 made of a low resistance metal layer is formed at equal distances in the peripheral region of the opening 20 for forming bump metal, so that the resistance of the transparent conductive film layer 18 is less likely to affect the resistance. The plating is deposited without being received. That is, the plating conditions are made uniform in all parts on the bump substrate 16, and the variation in the dimensional accuracy of the bump metal due to the difference in plating speed can be suppressed.
なお、本実施例のように透明導電膜層および絶縁保護膜
層およびバンプメッキ基板のいずれもに透明な材料を用
いた場合には、電極配線網およびバンプ金属を除くとバ
ンプ基板は透明な基板となるので、転写、ボンディング
時のアライメントを透過方式により実施することも可能
になるという効果が上記の効果に加えて生じる。When a transparent material is used for all of the transparent conductive film layer, the insulating protective film layer, and the bump-plated substrate as in this embodiment, the bump substrate is a transparent substrate except for the electrode wiring network and the bump metal. Therefore, the effect that it becomes possible to carry out the alignment at the time of transfer and bonding by the transmissive method is produced in addition to the above effect.
次にバンプ金属の形成方法について第8図(A)〜第8図
(F)を参照しながら説明する。まず、バンプメッキ基板1
7上の全面に低抵抗金属層23、例えば、銅、ニッケル等
の薄膜を蒸着または無電解メッキで形成する。次に、前
記低抵抗金属層23を選択エッチングして電極金属配線網
21を形成する。そして前記バンプメッキ基板17上に透明
導電膜層18、例えば酸化錫および酸化インジウムからな
る膜をスパッタ蒸着で形成する。それから、シリコンの
酸化膜またはシリコンの窒化膜またはシリコンの樹脂膜
で絶縁保護膜層19を形成する。その後、前記絶縁保護膜
層19を選択エッチングして開孔部20を形成する。そして
最後に、電気メッキ処理を行い、バンブ金属24を形成す
る。以上の形成方法によるバンプ金属24は、低抵抗金属
層からなる前記電極金属配線網21によってバンプ基板全
体の開孔部に均一に電流が供給されるので、寸法精度の
良いものとなる。Next, regarding the method of forming the bump metal, FIG. 8 (A) to FIG.
An explanation will be given with reference to (F). First, bump plating board 1
A low-resistance metal layer 23, for example, a thin film of copper, nickel or the like is formed on the entire surface of 7 by vapor deposition or electroless plating. Next, the low resistance metal layer 23 is selectively etched to form an electrode metal wiring network.
Form 21. Then, a transparent conductive film layer 18, for example, a film made of tin oxide and indium oxide is formed on the bump-plated substrate 17 by sputter deposition. Then, the insulating protective film layer 19 is formed of a silicon oxide film, a silicon nitride film, or a silicon resin film. Then, the insulating protection film layer 19 is selectively etched to form an opening 20. Finally, electroplating is performed to form the bump metal 24. The bump metal 24 formed by the above-described forming method has good dimensional accuracy because the electrode metal wiring network 21 made of a low resistance metal layer uniformly supplies current to the openings of the entire bump substrate.
なお、電極金属配線網21はバンプ基板17の上層に形成し
た透明導電膜層18の上層に形成しても上記の効果と同様
の効果を得ることができる。Even if the electrode metal wiring network 21 is formed on the transparent conductive film layer 18 formed on the bump substrate 17, the same effect as described above can be obtained.
(発明の効果) 以上のように本発明によれば、バンプ基板中に低抵抗金
属層である電極金属配線網を網目状に配置するので、メ
ッキ法によるバンプ金属の仮形成を行う場合でも、バン
プ金属の形成寸法のバラツキのない寸法精度の良いバン
プ金属の仮形成を行うことができるものである。(Effect of the invention) As described above, according to the present invention, since the electrode metal wiring network which is the low resistance metal layer is arranged in a mesh in the bump substrate, even when the bump metal is temporarily formed by the plating method, The bump metal can be temporarily formed with good dimensional accuracy without variation in the bump metal formation dimension.
第1図(A),(B)は一般的なテープキャリア法の断面略
図、第2図(A),(B),(C)は転写バンプボンディング法
を示す断面略図、第3図(A)は同バンプ基板の断面略
図、第3図(B)は同バンプ基板の平面略図、第4図は本
発明のバンプ基板の平面略図、第5図は同局部拡大図、
第6図は同断面図、第7図は他の構成の基板断面図、第
8図(A)〜(F)は本発明のバンプ金属の形成方法の各工程
を示す部分断面図である。 1…半導体チップ、 2…電極パッド、3,24…バンプ
金属、 4…テープキャリア、5…インナーリード、
6,16…バンプ基板、 7,17…バンプメッキ基板、
8,18…透明導電膜層、 9,19…絶縁保護膜層、 1
0,20…開孔部、 11,22…外部接続用電極部、 21…電極金属配線網、
23…低抵抗金属層。FIGS. 1 (A) and (B) are schematic sectional views of a general tape carrier method, FIGS. 2 (A), (B) and (C) are schematic sectional views showing a transfer bump bonding method, and FIG. 3 (A). ) Is a schematic sectional view of the bump substrate, FIG. 3B is a schematic plan view of the bump substrate, FIG. 4 is a schematic plan view of the bump substrate of the present invention, and FIG.
FIG. 6 is a sectional view of the same, FIG. 7 is a sectional view of a substrate having another structure, and FIGS. 8A to 8F are partial sectional views showing respective steps of the bump metal forming method of the present invention. 1 ... Semiconductor chip, 2 ... Electrode pad, 3, 24 ... Bump metal, 4 ... Tape carrier, 5 ... Inner lead,
6,16 ... bump substrate, 7,17 ... bump plated substrate,
8, 18 ... Transparent conductive film layer, 9, 19 ... Insulating protective film layer, 1
0,20 ... Opening part, 11,22 ... External connection electrode part, 21 ... Electrode metal wiring network,
23 ... Low resistance metal layer.
Claims (3)
する第1工程と、前記透明導電膜層の上層に絶縁保護膜
層を形成する第2工程と、前記絶縁保護膜層の所望局部
に開孔部を形成して前記透明導電膜層の一部に露出部位
を形成する第3工程と、前記露出部位を電極として前記
露出部位に電解メッキ金属を折出させる第4工程とを備
え、前記第1工程前、または前記第1工程と前記第2工
程との間、または前記第2工程と前記第3工程との間に
おいて、各々前記バンプメッキ基板上、透明導電膜層上
に低抵抗金属層を形成する工程を有するとともに、前記
低抵抗金属層の形状を網目状に形成し、かつ前記開孔部
と前記低抵抗金属層とまでの最短距離を略同等に形成し
たことを特徴とするバンプ金属の形成方法。1. A first step of forming a transparent conductive film layer on a bump-plated substrate, a second step of forming an insulating protective film layer on the transparent conductive film layer, and a desired local portion of the insulating protective film layer. A third step of forming an opening in the transparent conductive film layer to form an exposed portion on a part of the transparent conductive film layer; and a fourth step of protruding an electroplated metal to the exposed portion using the exposed portion as an electrode. , Before the first step, or between the first step and the second step, or between the second step and the third step, respectively on the bump-plated substrate and the transparent conductive film layer. In addition to having a step of forming a resistance metal layer, the shape of the low resistance metal layer is formed in a mesh shape, and the shortest distance between the aperture and the low resistance metal layer is formed to be substantially equal. And method for forming bump metal.
護膜層と低抵抗金属層とからなり、前記絶縁保護膜層は
所望局部に開孔部を有し、前記低抵抗金属層はその形状
が前記開孔部より大きい開孔を備えた網目状のものであ
り、かつ前記開孔部と前記低抵抗金属層とまでの最短距
離が略同等であり、前記バンプメッキ基板の上層に透明
導電膜層を有し、前記透明導電膜層の上層に前記絶縁保
護膜層を有するとともに、前記低抵抗金属層を前記バン
プメッキ基板と前記透明導電膜層との間、または前記透
明導電膜層と前記絶縁保護膜層との間に有したバンプ基
板。2. A bump-plated substrate, a transparent conductive film layer, an insulating protective film layer, and a low resistance metal layer, wherein the insulating protective film layer has an opening at a desired local portion, and the low resistance metal layer is The shape is a mesh with openings larger than the openings, and the shortest distances between the openings and the low-resistance metal layer are substantially equal to each other and transparent to the upper layer of the bump-plated substrate. A conductive film layer, the insulating protective film layer on the transparent conductive film layer, and the low-resistance metal layer between the bump-plated substrate and the transparent conductive film layer, or the transparent conductive film layer. And a bump substrate provided between the insulating protective film layer and the insulating protective film layer.
範囲第(2)項記載のバンプ基板。3. The bump substrate according to claim 2, wherein the bump-plated substrate is transparent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59060994A JPH067552B2 (en) | 1984-03-30 | 1984-03-30 | Method of forming bump metal and bump substrate used in the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59060994A JPH067552B2 (en) | 1984-03-30 | 1984-03-30 | Method of forming bump metal and bump substrate used in the method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60206157A JPS60206157A (en) | 1985-10-17 |
| JPH067552B2 true JPH067552B2 (en) | 1994-01-26 |
Family
ID=13158492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59060994A Expired - Lifetime JPH067552B2 (en) | 1984-03-30 | 1984-03-30 | Method of forming bump metal and bump substrate used in the method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067552B2 (en) |
-
1984
- 1984-03-30 JP JP59060994A patent/JPH067552B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60206157A (en) | 1985-10-17 |
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