JPH0675802A - Program memory switching system - Google Patents

Abstract

PURPOSE:To prevent an unnecessary switching operation from being repeated by stopping the subsequent switching operation, in the case of failing in the restart after a switching failure of a program memory. CONSTITUTION:A switching processing is executed by a fact that a control signal 17 from a PIO 9 is generated by a switching request, and a pulsative CPU reset signal 12 is outputted, and started by a program memory switched and a designated by flags 5, 6. At the time of its start processing, it is not started due to a trouble of the CPU 10, and in the case time-out of a watch dog timer part 7 is generated, the CPU reset signal 12 is generated again, but since a retry control output signal 15 is Low, it is released after a prescribed time and the restart processing is executed by a program before switching. When time-out of the watch dog timer part 7 is generated again by this restart processing, the CPU reset signal 12 is generated, but since the retry control output signal 15 is High, this CPU reset signal 12 is held. Accordingly, this restart processing is stopped by once.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program memory switching system, and more particularly to a switching system having a function of detecting a switching failure and a program restart function before switching.

[0002]

2. Description of the Related Art Conventionally, a switching system of two program memories of this type is a CP in which two program memories are mounted.
In the U circuit, it is used when switching to the program in the second memory while the program in the first memory is being executed.

Conventionally, as a switching method, each time a CPU is reset, which of the two program memories is to be executed is determined by two states of 0 or 1, and this CPU is placed. A method of switching by resetting is known.

In this method, the switching of the program memory is started by executing the reset of the CPU. The state of the toggle switch is identified in the startup process after the end of the reset, and the program on any of the program memories is executed according to this. If the CPU goes out of control at the time of startup by switching, the CPU is restarted by the watchdog timer.
Since the reset is generated and the rising process is re-executed (retry), the program before the switching is restarted.

[0005]

In this conventional program memory switching method, since the number of retries by resetting is not limited, startup by switching fails, and further restarting by the program before switching fails. In that case, the switching operation may not stop.

[0006]

When switching from a running first program to a waiting second program, the CPU is reset by a switching request and the second program is started up to switch, and this switching is performed. In a program switching system that automatically repeats the startup operation of the first program when it fails, by automatically resetting the CPU and holding it when the switching of the second program fails The rising operation of the first program is stopped once.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the CPU 1 includes a boot memory 2 in which a boot program 101 is written, a first program memory 3 in which a first program 201 is written, and a second program 202 in which a second program 202 is written. The program memory 4, the first flag 5 for identifying the program to be started up, the second flag 6 for identifying the processing state at the time of switching, the watchdog timer unit 7, and the retry control unit 8 are set. For parallel I0 (PI
O) 9 and data / address bus 18.
The flags 5 and 6 realize the function of the toggle switch in the conventional example.

The memories 2, 3, 4 and the flags 5, 6 are memories whose contents are retained even when the power is turned off. Further, the memories 3 and 4 and the flags 5 and 6 are electrically writable memories. Also, flags 101, 201, 20
2 are arranged in different address spaces. C
The PU 1 executes the boot program 101 on the memory 2 when the power is turned on or the reset is released. By the boot program 101 on the memory 2, the first program 201 on the memory 3 or the memory 4
The execution is transferred to the second program 202 above.

The watchdog timer section 7 is a clock section 1
The clock 11 supplied by 0 is counted, and the CPU
If 1 does not clear the internal timer of the watchdog timer unit 7 for a certain time or more (timeout occurs),
The CPU 1 is reset by the CPU reset signal 12. The retry control unit 8 controls the number of retries according to the time-out of the watchdog timer unit 7 according to the setting made by the PIO 9.

FIG. 2 is a circuit diagram of the watchdog timer section 7 and the retry control section 8 in FIG. Counter 72
Counts clock 11. Count value is CPU1
Is reset through the decoder 71 and OR77. When the count value is not reset for a certain period of time, the CPU reset signal 12 is generated from the counter 72 through NOT75 and OR74. Furthermore, when the clock 11 is continuously input for a certain period of time, the CPU reset signal 12 is released (retry operation). The D flip-flop (D-FF) 81 outputs the output 802 of the counter 72 to C
It operates as an LK input and controls the input clock 11 of the counter 72 via the NAND 83 and AND 76. Reset and set of flip-flop 8 is signal 1 of PIO9
6 and 17

FIG. 3 is a timing chart of each part in FIG. 4 and 5 are the same as the embodiment of FIG.
It is a flowchart showing processing executed by each program.

Next, regarding the operation of the circuit of FIG. 1, from the first program 201 on the memory 3 to the second program 201 on the memory 4.
3 and 4 when switching to the program 202 of FIG.
Will be described with reference to. In FIG. 4A, first, flag 5 is set to 2 (process 1010) and flag 6 is set to 0 (1020). Next, by controlling the output 17 of the PIO, the Q output 803 of the D-FF 81 becomes High.
It is set to h (1030) and the software of the CPU 1 is reset (1040) (time t1 in FIG. 3). C
After the software reset of PU1, the boot program 101 on the memory 2 is executed (1100).

In FIG. 4B, the first program 10
In the case of 1, the value of the flag 6 is 0, so that it is recognized as the switching process (1110), and the flag 6 is set to 1 (1120). Next, since the value of the flag 5 is 2, the program to be started up is the second program 202, and the entry address of the second program 202 is jumped (1130). When the second program 202 normally starts up in FIG. 4C, the flag 6 is reset to 0 (1230), the flip-flop 10 is reset (1240), and normal switching is performed (1250).

When the CPU stops operating or runs out during the start-up process of the second program 202, or a specific abnormal state is detected by the second program 202 (1220), the CPU stops operating. . (126
0), the timer 72 times out in FIG. 3 (at time t3), and the first CPU reset signal 12 is generated. At this time, the output 15 of the retry control unit is Lo.
Since it is w and the clock input 11 continues, the CPU reset signal 12 is released after a certain period of time (time t4), and thereby the boot program 101 is executed again (1
100).

Returning to FIG. 4B, the boot program 10
In the case of 1, the value of the flag 6 is 1, so that it is recognized that the process is a restart process due to a switching failure (1100). Next, since the value of the flag 5 is 2, the program to be restarted is the first program 201, the flag 5 is 1 (1150), and the entry address of the first program 201 is jumped (1160). When the first program 201 normally starts up in FIG. 4D, the flag 6 is reset to 0 (1330), the flip-flop 19 is reset (1340), and the restarting is completed (1350).

CP during the start-up process of the program 201
When the operation of U is stopped, a runaway occurs, or a specific abnormal state is detected by the program 201 (1320) C
When the operation of the PU is stopped (1360), a time-out of the timer 72 occurs in FIG. 3 (at time t6),
The second CPU reset signal 12 is generated. At this time, the output 15 of the retry control unit becomes High, the clock input 11 is stopped, and the CPU reset signal 12 is held in reset (1400).

In FIG. 5, when switching from the second program 202 on the program memory 4 to the first program 201 on the memory 3, the initial value of the flag 5 is 1,
Program 20 when the program to start is switched
1. At the time of restarting, the operation is the same as above except that the program 202 is set.

By inserting a frequency dividing circuit for dividing the CLK input signal 802 of the D-FF 81 in FIG. 2, the number of restarting processes of the first program 201 is designated according to the frequency dividing ratio. can do.

[0019]

As described above, the program memory switching system of the present invention is provided with the retry control circuit capable of limiting the number of retries performed after the reset due to the timer-out of the watchdog timer during the switching operation.
If the start-up due to the switching fails and the restart before the program before the switching fails, the reset state is held, and there is an effect that the repetition of the unnecessary switching operation is stopped.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a watchdog timer unit and a retry control unit in FIG.

FIG. 3 is a timing chart of signals of respective parts in FIG.

FIG. 4 is a first flowchart in FIG. 1 (when switching from the first program 201 to the second program 202) (a) Initial setting executed by the first program 201 (b) Execution by the boot program 101 Processing (c) Startup processing at the time of switching executed by the second program 202 (d) Re-startup processing by switching failure executed by the first program 201

5 is a second flowchart in FIG. 1 (when the first program 201 is switched from the second program 202) (a) Initial setting executed by the second program 202 (b) Processing executed by the boot program 101 (C) Startup processing at the time of switching executed by the first program 201 (d) Re-startup processing by switching failure executed by the second program 202

[Explanation of symbols]

 1 CPU 2, 3, 4 Memory 5, 6 Flag 7 Watchdog Timer Section 8 Retry Control Section 9 PIO 10 CLK Generation Section 71 Decoder 72 Counter 73 Power Supply Voltage Monitoring Circuit 81 D-FF 12 CPU Reset Signal 15 Retry Control Signal 11 CLK

Claims (2)

[Claims] 1. When switching from a running first program to a waiting second program, a CPU is issued by a switching request.
Switch by resetting and starting up with the second program, and when this switching fails, the CPU is automatically reset again and the first program before switching is started up, and this startup fails again. When the switching of the second program is failed, the CPU is automatically reset and held in the program switching system in which the startup operation of the first program is automatically repeated. A program switching method characterized in that the start-up operation of the first program is stopped once. 2. A first abnormality detecting function for resetting the CPU by detecting the CPU operation stop or runaway, and releasing the reset state after the CPU reset state by the first abnormality detecting function is continued for a certain period of time. And a function of performing a startup process for switching from the first program to the second program on the second program memory by a program switching request while running the first program on the first program memory. , A program memory having a function of starting the first program when a reset by the first abnormality detection function and a reset release by the retry function occur during execution of the start-up process of the second program In the switching method, the retry function is a reset state of the CPU generated during the startup process of the second program. A program memory switching system having a function of releasing the reset state after continuing the state for a certain period of time and holding the reset state generated during the start-up process of the first program as it is.