JPH067596B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH067596B2 JPH067596B2 JP59015213A JP1521384A JPH067596B2 JP H067596 B2 JPH067596 B2 JP H067596B2 JP 59015213 A JP59015213 A JP 59015213A JP 1521384 A JP1521384 A JP 1521384A JP H067596 B2 JPH067596 B2 JP H067596B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- forming
- region
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔技術分野〕 本発明は高速作動を可能とし、かつ一方では高集積化や
耐圧の向上を可能にした半導体装置およびその製造方法
に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor device capable of high-speed operation and, at the same time, highly integrated and improved withstand voltage, and a manufacturing method thereof.
近年のＩＣ，ＬＳＩ等の半導体装置は益々高集積化が図
られており、ＭＯＳＦＥＴ（ＭＯＳ型電界効果トランジ
スタ）では短チャネル化が図られている。しかしなが
ら、短チャネル化を進めると、いわゆる短チャネル効果
で生じるしきい値のゲート長依存性などの副作用を防ぐ
上からソース・ドレイン領域を浅くしなければならず、
これらソース・ドレイン領域の抵抗が大となって素子の
高速化の障害になる。また、短チャネル化に伴なって耐
圧にも問題が生じることとなり、従来、ソース・ドレイ
ン領域を高濃度の領域主部と、低濃度の領域とからなる
プロファイルのLightly Doped Drain構造が提案されて
きている（ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＳ ＯＮ
ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ，ＶＯＬ ＥＤ−
２９．ＮＯ．４ APRIL１９８２ Ｐ５９０〜）。しか
し、抵抗が相対的に小さい領域主部が更に微小化されて
しまい、前述した高抵抗化を助長することになる。ま
た、ソース・ドレイン領域の特に高濃度部位が直接逆導
電型の基板やウエルに接している構成であることから、
接合容量が大きくなると共に、これをＣ−ＭＯＳ構造に
用いたときにはラッチアップ耐圧が低くなり、素子分離
寸法を大きくしなければならない等高集積化の障害とな
る。In recent years, semiconductor devices such as ICs and LSIs have been highly integrated, and MOSFETs (MOS field effect transistors) have been shortened in channel. However, as the length of the channel is shortened, the source / drain regions must be shallow in order to prevent side effects such as the gate length dependence of the threshold, which is caused by the so-called short channel effect.
The resistance of these source / drain regions becomes large, which impedes the speedup of the device. In addition, with the shortening of the channel, a problem with breakdown voltage will also arise, and conventionally, a Lightly Doped Drain structure with a profile consisting of a source / drain region with a high-concentration region main part and a low-concentration region has been proposed. I have (IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL ED-
29. NO. 4 APRIL1982 P590-). However, the main portion of the region where the resistance is relatively small is further miniaturized, which promotes the above-described high resistance. In addition, since the source / drain region is particularly in a high-concentration region in direct contact with the substrate or well of the opposite conductivity type,
When the junction capacitance becomes large and the C-MOS structure is used, the latch-up breakdown voltage becomes low, which is a hindrance to high integration such as increasing the element isolation size.
本発明の目的は短チャネル化を図ったＭＯＳＦＥＴのソ
ース・ドレイン領域の低抵抗化を図って高速化を可能に
すると共に、その耐圧の向上および接合容量の低減を可
能とし、更に高集積化を達成することのできる半導体装
置を提供することにある。The object of the present invention is to reduce the resistance of the source / drain region of the MOSFET having a short channel to achieve high speed, and at the same time, to improve its withstand voltage and decrease the junction capacitance, thereby further increasing the integration. It is to provide a semiconductor device that can be achieved.
また、本発明の他の目的は前記した高速作動可能でかつ
高集積化を達成する半導体装置の好適な製造方法を提供
することにある。Another object of the present invention is to provide a suitable method of manufacturing a semiconductor device which can operate at high speed and achieve high integration.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel characteristics of the present invention are
It will be apparent from the description of the present specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.
すなわち、オフセット構造に形成したＭＯＳＦＥＴのソ
ース・ドレイン領域における領域主部を深く形成すると
共に、この領域主部と基板側との界面に絶縁膜を介在さ
せる構成とすることにより、耐圧の向上はもとよりソー
ス・ドレイン領域の見かけ上の深さを大きくして低抵抗
化、つまり高速化を達成し、更に接合容量の低減を図
り、しかも短チャネル化により高集積化を達成するもの
である。That is, by forming the region main portion in the source / drain region of the MOSFET formed in the offset structure deeply and interposing the insulating film at the interface between the region main portion and the substrate side, not only the breakdown voltage is improved. By increasing the apparent depths of the source / drain regions to achieve low resistance, that is, high speed, further reduction of junction capacitance, and further shortening of the channel to achieve high integration.
また、ソース・ドレイン領域のオフセット部位を形成し
た後に領域主部の部位に溝を形成し、この溝の表面に絶
縁膜を形成した上で溝内に導電材料を充填することによ
り、前記高速作動型、高集積型の半導体装置の製造を完
成するものである。Further, after forming the offset portion of the source / drain region, a groove is formed in the main portion of the region, an insulating film is formed on the surface of the groove, and then the conductive material is filled in the groove, thereby achieving the high speed operation. To complete the manufacture of semiconductor devices of high-density type.
第１図は本発明方法を適用して得られたＮ型ＭＯＳＦＥ
Ｔの１実施例を示している。即ち、Ｐ型のシリコン半導
体基板２の主面上には選択酸化法（ＬＯＣＯＳ法）で形
成したフィールド絶縁膜３を設けて活性領域を画成し、
この活性領域内にＮ−ＭＯＳＦＥＴ１を構成している。
このＮ−ＭＯＳＦＥＴ１はゲート絶縁膜４上に形成した
ゲート電極５と、Ｎ型不純物をドープさせたソース・ド
レイン領域６、６とで構成しており、特にソース・ドレ
イン領域は不純物濃度の低い（Ｎ−）部分７と、７と、
これらの各外側に連続する不純物濃度の高い（Ｎ＋）領
域主部８、８とで形成している。そして、前記領域主部
８、８は基板２の内方に向かって深く形成して低抵抗化
を図っている。また、領域主部８、８と基板２との界面
にはシリコン酸化膜（SiO2膜）からなる絶縁膜９、９を
形成し、各領域主部８、８における接合容量の低減を図
っている。図中、１０，１１はSiO2，ＰＳＧの層間絶縁
膜、１２はＡｌ配線である。FIG. 1 shows an N-type MOSFE obtained by applying the method of the present invention.
An example of T is shown. That is, a field insulating film 3 formed by a selective oxidation method (LOCOS method) is provided on the main surface of a P-type silicon semiconductor substrate 2 to define an active region,
The N-MOSFET 1 is formed in this active region.
This N-MOSFET 1 is composed of a gate electrode 5 formed on a gate insulating film 4 and source / drain regions 6 and 6 doped with N-type impurities. Particularly, the source / drain region has a low impurity concentration ( N − ) portions 7 and 7,
They are formed by the (N + ) region main portions 8 and 8 having a high impurity concentration which are continuous to the outside of each of these. The area main parts 8 and 8 are deeply formed inward of the substrate 2 to reduce the resistance. Insulating films 9 and 9 made of a silicon oxide film (SiO 2 film) are formed at the interface between the region main parts 8 and 8 to reduce the junction capacitance in each of the region main parts 8 and 8. There is. In the figure, 10 and 11 are SiO 2 and PSG interlayer insulating films, and 12 is an Al wiring.
次に以上の構成のＮ−ＭＯＳＦＥＴ１の製造方法を第２
図(A)〜(I)の工程図に基づいて説明する。Next, a second method for manufacturing the N-MOSFET 1 having the above configuration will be described.
A description will be given based on the process diagrams of FIGS.
先ず、第２図(A)のようにＰ型シリコン基板２の主面に
ＬＯＣＯＳ法によりフィールド絶縁膜（SiO2）３を形成
して活性領域を画成すると共に、この活性領域上にゲー
ト絶縁膜（SiO2）４を形成し、更にその上にポリシリコ
ン層を形成した上でこれをパターニングしてゲート電極
５を形成する。しかる後に不純物としてリン(P)を自己
整合によって基板主面にドープさせ、オフセット部７、
７に相当する低濃度のＮ−層７ａ、７ａを形成する。First, as shown in FIG. 2 (A), a field insulating film (SiO 2 ) 3 is formed on the main surface of a P-type silicon substrate 2 by the LOCOS method to define an active region, and a gate insulating film is formed on the active region. A film (SiO 2 ) 4 is formed, a polysilicon layer is further formed on the film, and this is patterned to form a gate electrode 5. Then, phosphorus (P) is doped as an impurity into the main surface of the substrate by self-alignment, and the offset portion 7,
The low concentration N − layers 7a and 7a corresponding to No. 7 are formed.
次いで、同図(B)のようにシリコンナイトライド膜（Si3
N4）１３およびSiO2膜１４をＣＶＤ法により全面に形成
し、その後これを反応成イオンエッチング法（ＲＩＥ）
によりエッチング除去することにより、同図(C)のよう
にゲート電極５の両側にサイドウオール１５、１５を形
成する。このとき、SiO2膜１４を比較的厚く形成してお
けば、ゲート電極５における断面形状とＲＩＥ法の関係
により、ゲート電極５上にもSiO2膜１４とSi3N4膜１３
を若干残すことができる。そして、このサイドウオール
１５、１５をマスクとしてソース・ドレイン領域６、６
に前記Ｎ−層７ａ、７ａと同じ深さの溝１６、１６をエ
ッチング形成する。Then, as shown in FIG. 3B, a silicon nitride film (Si 3
N 4 ) 13 and SiO 2 film 14 are formed on the entire surface by the CVD method, and then this is formed by reactive ion etching (RIE).
Then, the side walls 15 and 15 are formed on both sides of the gate electrode 5 as shown in FIG. At this time, if the SiO 2 film 14 is formed relatively thick, the SiO 2 film 14 and the Si 3 N 4 film 13 are also formed on the gate electrode 5 due to the relationship between the cross-sectional shape of the gate electrode 5 and the RIE method.
Can be left a little. The source / drain regions 6 and 6 are formed by using the sidewalls 15 and 15 as masks.
Then, trenches 16 and 16 having the same depth as the N − layers 7a and 7a are formed by etching.
次に、再びSi3N4膜（第２Si3N4膜）１７とSiO2膜（第２
SiO2膜）１８をＣＶＤ法により全面に形成し、かつこれ
をＲＩＥ法によりエッチング処理することにより、同図
(D)のように前記サイドウオール１５、１５の両側ない
し前記溝１６、１６の内立面に第２サイドウオール１
９、１９を形成する。そして、再びこの第２のサイドウ
オール１９、１９をマスクとしそ基板２をエッチング
し、前記溝１６、１６の下側に同図(E)のように、更に
深い新たな溝２０、２０を形成する。Next, again the Si 3 N 4 film (second Si 3 N 4 film) 17 and the SiO 2 film (second
A SiO 2 film 18 is formed on the entire surface by the CVD method, and this is etched by the RIE method.
As shown in (D), the second side wall 1 is provided on both sides of the side walls 15 and 15 or on the inner surface of the grooves 16 and 16.
9 and 19 are formed. Then, using the second sidewalls 19 and 19 again as a mask, the substrate 2 is etched to form deeper new grooves 20 and 20 below the grooves 16 and 16 as shown in FIG. To do.
次いで、同図(F)のように、第２SiO2膜１８をエッチン
グ除去した上で溝２０、２０内面を酸化して酸化膜９、
９を絶縁膜として形成する。このとき、領域７、７の側
面は第２SiO2膜１７、１７に被覆されているので酸化膜
が形成されることはない。しかる上で、第２SiO3N4膜１
７を除去した後、同図(G)のように、高濃度にＮ型不純
物をドープしたポリシリコン８ａを全面に堆積させる。
このとき、溝２０、２０はポリシリコン８ａにより充填
される。そして、このポリシリコン８ａを表面からエッ
チングバックすれば、前記溝２０、２０内のポリシリコ
ン８ａのみが残され、同図(H)のように、高濃度不純物
（Ｎ＋）の領域主部８、８が構成される。この領域主部
８、８は低濃度不純物の前記オフセット部７、７と接続
状態にあり、これにより各領域主部８、８と領域７、７
とでソース・ドレイン領域６、６を形成する。Next, as shown in FIG. 6F, the second SiO 2 film 18 is removed by etching, and then the inner surfaces of the grooves 20 and 20 are oxidized to form an oxide film 9,
9 is formed as an insulating film. At this time, since the side surfaces of the regions 7 and 7 are covered with the second SiO 2 films 17 and 17, no oxide film is formed. Then, the second SiO 3 N 4 film 1
After removing 7, the polysilicon 8a heavily doped with N-type impurities is deposited on the entire surface as shown in FIG.
At this time, the trenches 20 and 20 are filled with the polysilicon 8a. Then, when this polysilicon 8a is etched back from the surface, only the polysilicon 8a in the trenches 20 and 20 is left, and as shown in FIG. 7H, the high concentration impurity (N + ) region main portion 8 is formed. , 8 are configured. The area main parts 8 and 8 are connected to the offset parts 7 and 7 of low-concentration impurities, whereby the area main parts 8 and 8 and the areas 7 and 7 are connected.
And form source / drain regions 6, 6.
しかる上で、ゲート電極５のSiO2膜１４とSi3N4膜１３
を除去し、改めて酸化処理して同図(I)のようにゲート
電極５ないしソース・ドレイン領域６、６上にSiO2膜１
０を形成する。更にその上にＰＳＧ膜１１を形成し、か
つコンタクトホールの形成後にＡｌ配線１２、１２を形
成すれば第１図のＮ−ＭＯＳＦＥＴ１を完成することが
できる。Then, the SiO 2 film 14 and the Si 3 N 4 film 13 of the gate electrode 5 are
Is removed, and oxidation treatment is performed again, and the SiO 2 film 1 is formed on the gate electrode 5 or the source / drain regions 6 and 6 as shown in FIG.
Form 0. Further, a PSG film 11 is formed thereon, and Al wirings 12 are formed after the contact holes are formed, whereby the N-MOSFET 1 shown in FIG. 1 can be completed.
以上のように形成されたＮ−ＭＯＳＦＥＴ１によれば、
ソース・ドレイン領域６、６は不純物濃度の低い領域
７、７と、濃度の高い領域主部８、８とで形成され、か
つゲート電極５とで構成されていることになる。したが
って、短チャネル化した場合にもその耐圧を高いものに
できる。一方、ソース・ドレイン領域６、６にこの構造
により、領域の広い部分を占める領域主部８、８の深さ
を大きくできるのでその低抵抗化を図り、高速化を実現
できる。この場合、領域７、７は従来通りであり、短チ
ャネル化に伴なうしきい値のゲート長依存性の副作用が
生じることはない。更に、領域主部８、８と基板２との
界面には絶縁膜９、９を形成しているので、ソース・ド
レイン領域６、６全体の接合容量を大幅に低減すること
もできる。結局、短チャネル化に伴なう種々の不具合を
防止でき、素子の微細化を図って高集積化を達成でき
る。According to the N-MOSFET 1 formed as described above,
The source / drain regions 6 and 6 are formed of regions 7 and 7 having a low impurity concentration and region main portions 8 and 8 having a high impurity concentration, and are composed of the gate electrode 5. Therefore, even if the channel is shortened, the breakdown voltage can be increased. On the other hand, with this structure in the source / drain regions 6 and 6, the depth of the region main portions 8 and 8 occupying a wide region can be increased, so that the resistance can be reduced and the speed can be increased. In this case, the regions 7 and 7 are the same as in the conventional case, and the side effect of the gate length dependency of the threshold value due to the shortening of the channel does not occur. Furthermore, since the insulating films 9, 9 are formed at the interfaces between the region main parts 8, 8 and the substrate 2, the junction capacitance of the source / drain regions 6, 6 as a whole can be significantly reduced. After all, various problems associated with the shortening of the channel can be prevented, and the device can be miniaturized to achieve high integration.
ここで、領域主部８、８の絶縁膜９、９は素子間分離用
の絶縁膜として利用することもでき、したがって第３図
のように２個のＭＯＳＦＥＴ１Ａ、１Ｂを近接して配置
することもできる。この構造を同図のように、Ｐウエル
２１、Ｎウエル２２上に形成したＮ−ＭＯＳＦＥＴ１
Ａ、Ｐ−ＭＯＳＦＥＴ１ＢからなるＣ−ＭＯＳデバイス
に適用した場合には、高集積化、高速度化に加えてラッ
チアップ耐圧の向上も可能とされる。第３図中、第１図
に対応する部分には同一符号を付してある。Here, the insulating films 9 and 9 of the region main parts 8 and 8 can also be used as an insulating film for element isolation, so that two MOSFETs 1A and 1B should be arranged close to each other as shown in FIG. You can also This structure has the N-MOSFET 1 formed on the P well 21 and the N well 22 as shown in FIG.
When applied to a C-MOS device composed of A and P-MOSFET 1B, not only high integration and high speed but also latch-up breakdown voltage can be improved. In FIG. 3, those parts corresponding to those in FIG. 1 are designated by the same reference numerals.
(1) ＭＯＳＦＥＴのソース・ドレイン領域を低不純物
濃度領域と領域主部とからなるオフセット構造としてい
るので、耐圧の向上を図ることができる。(1) Since the source / drain regions of the MOSFET have an offset structure composed of the low impurity concentration region and the region main portion, the breakdown voltage can be improved.
(2) ソース・ドレイン領域の領域主部のみを深く形成
しているので、短チャネル化に伴なうしきい値のゲート
長依存性の副作用を防止する一方で、ソース・ドレイン
領域の低抵抗化を達成でき、高速化を達成できる。(2) Since only the main part of the source / drain region is deeply formed, the side effect of the gate length dependence of the threshold value accompanying the shortening of the channel is prevented, while the resistance of the source / drain region is reduced. Can be achieved, and high speed can be achieved.
(3) 領域主部と基板との界面に絶縁膜を形成している
ので、接合容量の低減を図ることができ、高速化を助長
すると共に動作の安定化を図ることができる。(3) Since the insulating film is formed at the interface between the main part of the region and the substrate, it is possible to reduce the junction capacitance, promote higher speed, and stabilize the operation.
(4) 短チャネル化によっても耐圧の向上、高速化等を
達成できるので、素子の微細化を進めて高集積化を達成
できる。(4) Since the breakdown voltage can be improved and the speed can be increased even by shortening the channel, it is possible to advance the miniaturization of elements and achieve high integration.
(5) ゲート電極の自己整合を利用したエッチング技術
により溝を形成し、溝内面の酸化技術により絶縁膜を形
成し、かつポリシリコンの堆積、エッチングバック技術
によりソース・ドレインの領域主部を形成できるので、
特殊な技術を必要とすることなく、しかも従来のＭＯＳ
ＦＥＴの製造工程に比べて大幅に工程数を増加すること
なく高耐圧、高速、高集積度の半導体装置を製造するこ
とができる。(5) Grooves are formed by etching technology that utilizes self-alignment of gate electrodes, an insulating film is formed by oxidation technology on the inner surface of the groove, and source / drain region main parts are formed by polysilicon deposition and etching back technology. Because you can
Conventional MOS without the need for special technology
It is possible to manufacture a semiconductor device having a high breakdown voltage, high speed, and a high degree of integration without significantly increasing the number of steps as compared with the FET manufacturing process.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、ソース・ド
レイン領域の領域主部を高濃度不純物ポリシリコンに代
えて金属又は金属シリサイドを使用してもよく、低抵抗
化を一層向上することができる。また、溝の形成にはホ
トリソグラフィ技術を利用した選択エッチング法を利用
してもよい。更に、各膜の形成法やポリシリコンの堆積
法にはＣＶＤ法の外種々の方法が利用できる。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Nor. For example, a metal or metal silicide may be used instead of the high-concentration impurity polysilicon in the main part of the source / drain region, and the lowering of resistance can be further improved. Alternatively, a selective etching method using a photolithography technique may be used for forming the groove. Further, in addition to the CVD method, various methods can be used for forming each film and depositing polysilicon.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である基本ＭＯＳＦＥＴに
適用した場合について説明したが、それに限定されるも
のではなくこのＭＯＳＦＥＴを素子とするＩＣ、ＬＳＩ
の全てに適用することができ、特に高速、高集積型の半
導体装置に有効に適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to the basic MOSFET which is the field of application as the background has been described, but the present invention is not limited to this, and ICs and LSIs using this MOSFET as an element are described.
Can be applied to all of the above, and can be effectively applied to a high-speed and highly integrated semiconductor device.
第１図は本発明の一実施例の断面図、 第２図(A)〜(I)は製造工程の断面図、 第３図は変形例の断面図である。 １，１Ａ，１Ｂ…ＭＯＳＦＥＴ、２…半導体基板、３…
フィールド絶縁膜、４…ゲート絶縁膜、５…ゲート電
極、６…ソース・ドレイン領域、７…低不純物濃度領
域、８…領域主部、９…絶縁膜、１０…SiO2膜、１１…
ＰＳＧ膜、１５…サイドウオール、１６…溝、１９…第
２サイドウオール、２０…溝、２１…Ｐウエル、２２…
Ｎウエル。FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 (A) to (I) are sectional views of a manufacturing process, and FIG. 3 is a sectional view of a modified example. 1, 1A, 1B ... MOSFET, 2 ... Semiconductor substrate, 3 ...
Field insulating film, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Source / drain region, 7 ... Low impurity concentration region, 8 ... Region main part, 9 ... Insulating film, 10 ... SiO 2 film, 11 ...
PSG film, 15 ... Side wall, 16 ... Groove, 19 ... Second side wall, 20 ... Groove, 21 ... P well, 22 ...
N well.
Claims (1)
しこの絶縁膜で画成された活性領域を形成する工程と、 上記活性領域の表面の一部にゲート絶縁膜を介してゲー
ト電極を形成する工程と、 上記ゲート電極をマスクとして上記活性領域表面に不純
物を導入して上記ゲート電極の両側に一対の低濃度の半
導体領域を形成する工程と、 上記ゲート電極および低濃度半導体領域の上に絶縁膜を
形成しこれを反応性イオンエッチングで除去して上記ゲ
ート電極の側壁に第１のサイドウォールを形成する工程
と、 上記ゲート電極部分および第１のサイドウォールをマス
クとして上記ゲート電極の両側の活性領域表面に上記低
濃度半導体領域の深さと同程度の溝を形成する工程と、 上記ゲート電極部分および溝の上に絶縁膜を形成しこれ
を反応性イオンエッチングで除去して上記ゲート電極の
側壁から上記低濃度半導体領域の側壁にかけて第２のサ
イドウォールを形成する工程と、 上記ゲート電極部分および第２のサイドウォールをマス
クとしてエッチングにより上記溝の底を更に深く掘り下
げる工程と、 上記溝の内面に絶縁膜を形成する工程と、 上記第２のサイドウォールを除去し、上記溝内に高濃度
に不純物が導入された半導体材料を充填して上記低濃度
半導体領域とそれぞれ接する一対の高濃度半導体領域を
形成する工程と、 上記高濃度半導体領域の表面に絶縁膜を形成してコンタ
クトホールを開け上記高濃度半導体領域にそれぞれ接す
る電極を形成する工程と、 を含むことを特徴とする半導体装置の製造方法。1. A step of selectively forming an insulating film on a main surface of a semiconductor substrate to form an active region defined by the insulating film, and a part of the surface of the active region via a gate insulating film. Forming a gate electrode, introducing impurities into the surface of the active region using the gate electrode as a mask to form a pair of low-concentration semiconductor regions on both sides of the gate electrode, the gate electrode and the low-concentration semiconductor Forming an insulating film on the region and removing it by reactive ion etching to form a first sidewall on the side wall of the gate electrode; and using the gate electrode portion and the first sidewall as a mask, The step of forming a groove on the surface of the active region on both sides of the gate electrode to the same extent as the depth of the low-concentration semiconductor region, and the step of forming an insulating film on the gate electrode portion and the groove and making them reactive. A step of forming a second sidewall from the sidewall of the gate electrode to the sidewall of the low-concentration semiconductor region by removing it by on-etching; and etching the bottom of the groove by using the gate electrode portion and the second sidewall as a mask. To a deeper depth, a step of forming an insulating film on the inner surface of the trench, a step of removing the second sidewall, and filling the trench with a semiconductor material in which impurities are introduced at a high concentration. Forming a pair of high-concentration semiconductor regions that are in contact with the high-concentration semiconductor regions, and forming an insulating film on the surface of the high-concentration semiconductor regions to open contact holes and form electrodes that are in contact with the high-concentration semiconductor regions. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015213A JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59015213A JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60161669A JPS60161669A (en) | 1985-08-23 |
| JPH067596B2 true JPH067596B2 (en) | 1994-01-26 |
Family
ID=11882592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59015213A Expired - Lifetime JPH067596B2 (en) | 1984-02-01 | 1984-02-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067596B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2886858B2 (en) * | 1986-08-11 | 1999-04-26 | テキサス インスツルメンツ インコーポレイテツド | Integrated circuit |
| DE19749378B4 (en) * | 1997-11-07 | 2006-10-26 | Infineon Technologies Ag | MOS transistor and method for its production |
| DE10246718A1 (en) | 2002-10-07 | 2004-04-22 | Infineon Technologies Ag | Field effect transistor comprises a semiconductor substrate, a source recess and a drain recess formed in the substrate, a recessed insulating layer, an electrically conducting filler layer, a gate dielectric, and a gate layer |
| CN103426753B (en) * | 2012-05-14 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of source-drain area and MOS device |
-
1984
- 1984-02-01 JP JP59015213A patent/JPH067596B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60161669A (en) | 1985-08-23 |
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