JPH067659B2 - Reader - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an apparatus for optically reading a document or the like using a plurality of light receiving elements.

BACKGROUND ART FIG. 1 is a diagram showing a configuration of a typical prior art facsimile transmitter. A so-called photo sensor array of a facsimile transmitter includes a plurality of light receiving / detecting units U1 to U.
It consists of n. In the figure, the photodetection units U1 to Un
The configuration of is shown by its equivalent circuit. An amorphous silicon photoconductor is placed on the common electrode 1,
The photodiodes D1 to D1 arranged in a line in the width direction of the document.
Configure Dn. The photodiodes D1 to Dn are individually grounded to the line 2 via the analog switches S1 to Sn. The common electrode 1 has a stray capacitance CS, and a load resistance RL and a bias power supply E are connected between the line 3 and the line 2 connected to the common electrode 1. The analog switches S1 to Sn are sequentially turned on and scanned by the control circuit 4 including a shift register or the like. For example, when the analog switch S1 is turned on,
The remaining analog switches S2 to Sn are cut off. Next, the analog switch S2 is turned on, and all the remaining analog switches S1 and S3 to Sn are turned off. The photodiodes D1 to Dn have storage capacitors C11 to Cn1. Further, the analog switches S1 to Sn have an input capacitance C1.
2 to Cn2 and conduction resistances R1 to Rn. When the photodiodes D1 to Dn receive light, the analog switch S
When 1 to Sn become conductive, the bias power source E causes the load resistance R
A current flows through L, and a waveform corresponding to the amount of received light is output to the amplifier 5 via the coupling capacitor CP connected to the line 3.
Is output to. The waveform amplified by the amplifier 5 is input to the sample hold circuit 6. The sample and hold circuit includes two operational amplifiers A1 and A2, an analog switch SA, and a hold capacitor CA that holds a signal, and the analog switch SA is controlled by the control circuit 4. The signal output from the amplifier 5 is a differential waveform, and its peak value is held by the sample hold circuit 6. The signal held by the sample hold circuit 6 is A / D (analog / digital)
It is input to the converter 7, converted into a digital value, and then output to the output terminal 8 as a digitized image signal.
2 (1) shows the differential waveform input to the sample hold circuit 6, and FIG. 2 (2) shows the hold signal. The sample-hold circuit 6 samples the peak voltage VP of the differential waveform, and the potential difference ΔV near the peak voltage VP changes greatly with a slight time difference Δt. If the timing of sampling by the sample signal fluctuates due to temperature or the like, the peak voltage VP is not sampled and a large error occurs in the held voltage. This makes it impossible to obtain an image symbol corresponding to the detection signal.

The output from the line 3 may include a noise component N caused by the switching operation of the analog switches S1 to Sn together with the detection signal component L of the photodiodes D1 to Dn, as shown in FIG. . When the waveform is sampled during the period W1 by the hold signal shown in FIG. 3 (2), the line 11 is set to 0 level as shown in FIG. 3 (3) and the noise component N
Therefore, the voltage Vn including the voltage is held. When the voltage Vn including the noise component N is input to the A / D converter 7, the S / N (signal / noise) ratio of the reading device is lowered.

There are variations in the input capacitances C12 to Cn2 and the conduction resistances R1 to Rn of the analog switches S1 to Sn realized by field effect transistors and the like. Even if the amount of light received by the photodiodes D1 to Dn is the same, the level of the output signal is different.

OBJECT The object of the present invention is to provide a reading device in which a reading error of a detection signal from a light receiving element does not occur.

Another object of the present invention is to provide a reading device that does not affect the output signal even if there is variation in the characteristics of the switch for scanning the detection signal by the light receiving element.

Yet another object of the present invention is to provide a reader having an improved S / N ratio.

Configuration of the Invention The present invention relates to (a) a plurality of light receiving detection units U1 to Un connected in parallel between the common line 3 and the ground line 2, and (b) each light receiving detection unit U1 to Un stores in parallel. The photodiodes D1 to Dn, which have the capacitors C11 to Cn1 and whose cathodes are connected to the common line 3, and the individual analog switches S1 to Sn, which have the input capacitors C12 to Cn2 in parallel and conduct in response to the scanning signal, are formed. (C) A DC power source E for applying a voltage to the photodiodes D1 to Dn in the reverse direction and a load resistor RL are connected in series, and are connected in parallel to the light receiving and detecting units U1 to Un. (D) a coupling capacitor for deriving a signal from the common line 3 on the positive side of the DC power source E to which the light receiving / detecting units U1 to Un are commonly connected. And Sa Cp, integrating circuit 9 integrates the output of (e) coupling capacitor Cp
And a gain setting resistor R11 connected in series to the coupling capacitor Cp, an operational amplifier 10 having one input connected to the gain setting resistor R11 and a ground line 2 connected to the other input, The low band gain limiting resistor R12 connected between the one input and the output of the amplifier 10, the integrating capacitor CI connected in parallel to the low band gain limiting resistor R12, and the low band gain limiting resistor R12 in parallel. An integrating circuit 9 having a reset analog switch SW that is connected and is turned on by a control signal, and (f) scanning signals are sequentially applied to the individual analog switches S1 to Sn to sequentially supply the individual analog switches S1 to S.
Scanning is performed while turning on one of the n and turning off all of the remaining, and during the conduction period of each of the individual analog switches S1 to Sn, a control signal is generated to generate a noise component N generated when the individual analog switches S1 to Sn are turned on. Period W longer than period W3
2 is generated and given to the reset analog switch SW, and the period W4 between the control signals is the same as that of the photodiode D1.
To Dn, and a control means 4 which is set to a time longer than necessary to integrate the signal component L corresponding to the amount of received light of Dn.

Embodiment FIG. 4 is a diagram showing the construction of an embodiment of the present invention. Fourth
The drawing is similar to that of FIG. 1, and the corresponding portions are designated by the same reference numerals. Light receiving and detecting unit U1 for optically reading an original or the like in a facsimile transmitter or the like
~ Un are provided. The line 3 includes light receiving detection units U1 to U scanned by the control signal from the control circuit 4.
The signal from n is derived. Analog switch S1-S
When n is open, the storage capacitors C1-Cn have already been charged by the bias power supply E.

For example, when the photodiode D1 receives light, the photodiode D1 becomes conductive, which causes the storage capacitor C
The electric charge of 1 is discharged. This causes a photocurrent i (t), which is a function of time t, to flow in the photodiode D1. The functions of the photocurrent i (t) are the equivalent resistance R (not shown) of the photodiode D1 at the time of reverse bias, the storage capacitance C11 of the photodiode D1 and the input capacitance C12 of the analog switch S1. This photocurrent i (t) is expressed by the following first equation.

In the first expression, V is the voltage of the bias current E.

The output current I (t) is generated in the line 3 by the generation of the photocurrent i (t). The functions of the output current I (t) are the load resistance RL and the stray capacitance C of the common power 1.
S, a storage capacitance C11 of the photodiode D1, an input capacitance C12 of the analog switch S1, and a conduction resistance R1 of the analog switch S1. The relationship between the output resistance I (t) and the photocurrent i (t) is expressed by the following second equation based on the law of conservation of charge.

I (t) dt = i (t) dt (2) As shown in the second equation, the output current I (t) equal to the photocurrent i (t) is output to the line 3 to output its output. The output voltage V1 represented by the product of the current I (t) and the load resistance RL is amplified by the amplifier 5 via the coupling capacitor CP and output to the integrating circuit 9. At this time, the integrated value of the output voltage V1 is expressed by the following third equation.

∫ ^∞ ₀ ▼ V1 (t) dt = RL ∫ ^∞ ₀ ▼ I (t) dt (3) The output voltage V2 value from the integrating circuit 9 is the integrated value of the input voltage V1. From FIG. 3, the output voltage V2 is the load resistance RL and the storage capacitance C1 of the diode D1.
2. It is a function of the input capacitance C12 of the analog switch S1, and the conduction resistance R1 of the analog switch S1 can be ignored. The output voltage V2 is influenced by the input capacitance C12 of the analog switch S1. However, the input capacitance C12 of the analog switch S1 is, for example, the photodiode D1.
Is 1/10 of the storage capacitance C1, and the input capacitance C12 is equal to the photodiode D1 as shown in the first equation.
Since the output voltage V2 is affected by the sum of the storage capacitance C1 and the storage capacitance C1, the provision of only ± 3% is provided even if the variation of the input capacitance C12 of the analog switch is ± 30%. As a result, the output voltage V2 of the integrating circuit 9 is not affected by variations in the characteristics of the analog switch S1. At this time, when the stray capacitance CS becomes large for some reason, if the load resistance RL is made small in order not to decrease the reading speed, the output voltage V2 from the integrating circuit 9 decreases, so that the common electrode 1 is divided. As a result, the stray capacitance C12 can be reduced.

The integrating circuit 9 includes an operational amplifier 10, as shown in FIG.
It is composed of resistors R11 and R12, a capacitor CI, and a switch SW. Operational amplifier 1 to which the signal from the amplifier 5 is input
A gain setting resistor R11 is connected to the inverting terminal of 0, and the non-inverting terminal of the operational amplifier 10 is grounded. In parallel with the operational amplifier 10, a low band gain limiting resistor R12, an integrating capacitor CI and a reset analog switch SW are connected. The reset analog switch SW is the control circuit 4
Is activated by a reset control signal P from

FIG. 5 (1) shows the waveform of the input voltage V1 of the integrating circuit 9, FIG. 5 (2) shows the waveform of the control signal P for controlling the analog switch SW, and FIG. 5 (3). Shows the output waveform of the output voltage V2 of the integrating circuit 9. The waveform of the input voltage V1 is a waveform in which a noise component N generated when the analog switch S1 is turned on and a signal component L corresponding to the amount of light received by the photodiode D1 are added. This noise component N
When the voltage of is input, the control signal P is input as shown in FIG.
Conduction for 2 resets the integrated input voltage. The signal component L is input subsequently to the noise component N, but before the signal component L is input,
By cutting off the analog switch SW, the signal component L is integrated, and the waveform of the output voltage V2 as shown in FIG. 5 (3) is output. Since the voltage of the integrated signal component L is held until the analog switch SW is turned on, the held voltage is input to the A / D converter 7.
The input voltage is level discriminated from the A / D converter reference voltage 12 and converted into a digital value corresponding to the reference voltage 1. In this way, it is possible to obtain an image signal faithful to the signal component L corresponding to the amount of light received by the photodiodes D1 to Dn.

To further describe the configuration, a plurality of n light receiving detection units U1 to Un are connected in parallel between the common line 3 and the ground line 2. The photodiodes D1 to Dn have parallel storage capacitors C11 to Cn1, and the cathode side is connected to the common line 3. Individual analog switches S1 to Sn
Has a parallel input capacitance C12 to Cn2, and the control circuit 4
Are sequentially turned on one by one in response to the signal from the other terminals, while the remaining individual analog switches are turned off. The DC power source E applies a voltage to the photodiodes D1 to Dn in the reverse direction. The coupling capacitor Cp derives the signal from the common line 3.

In the integrating circuit 9, the time setting resistor R11 is connected in series with the coupling capacitor Cp and is connected to one input of the operational amplifier 10. The other input of the operational amplifier 10 is grounded, that is, connected to the ground line 2. The low-frequency gain limiting resistor R12 is connected between the one input and the output of the operational amplifier 10, and an integrating capacitor CI and a reset analog switch SW conducted by a control signal are connected in parallel with the resistor R12. Connected in parallel. The control circuit 4 conducts one of the individual analog switches S1 to Sn as described above and scans while cutting off all the remaining analog switches S1 to Sn.
During the conduction period of n, a control signal is given to the reset analog switch SW, and the period W2 of this control signal is set longer than the generation period W3 of the noise component N as shown in FIG. Period W between control signals
4 is set to be equal to or longer than the time required to integrate the signal component L.

The light reception detection units U1 to Un according to the above-described embodiments may have other configurations.

Effect As described above, according to the present invention, by arranging the integrating circuit instead of the sample-hold circuit, a reading error that occurs when using the sample-hold circuit does not occur in principle when using the integrating circuit. , An output value faithful to the signal waveform from the light receiving element can be obtained. As another effect, even if there is a variation in the characteristics of the analog switch for scanning the detection signal, the use of the integrating circuit can prevent the influence of the variation in the characteristics of the analog switch on the output signal. it can.

Further, the noise component can be removed by using the analog switch for resetting the signal input to the integrating circuit, and the S / N ratio can be improved.

As another effect, it is not necessary to consider the deviation of the control signal given to the sample and hold circuit, and when using the integrator circuit, it is possible to perform low-cost calculation as compared to the case of selecting a high-priced sample and hold circuit that operates at high speed. Since it can be easily realized by an amplifier, the manufacturing cost can be reduced.

Furthermore, according to the present invention, the signal component L corresponding to the amount of light received by the photodiodes D1 to Dn is generated by the coupling capacitor Cp.
Since each of the received light detection units U1 to U1
The signal component L does not change depending on the DC voltage applied to the Un, and the amount of received light is reliably and accurately detected.

Further, in order to remove the noise component N generated when the individual analog switches S1 to Sn are turned on, the control signal is generated and given to the reset analog switch SW.
An excellent effect that the noise component N can be removed with a relatively simple structure is also achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of the prior art, FIG. 2 is a waveform diagram for explaining the operation of the prior art shown in FIG. 1, and FIG. 3 is an operation of the prior art shown in FIG. FIG. 4 is a waveform diagram for explaining FIG. 4, FIG. 4 is a diagram showing a configuration of an embodiment of the present invention, and FIG.
The drawing is a waveform diagram for explaining the operation of the embodiment of the present invention shown in FIG. 4 ... control circuit, 5 ... amplifier, 7 ... A / D converter,
9 ... Integrator circuit, U1-Un ... Received light detection unit, D
1 to Dn ... photodiode, C11 to Cn1 ... storage capacitor, S1 to Sn ... analog switch, C12
~ Cn2 ... input capacitor, R1 to Rn ... conduction resistance, RL ... load resistance, E ... bias power supply

Claims (1)

[Claims] 1. (a) A plurality of light receiving and detecting units U1 to Un
Are connected in parallel between the common line 3 and the ground line 2, and (b) each of the photodetection units U1 to Un has parallel storage capacitors C11 to Cn1, and the photodiode connected to the common line 3 on the cathode side. D1 to Dn and parallel input capacitors C12 to Cn2, and individual analog switches S1 to Sn that are conductive in response to a scanning signal are connected in series and are configured in the following manner: (c) Reverse direction to the photodiodes D1 to Dn A direct-current power supply E for applying a voltage to a load resistance RL, and a series circuit connected in parallel to the light receiving and detecting units U1 to Un; and (d) the light receiving and detecting units U1 to Un and the series. A coupling capacitor Cp for deriving a signal from the common line 3 on the positive side of the DC power source E, which is commonly connected to a circuit, and (e) an integrating circuit for integrating the output of the coupling capacitor Cp. 9
And a gain setting resistor R11 connected in series to the coupling capacitor Cp, an operational amplifier 10 having one input connected to the gain setting resistor R11 and a ground line 2 connected to the other input, The low band gain limiting resistor R12 connected between the one input and the output of the amplifier 10, the integrating capacitor CI connected in parallel to the low band gain limiting resistor R12, and the low band gain limiting resistor R12 in parallel. An integrating circuit 9 having a reset analog switch SW that is connected and is turned on by a control signal, and (f) scanning signals are sequentially applied to the individual analog switches S1 to Sn to sequentially supply the individual analog switches S1 to S.
Scanning is performed while turning on one of the n and turning off all of the remaining, and during the conduction period of each of the individual analog switches S1 to Sn, a control signal is generated to generate a noise component N generated when the individual analog switches S1 to Sn are turned on. Period W longer than period W3
2 is generated and given to the reset analog switch SW, and the period W4 between the control signals is the same as that of the photodiode D1.
To Dn, and a control means 4 which is set to a time longer than necessary to integrate the signal component L corresponding to the amount of received light of Dn.