JPH067681B2 - Color signal processing circuit - Google Patents

Description

The present invention relates to a digital television device that performs signal processing after digitizing a video signal, and more particularly to a color signal processing circuit thereof.

(Prior Art) With remarkable progress in digital IC technology, it has become possible to digitally perform baseband signal processing in a television receiver, which was conventionally performed in analog. The advantage of digitizing the signal processing circuit is that in terms of performance, it is possible to perform high-precision, distortion-free processing peculiar to digital, and also to improve temperature change, time change, and noise performance, In terms of functionality, it can be combined with a memory or computer to provide multi-screen televisions, scanning speed conversion,
It is possible to facilitate still images, special effect processing, and the like, and also to facilitate connection with various new media signals that are digital signals.

FIG. 4 shows a general structure of the digital video processing unit.
The analog video signal AV is supplied to the analog-digital converter 1
Sampling and digitization are performed by 02 and converted into a digital video signal DV. Sampling is performed at the timing of the sampling pulse ΦS output from the voltage controlled crystal oscillator (hereinafter referred to as VCXO) 103. The frequency of the sampling pulse ΦS is four times the color subcarrier frequency fsc, and the phase is synchronized with the demodulation axis of the color signal.

The following description takes I and Q demodulation as an example. Therefore, the sample phase becomes a multiple of ± I and ± Q. The control of the sample phase is performed by the phase locked loop (PLL) circuit 106. The PLL circuit 106 calculates the sample phase in the color burst section of the input digital video signal DV and outputs the phase error signal S1 corresponding to the difference between this and the I and Q phases. The phase error signal S1 is VCX
The oscillation frequency of O103 is controlled, whereby closed loop control is performed so that the phase of the sample pulse ΦS is synchronized with the I and Q phases. The sample pulse ΦS is supplied to each circuit as a reference clock in digital processing.

The digital video signal DV is separated into a luminance signal Y1 and a color signal C by a luminance / chromaticity separation circuit (hereinafter referred to as Y / C separation circuit) 108. The brightness signal Y1 is newly output as the brightness signal Y2 after the contour, contrast, and brightness are adjusted in the brightness processing circuit 112.
The color signal C is supplied to the color signal processing circuit 113 for automatic saturation control (ACC), color saturation adjustment, hue adjustment, color demodulation,
Matrix operation processing is performed, and three color difference signals (R-
Y), (G-Y), and (B-Y) signals are converted and output. The timing signal S necessary for the processing here is
2 is input from the PLL circuit 106. Color difference signal (R
-Y), (G-Y), and (B-Y) are adders 121, 1
22 and 123, the luminance signal Y2 is added and the color signals R, G, and B are output. These signals, after being digital-analog converted, drive the color cathode ray tube through the output circuit. Also, the control 124
An image quality adjustment signal 125 controlled by the viewer and a signal 126 sent from the digital processing unit to the controller 124, which is necessary for various automatic controls, are input. The controller 124 processes the input signals 125 and 126 based on a predetermined program and outputs them as signal processing parameters 127 to each circuit of the digital processing unit.

The above is the outline of the entire digital processing unit. Next, the color signal processing circuit 113 will be described.

FIG. 5 shows a conventional color signal processing circuit 113.
The color signal C from the Y / C separation circuit 108 is supplied to the multiplier 201.
Is multiplied by the ACC signal A2. The output signal C1 of the multiplier 201 is input to the ACC circuit 203. here,
The amplitude of the color burst is detected, and the magnitude of the ACC signal A2 is controlled so that it approaches a predetermined target value. As a result, the amplitude change of the color signal C due to the characteristics of the transmission path from the transmission station to the receiver is corrected.

A burst flag pulse (BFP) indicating the position of the color burst is input to the ACC circuit 203 to set the timing of the ACC operation. The output of the multiplier 201 is input to the data latch circuits 205 and 206. The data latch circuit 205 extracts I phase data from the input signal C1 and demodulates the I signal (ID). The timing of data extraction is given by the pulse ΦI. Similarly, in the data latch circuit 206, Q is generated by pulse ΦQ.
Phase data is extracted and the Q signal (DQ) is demodulated. The pulses ΦI and ΦQ are generated by the timing circuit 207 based on the color demodulation pulse ΦC. The color demodulation pulse ΦC is
PLL circuit 10 with burst flag pulse BPF
6 is a pulse which is always output and which gives a constant phase timing (for example, Q phase).

The demodulated I signal (ID) and Q signal (QD) are input to the color adjustment circuit 17. Here, the controller 124
From the sine signal (A1 sin θ) and the cosine signal (A1 cos θ) input from the color saturation degree adjustment and hue adjustment are performed. Signal (A1 sin θ), (A1 cos θ)
Is calculated by the controller 124 based on the color saturation signal A1 and the color signal θ controlled by the viewer and has values of (A1 sin θ) and (A1 cos θ), respectively. The color adjusting circuit 217 subjects the input I and Q signals to gain adjustment and coordinate rotation calculation as shown in the following equations to obtain output I'signal (I'D) and Q'signal (Q'D). .

That is, as compared with the input, the output has the color intensity A1 times, and the hue changes by θ. I'signal I '
The D and Q'signals Q'D are converted into color difference signals (RY), (GY), and (BY) by the matrix calculation shown in the following equations in the multipliers 221 to 226 and the adders 227 to 229. To be converted.

Matrix coefficient (RI, RQ, GI, GQ, BI, B
Q) is provided from the controller 124. This value is not always a theoretically constant value and must be changed according to the characteristics of the color cathode ray tube used.

(Problems to be Solved by the Invention) In the conventional color signal processing method described above, ACC processing,
At least 9 multipliers are required for color saturation / hue adjustment and matrix operation. As is well known, the circuit scale of the multiplier is very large. For example, in the case of (8 × 8) bits, it reaches about 1000 gates. this is,
It becomes a serious problem in making the system IC. In particular, matrix calculation requires a large number of circuits.
However, if this is digitized, the connection with the externally input digital RGB signals is facilitated, and many external parts required in the analog matrix circuit are reduced, which is a great advantage. Therefore, it has been strongly desired to reduce the circuit amount in the matrix circuit.

Therefore, an object of the present invention is to provide a color signal processing circuit capable of significantly reducing the number of high speed multipliers required for color signal processing (ACC, color saturation / hue adjustment, matrix operation).

[Structure of the Invention] (Means for Solving the Problems) The present invention creates a new ACC signal from a new color burst obtained by multiplying a color burst and an ACC signal during a color burst period of a digital color signal. ACC creating means, means for preparing the second matrix coefficient by multiplying the new ACC signal in the horizontal blanking period by the first matrix coefficient obtained from the system characteristics and user adjustment information. From the sum of the means for multiplying the digital color signal and the second matrix coefficient in the picture period to obtain a corrected digital color signal, and the corrected digital color signal and a signal obtained by delaying the digital color signal by one sample. And means for obtaining a color difference signal.

(Operation) By the above means, different kinds of operations are performed in time division. Then, the second matrix coefficient is prepared in the horizontal blanking period, and the color saturation signal or the hue signal and the ACC information are included in advance. Therefore, the corrected color signal can be directly demodulated and separated for each hue component, and the system configuration is simplified.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The color signal C from the Y / C separation circuit is input to the signal conversion circuit 401, and -Q
The phase data is converted into + Q, the -I phase data is converted into + I, and is converted into the color signal C10 in the data format of Q, I, Q, I, Q, I ... This is an operation for facilitating the subsequent processing.

The color signal C10 is the AC output from the ACC circuit 405.
It is input to the multiplexer 402 together with the C signal A0.
The output of the multiplexer 402 is input to the multiplier 403.

In the ACC circuit 405, the amplitude of the color burst is detected, and ACC is set so as to bring it close to a predetermined target value.
The magnitude of the signal A0 is controlled. Multiplexer 402
In (2), the selection processing of the ACC signal A0 and the color signal C10 is performed, and the output signal C11 is as shown in FIG. 2 (2b). In the period (T0), the ACC circuit 405
Is selected, and input color signals (burst and pattern color signals) are selectively derived in the periods (T1) and (T2).

The output signal C11 is input to the multiplier 403 and subjected to multiplication processing with the output signal K10 (matrix coefficient, ACC signal) from the multiplexer 427.

In the period (T0), the multiplication process of the ACC signal (A0) and the first matrix coefficient (RQ1 to BI1) is performed,
New matrix coefficients (RQ2-BI2) are created. In the next period (T1), the multiplication process of the ACC signal (A0) and the color burst is performed, the amplitude of the resulting color burst is detected by the ACC circuit 405, and a new ACC signal (A0) is created. It And the period (T
In 2), the new matrix coefficient (RQ2 to BI2) calculated previously is multiplied by the picture color signal, and the corrected color signal is output.

The output signal C12 of the multiplier 403 has been subjected to ACC control, color saturation adjustment, and hue adjustment. The delay circuit 430,
Matrix operation is performed by the adder 431, the registers 432 to 434, etc., and (RY), (GY), (BY)
Of the color difference signal and separated for each color difference signal.

Next, multiplexers 402, 427, 421-42
6, the registers 411 to 416 are shown in FIGS.
It will be described with reference to the drawings.

First, the controller 440 uses the matrices RQ1 to B
I1 can be output. These matrix coefficient coefficients RQ1 to BI1 are matrix coefficients RQ0, RI0, GQ corresponding to the pre-programmed cathode ray tube characteristics.
0, GI0, BQ0, BI0, and the color saturation signal A1 and the hue (θ) adjusted by the user.

The calculation process for that is as follows: Therefore, the matrix coefficients RQ1 to BI1 are
It will include hue adjustment information. Matrix coefficient RQ
1 to BI1 are respectively corresponding multiplexers 42
1 to 426, are derived in a time division manner during a necessary period (T0), and are input to the multiplier 403 via the multiplexer 427. This period (T0) is before the color burst period and is a horizontal blanking period (no signal period).

The processing in the period (T0) will be described. During this period (T0), the multiplexer 402 operates in the ACC circuit 4
The ACC signal (A0) from 05 is selected. As a result,
The multiplier 403 performs arithmetic processing on the ACC signal (A0) and the matrix coefficients RQ1 to BI1 to create new matrix coefficients RQ2 to BI2. The second matrix coefficients RQ2 to BI2 thus obtained are stored in the corresponding registers 411 to 416, respectively. As a result, new matrix coefficients RQ2 to BI2 are prepared.

Next, processing of the period (T1) will be described. During this period (T1), the multiplexer 402 selects the color signal C10. In addition, the multiplexer 427 is the ACC circuit 4
Select the ACC signal from 05. As a result, the multiplier 40
In 3, the ACC signal (A0) is multiplied by the color burst, and the multiplier 403 obtains the amplitude-controlled color burst. Here, the ACC circuit 405 is
It is determined whether the color burst has a predetermined amplitude, the value of the ACC signal (A0) is adjusted according to the deviation from the predetermined value, and the color burst is controlled to have a constant value.

Therefore, a new ACC signal (A0) is stored in this ACC circuit 405.

This ACC signal (A0) is used to create the second matrix coefficient in the next horizontal blanking period, as described in the processing of the period (T0). As a result, the second matrix coefficients RQ2 to BI2 also include information on the ACC signal (A0).

The processing of the period (T2) will be described.

During this period (T2), the previously prepared second matrix coefficients RQ2 to BI2 are stored in the registers 411 to 416.
Are output as signals K1 to K6 from the multiplexers 421 to 426, respectively.
It is supplied to the multiplier 403 via 27. On the other hand, the multiplexer 402 selects the input color signal C10 and selects the multiplier 4
03.

As a result, the color signal C12 whose color saturation, hue, and amplitude are controlled can be obtained from the multiplier 403.

FIG. 3 shows the color signal C11 input to the multiplier 403 described above.
And the second matrix coefficient RQ input as coefficient K10
2 to BI2 are shown. The result of this multiplication processing is supplied to the delay circuit 430 having a delay amount of one sample and the adder 431. The output of the delay circuit 430 is also supplied to the adder 431. Therefore, the adder 431
From (R-Y), (G-Y), as shown in FIG.
The (BY) color difference signal is demodulated and output every other sample. These color difference signals are latched and separated by the registers 432, 433, and 434 at the timings corresponding to the respective signals, and then output.

The color difference signal is calculated by the following formula.

Timing signal (tn) required for the above system operation
Is generated by the timing circuit 441 using the burst flag pulse (BFP) and the color demodulation pulse (ΦC) and is supplied to each unit.

In this embodiment described above, the information of the ACC signal is included in the second matrix coefficient by effectively utilizing the horizontal blanking period, and the second matrix coefficient is multiplied by the color signal of the picture period. The color signal corrected by can be obtained. That is, the periods in which the required arithmetic processing is required are properly classified, and the arithmetic processing is performed in a time division manner. Therefore, the system can be simplified and the number of multipliers to be used can be reduced.

Furthermore, since the above-mentioned time division processing has become possible, one multiplier is required to perform the necessary multiplication processing in each of the horizontal blanking period (T0), the gain adjustment period (T1), and the image period (T2). You can That is,
The calculation required for color signal processing can be realized with a minimum number of multipliers.

[Advantages of the Invention] As described above, according to the present invention, the color signal processing (ACC,
It is possible to significantly reduce the number of high-speed multipliers required for color saturation / hue adjustment, matrix operation).

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of towing and signals shown for explaining the operation of the circuit of FIG. 1, and FIG. 3 is also an operation of the circuit of FIG. 4 is a timing diagram for explaining the above, FIG. 4 is a diagram showing a digital video signal processing circuit, and FIG. 5 is a circuit diagram showing a conventional color signal processing circuit. 401 ... Signal conversion circuit, 402, 427, 421-42
6 ... Multiplexer, 403 ... Multiplier, 405 ... ACC
Circuits, 430 ... Delay circuits, 411-416, 432, 4
33, 434 ... Registers.

Claims (1)

[Claims] 1. An ACC creating means for creating a new ACC signal from a new color burst obtained by multiplying a color burst and a ACC signal in a color burst period of a digital color signal, and the new ACC signal in a horizontal blanking period. Means for preparing a second matrix coefficient by multiplying the ACC signal by the first matrix coefficient obtained from the system characteristics and user adjustment information; and the digital color signal and the second matrix coefficient during a picture period. A means for obtaining a corrected digital color signal by multiplying by a matrix coefficient; and means for obtaining a color difference signal from a sum of the corrected digital color signal and a signal delayed by one sample. Color signal processing circuit.