JPH0681040B2 - Logical operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention particularly relates to a logical operation suitable for generating a VLSI or the like by a logical operation circuit having a combination of AND / OR circuits connected in series in plural stages. Regarding the circuit.

[Background of the Invention]

For example, in the case of generating a logical operation circuit that executes the logical expression H H = ((A · B + C) · D + E) · F + G (1), conventionally, the above expression (1) is expanded and H = A · B ..D.F + C.D.F + E.F + G ... (2) was modified to form a logical operation circuit as shown in FIG. 1 based on this equation (2).

When the logical operation circuit of FIG. 1 is realized by a CMOS circuit, it becomes generally as shown in FIG. This CMOS circuit is P channel
MOSFET (PMOS-FET) 30 and N-channel MOSFET (NMOS-FE)
T) 40 is used as a basic NAND gate configuration, so the number of elements is 28, and the number of wires (the number of wires here means the number of input / output lines for each gate and the final output signal line of the logic circuit). Is the sum of the following.
Many books, for example, have the disadvantage that the area becomes large when laid out on VLISI.

[Object of the Invention]

An object of the present invention is to provide a logical operation circuit having a small number of elements and a small number of wirings for constructing a high speed logical operation circuit in VLSI or the like.

[Outline of Invention]

In the logic operation circuit according to the present invention, in order to reduce the number of elements and the number of wirings on VLSI, the logic which has been conventionally composed of a basic logic operation circuit (logical gate) such as NAND, NOR is formed by using a transistor as a basic circuit. It is composed of complex logic.

The structure considers the transistor as an open / close switch,
The first that is connected in parallel when the logic is OR and in series when it is AND
Switch group and a switching switch in the opposite state are used to connect in series the first switch group and the second switch group having a dual connection relationship, and a voltage is applied to both ends of the first switch group to draw it from the connection point. The output line outputs a logical "1" when a desired input condition is satisfied, and outputs a logical "0" when the desired input condition is not satisfied.

In addition, the maximum number of other switches connected between two types of switches connected to the same control signal line is minimized, and the number of switches connected to the output signal line is reduced. To do.

Among the inventions disclosed in the present application, typical configurations are as follows.

That is, between the first switch group (300) connected between the first operating potential point (500) and the output point (), and between the output point () and the second operating potential point (510). And a second switch group (400) connected to each other, wherein the first switch group (300) has first, second, third and fourth input signals (A, B, C, D). ) Respectively applied to the gates of the first, second, third and fourth P-channel MOSFETs.
(31, 32, 33, 34), and the second switch group (400) receives the first, second, third and fourth input signals (A, B, C, D). The first, second, third, and fourth N channels MO applied to the respective gates
SFETs (41, 42, 43, 44) are provided, and the source / drain path of the first P-channel MOSFET (31) in the first switch group (300) is the second
Source and drain paths of the P channel MOSFT (32) are connected in parallel, and the source and drain paths of the third P channel MOSFET (33) are connected in parallel.
Of the P-channel MOSFET (31, 32) connected in series with the source-drain path of the fourth P-channel MOSFET (34) connected in parallel with the first, second, and third. Source of P-channel MOSFET (31, 32, 33)
The source / drain path of the first N-channel MOSFT (41) in the second switch group (400) is connected in parallel with the drain path.
Source and drain paths of the N channel MOSFET (42) are connected in series, and source and drain paths of the third N channel MOSFET (43) are connected in series.
Of the N-channel MOSFET (42, 43) connected in parallel with the source-drain path of the fourth N-channel MOSFET (44), and the source-drain path of the fourth N-channel MOSFET (44) connected in series with the first, second, third. Source of N-channel MOSFET (41, 42, 43)
The source / drain paths of the first and second P-channel MOSFETs (31, 32) connected in series with the drain path and connected in parallel in the first switch group (300) are the third P-channel. Channel MOSFET (3
Output point () via the source / drain path of 3)
And the first, second, and third N-channel MOSFETs (41, 42, 41) connected in series and parallel in the second switch group (400).
The source / drain path of 43) is the fourth N-channel MO above.
It is characterized in that it is connected to the second operating potential point (510) through the source / drain path of the SFET (44).

According to the configuration of the present invention as described above, a plurality of P channel MOSs connected in parallel in the first switch group (300) are provided.
Since the connection order of the FETs and the plurality of N-channel MOSFETs connected in series and parallel in the second switch group (400) are equal, whichever input of a plurality of input signals (A, B, C, D) is input. The delay time of the output signal change at the output point () when the signal changes is averaged, and the maximum delay time is shortened.

Other objects and features of the present invention will be apparent from the following examples.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 3 (a) is a symbol diagram of the composite logic circuit 100 that executes the logic of the logical expression = (A * B + C) * D + E (3) from the input signals A, B, C, D, E. FIG. 3B is a circuit diagram realized by using a MOS-FET. The circuit of FIG. 3 (b) is a P-channel MOSFET (PMOS-FE).
T) 31 to 35 and N channel MOSFETs (NMOS-FET) 41 to 45.

From the formula (3), the negative logical formula F of the logical formula can be transformed into F = ((+) · +) ··· (4). The right side of Expression (3) and the right side of Expression (4) have a dual relationship (logical expression in which AND and OR are inverted).

In FIG. 3 (b), each MOS-FET constitutes a switch, and a switch group 400 constituted by NMOS-FETs 41 to 45.
Is a group of switches that are in a conductive state when = 1, that is, the right side of Expression (3) is satisfied, and thereby the ground potential 510 is transmitted to the output. Here, how to connect MOS-FET, series connection
AND and parallel connection are defined from the right side of Expression (3) in association with OR.

That is, NOMS-FETs 41 and 42 are A / B, 41, 42 and 43 are A / B +
C, 41, 42, 43 and 44 are (A ・ B + C) ・ D, 41, 42, 43, 4
4 and 45 are switch groups that are turned on when (A / B + C) / D + E are satisfied.

Similarly, a switch group 300 composed of PMOS-FETs 31 to 35
Is a switch group that is in a conductive state when F = 1, that is, the right side of Expression (4) is satisfied, and thereby transmits the power supply potential 500 to the output. The connection method of the MOS-FET at this time is also determined from the right side of the equation (4) in the same manner as the N-channel side.

That is, the PMOS-FETs 31 and 32 are +, 31 and 32 and 33 are (+
) ・ 31,32,33 and 34 are (＋) ・ ＋, 31,32,3
3,34 and 35 are switch groups that are turned on when ((+) ・ +) ・ holds.

As described above, the NMOS switch group 400 turns ON when = 1 and transmits the ground potential 510 to the output, and turns OFF when = 0.

Further, the PMOS switch group 300 turns on when = 0 and transmits the power supply voltage 500 to the output, and turns off when = 1.

Therefore, the logical expression can be realized by the connection logical sum of these outputs.

In FIG. 3B, the number of elements is 10 and the number of wirings is 6.

Therefore, by using a switch that conducts when a certain input signal is positive and a switch that conducts when a certain input signal is negative, two types of switches that conduct when a dual logical expression holds are AND and OR of the logical expressions, respectively. It is realized by expressing it as a parallel connection relationship with and realizes a logical operation circuit that outputs a logical "1" when a desired logic is satisfied by using these switch groups and outputs a logical "0" otherwise. be able to.

As a result of using the dual logic equation, either one of the two switches connected to the same signal is cut off, so NM
No through current flows between the OS switch group 400 and the PMOS switch group 300.

Further, in FIG. 3B, the NMOS-FET switch group 400 and the PMOS
-In connection of the FET switch group 300, for either one of the NMOS-FET switch group 400 or the PMOS-FET group 300,
It is possible to connect them upside down.

When the upper and lower sides of the NMOS-FET switch group 400 are turned upside down, the output signal line 550 is connected to the MOS-FETs 44, 45 and PM of the NMOS-FET switch group 400.
The MOS-FET 35 of the OS-FET switch group 300 is directly connected. When the POMS-FET switch group 300 is turned upside down, the MOS of the PMOS-FET switch group 300 is connected to the output signal line 550.
-FET 31, 32, 34 and NMOS-FET switch group 400 MOS-FET 41,
43 and 45 are directly connected. In the case of this method, the change of the output signal F accompanying the change of the input signals A, B, C, D, E becomes extremely slow with respect to a certain input signal.

For example, when the upper and lower sides of the NMOS-FET switch group 400 are connected in reverse, that is, when the configuration shown in FIG. 7 is used, another MOS connected between two MOS-FETs connected to the same input signal is connected.
-For the input signal A, the number of FETs is MOS-FET33,35,44,
There are 4 of 42. Similarly, for input signal B, MOS-F
Three of ET33,35,44, input signal C is MOS-FET35,4
4, the input signal D is one MOS-FET 35, and the input signal E is zero. Connect here in between
Focusing on the input signal A that maximizes the number of MOS-FETs,
When the input signals A, C, E are low level and the input signals B, D are high level, when the input signal A changes to high level now, the NMOS-FE
T41 is the load capacitance of output F, PMOS-FET31-35, NMOS-FE
Since the source and drain of T42 to 45 are at high level, the electric charge stored in the diffusion capacitance must be discharged. Quantitatively speaking, the load capacitance of the output F (≈C), the drain diffusion capacitance of the PMOS-FET 31 (≈C), the drain diffusion capacitance of the PMOS-FET 32 (≈C), the PMOS
-FET33 source and drain diffusion capacitance (≈2C), PMOS
-Drain diffusion capacitance of FET34 (≈C), source and drain diffusion capacitance of PMOS-FET35 (≈2C), drain diffusion capacitance of NMOS-FET41 (≈C), source and drain diffusion capacitance of NOMS-FET42 (≈) 2C), the drain diffusion capacitance (≈C) of the NMOS-FET43, the source and drain diffusion capacitance (≈2C) of the NMOS-FET44, and the drain diffusion capacitance (≈C) of the NMOS-FET45 are stored in the total diffusion capacitance of 15C. Must be discharged. Therefore, the output signal F cannot be changed at high speed. For other input signals, the amount of charge that has to be charged / discharged at that time is smaller than that in the above case regardless of any change in the input signal, and the maximum delay time is when the input signal A changes. Becomes

On the other hand, according to the configuration of FIG. 3B, similarly, another MO connected between two MOS-FETs connected to the same input signal is connected.
Regarding the number of S-FETs, for input signal A, MOS-FETs 33, 35
2 and the input signal B is 3 of MOS-FET 33, 35, 41
The input signal C is one of the MOS-FETs 35, the input signal D is three of the MOS-FETs 35, 41 and 42, and the input signal E is zero. Here, focusing on the input signal B that maximizes the number of MOS-FETs connected between them, the input signals A and D
Is high and the input signals B, C and E are low, the NMOS
-Because the source and drain of FET44 are at LOW level, no charge is stored in the diffusion capacitance. Therefore, when the input signal B changes from the LOW level to the High level, the amount of charge that must be discharged (here, the amount of charge that the NMOS-FET 42 discharges) is the load capacitance of the output F (≈C). , PMOS
-Drain diffusion capacitance of FET31 (≈C), drain diffusion capacitance of PMOS-FET32 (≈C), source and drain diffusion capacitance of PMOS-FET33 (≈2C), drain diffusion capacitance of PMOS-FET34 (≈C), PMOS -Source and drain diffusion capacity of FET35 (≈2C), source and drain diffusion capacity of NMOS-FET41 (≈2C), drain diffusion capacity of NMOS-FET42 (≈2C)
C), NMOS-FET43 drain diffusion capacitance (≈C) and NMO
Since the total drain diffusion capacitance (≉C) of the S-FET 45 is 13 C, this is smaller than in the case of the above configuration, and the output signal F can be changed at high speed.

That is, when the number of other switches connected between two switches connected to the same input signal is maximum, the condition that the charge / discharge capacity when the input signal is changed is minimized is satisfied. If designed, the maximum delay time will be short.

Here, referring to the case where only the PMOS-FET switch group 300 is connected upside down in the configuration of FIG. 3 (b), that is, the configuration of FIG. 8 is mentioned, the same input signal is connected. Another MO connected between two MOS-FETs
The number of S-FETs is 0 for input signal A, 1 for MOS-FET 41 for input signal B, and 1 for input signal C.
One of MOS-FET31, input signal D is MOS-FET41,4
2 for the input signal E, and two for the input signal E of the MOS-FETs 31 and 32. Therefore, paying attention to the input signal E that maximizes the number of MOS-FETs connected between them, when the input signals A, C, E are LOW level and the input signals B, D are High level, the input signal E is now H
When it changes to igh, the load capacitance of output F (≈C), PMOS-F
ET31 source and drain diffusion capacitance (≈2C), PMOS-FE
T32 source and drain diffusion capacitance (≈2C), PMOS-FET
33 source and drain diffusion capacitance (≈2C), PMOS-FET3
Source and drain diffusion capacity of 5 (≈ 2C), PMOS-FET35
Drain diffusion capacitance (≈C), NMOS-FET 41 drain diffusion capacitance (≈C), NMOS-FET 43 drain diffusion capacitance (≈C) and NMOS-FET 45 drain diffusion capacitance (≈C)
Therefore, the electric charge stored in the total diffusion capacity of 13C will be discharged. This is the same amount of charge as in the configuration of FIG. Therefore, there is no difference in the response speed of the output signal F. However, the internal load capacity of the output signal line 550 in FIG. 8 is M
Six of the OS-FETs 31, 32, 34, 41, 43, 45, which are considerably larger than the four internal load capacitance MOS-FETs 35, 41, 43, 45 in the configuration of FIG. 3 (b). I understand. A large internal load capacity means that the overall response speed is reduced. Therefore, it can be said that the condition is to design the logic circuit so that the internal load capacity is small.

In addition, in FIG. 3B, the PMOS-FET switch group 300 and
When the position of the NMOS-FET switch group 400 is turned upside down (that is, the MOS-FET3 of the PMOS-FET switch group 300 is connected to the output signal line 550).
1,32,34 and the MOS-FET44,45 of the NMOS-FET switch group 400 are connected), the response speed does not change to the output signal line 550, but it is connected to the output signal line 550 as above. MOS
-The number of FETs is four from MOS-FET35,41,43,45 to MOS-FET3
It can be seen that the internal load capacity of the output signal line 550 is increased and the overall response speed is reduced by increasing the number to 1, 32, 34, 44, 45.

As described above, in order to improve the response speed of the logic circuit, the input signal is changed when the number of other switches connected between two switches connected to the same input signal is maximum. In order to reduce the number of MOS-FETs connected to the output signal line 550 under the condition that the charge / discharge capacity is minimized, the PMOS-FET switch group 300 and the NMOS-FET are
It suffices to satisfy the condition of configuring the switch group 400.

Therefore, according to the present embodiment, by determining the logic circuit that realizes the logical expression under the above two conditions, the one having the best logic scale and circuit performance can be obtained.

FIG. 4 (a), a symbol diagram of the logical operation circuit 200 for generating = ((A + B + C) * D + E) * F + G (5) from the input signals A, B, C, D, E, F, G Further, FIG. 4 (b) is a circuit diagram realized by using a MOS-FET.

This circuit diagram is an extension of the circuit configuration shown in FIG. 3 (b) for each switch group (PMOS-FET switch group 300, NMOS-FET switch group 400). The connection of the switch group is determined.

This circuit is used in FIG. 6 described later.

In the circuit diagram of FIG. 4 (b), the number of elements is 14 and the number of wirings is 8, which is about half the circuit scale of the conventional example of FIG.

Conventionally, since a logical operation circuit is generated by expanding a logical expression (for example, expanding to an additive standard type), one input signal is input to a large number of logical gates (first stage), and its logical Although a logic gate (second stage) that generates a desired logic from the output of the gate (first stage) is required, in the circuit configured by the composite logic according to the present embodiment, one input signal has two logic gates. It is only input to the (first stage), and the logic gate of the second stage is unnecessary, and the number of elements and wirings in the entire circuit is reduced.

FIG. 5 is a logic diagram of a carry look-ahead circuit of a conventional 4-bit arithmetic unit based on a NAND gate.

In FIG. 5, pi, gi, ci (i = 0, 1, 2, 3) are the carry propagation signal, carry generation signal and carry signal at the i-th bit, respectively. Here, the third bit is MSE (Most Significant
ant Bit). Assuming that the input data of the i-th bit is xi, yi (for example, xi, yi take values of "1100" and "1010"), pi = xiyi gi = xi.yi. Here, is a symbol representing an exclusive sum. Therefore, ci is c ₀ = g ₀ + p ₀ · c _-1 c ₁ = g ₁ + p ₁ · g ₀ + p ₁ · p ₀ · c _-1 c ₂ = (assuming the carrier input is c _-1 ). g ₂ + p ₂ · g ₁ + p ₂ · p ₁ · g ₀ · + p ₂ · p ₁ · p ₀ · c _-1 . If P and G are P = p ₃ · p ₂ · p ₁ · p ₀ G = g ₃ + p ₃ · g ₂ + p ₃ · p ₂ + g ₁ + p ₃ · p ₂ · p ₁ · g ₀ , c ₃ is c ₃ = G + P · c ₋₁ .

If this is realized by the CMOS circuit as shown in FIG. 2, the number of elements will be 92 and the number of wiring will be 27, and the area will be large when integrated into an LSI.

However, the above logical formula is c ₀ = p ₀ · c ₋₁ + g ₀ c ₁ = (p ₀ · c ₋₁ + g ₀ ) · p ₁ + g ₁ c ₂ = ((p ₀ · c ₋₁ + g ₀ ) ・ P ₁ + g ₁ ) ・ p ₂ ＋ g ₂ P ＝ p ₃・ p ₂・ p ₁・ p ₀ G = ((p ₁・ g ₀ ＋ g ₁ ) ・ p ₂ ＋ g ₂ ) ・ p ₃ ＋ g ₃ The carry look-ahead circuit realized by using the CMOS logic circuits shown in FIGS. 3 and 4 is as shown in the symbol diagram of FIG.

According to the carry look-ahead circuit shown in FIG. 6, the number of elements is 52,
The number of wires is 14, which is about half the circuit scale of the conventional circuit shown in FIG. 5, and has the effect of reducing the area when laid out on an LSI. In particular, the effect is great in a logical operation circuit such as the carry look-ahead circuit shown in FIG. 6, which has an inherently deep number of logical stages and in which AND circuits and OR circuits are alternately arranged.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, since the logic in which the basic logics are combined is configured by one composite logic circuit, the number of elements and the number of wirings are reduced, and there is an effect that the area can be reduced in the VLSI. is there.

Also, the maximum number of other switches connected between the two types of switches connected to the same control signal is the smallest,
Moreover, since the number of switches connected to the output signal line is reduced, the maximum delay time can be shortened.

[Brief description of drawings]

FIG. 1 is a symbol diagram showing an example of a conventional logic configuration, FIG. 2 is a circuit diagram showing an example of a conventional circuit configuration, FIG. 3 is a symbol diagram of a composite logic circuit, and FIG. 4 is a composite logic circuit. Circuit diagram, FIG. 5 is a symbol diagram of a conventional carry look-ahead circuit, FIG.
FIG. 7 is a symbol diagram of a carry look-ahead circuit using a composite logic circuit according to the present invention, FIG. 7 is a first reference diagram for explaining the effect of the present invention, and FIG. 8 is for explaining the effect of the present invention. It is a 2nd reference drawing. 30 ... P-channel MOSFET (PMOS-FET), 40 ... N-channel MOSFET (NMOS-FET), 100,200 ... Complex logic circuit,
50 …… Conventional composite circuit, 60 …… NAND circuit, 300 …… PMOS
-Switch group composed of FETs, 400 ... Switch group composed of NMOS-FETs, 500 ... power supply voltage, 510 ... ground potential.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takaki Noguchi 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Tamotsu Takahashi 1479 Kamimizuhonmachi, Kodaira-shi, Hitachi Hitachi My Clos Computer Engineering Stock Association In-house (56) Reference JP 56-124256 (JP, A) JP 58-199554 (JP, A) JP 55-16593 (JP, A)

Claims (2)

[Claims] 1. A first switch group connected between a first operating potential point and an output point, and a second switch group connected between the output point and a second operating potential point. And the first switch group includes first, second, third, and third gates to which the first, second, third, and fourth input signals are applied, respectively.
A second P-channel MOSFET, and the second switch group has first, second, third, and fourth gate signals to which the first, second, third, and fourth input signals are applied, respectively. A fourth N-channel MOSFET is provided, and the first P-channel MO in the first switch group is included.
The source / drain path of the SFET is the second P channel MO above.
Connected in parallel with the source / drain path of the SFET,
The source / drain paths of the P channel MOSFETs are connected in series with the source / drain paths of the first and second P channel MOSFETs connected in parallel, and the fourth P channel is connected.
The source / drain path of the MOSFET is connected in parallel with the source / drain path of the first, second, and third P-channel MOSFETs connected in parallel in series, and the first N-channel MO in the second switch group is connected.
The source / drain path of the SFET is the second N channel MO above.
Connected in series with the source / drain path of the SFET,
The source / drain path of the N-channel MOSFET is connected in parallel to the source / drain path of the first and second N-channel MOSFETs connected in series, and the fourth N-channel is connected.
The source / drain path of the MOSFET is connected in series with the source / drain path of the first, second, and third N-channel MOSFETs connected in series and parallel, and the parallel connection is made in the first switch group. The source / drain paths of the first and second P-channel MOSFETs are connected to the output point via the source / drain path of the third P-channel MOSFET, and are connected in series / parallel in the second switch group. The logic is characterized in that the source / drain paths of the first, second and third N-channel MOSFETs are connected to the second operating potential point via the source / drain paths of the fourth N-channel MOSFET. Arithmetic circuit. 2. The logical operation circuit according to claim 1, wherein the logical operation circuit constitutes a carry look-ahead circuit.