JPH0682327B2 - Processor scan control method - Google Patents

Description

The present invention relates to a processor scan control system, and more particularly to a scan control system suitable for maintenance of a plurality of processors and a bus arbiter connected to a common bus.

[Conventional technology]

Conventionally, for a system with multiple processors,
When performing maintenance or diagnosis of each processor by the maintenance processor, for example, as described in JP-A-62-44858, a dedicated interface is provided from the maintenance processor to each processor, and scan-in / scan of target registers is performed. The output is generally performed for each processor via the dedicated interface.

[Problems to be Solved by the Invention]

The above-mentioned conventional technique has an advantage that each processor can be easily controlled from the maintenance processor, but when each processor is realized by only one LSI and the logical configuration and the number of interface signal lines are limited, it becomes a pin neck, and There is a problem that it is difficult to perform centralized control.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor scan control system in which when a maintenance processor performs maintenance of a plurality of processors, the dedicated interface from the maintenance processor can be minimized and control can be easily realized. .

[Means for Solving the Problems]

In order to achieve the above-mentioned object, the present invention provides a system in which a plurality of processors and a bus arbiter are connected to a common bus, and the processors which have a bus use right by the bus arbiter perform data transfer or the like using the common bus. A maintenance processor is connected to one of the processors with a dedicated interface, and the processor connected to the maintenance processor performs scan-in / scan-out control of the processor group and the bus arbiter using the common bus according to an instruction from the maintenance processor. That's what I did.

Specifically, when there is a scan instruction from the maintenance processor, the processor connected to the maintenance processor through a dedicated interface sends a scan request to the bus arbiter, and when the bus arbiter receives the scan request, the common When the bus is released, the acceptance of the common bus use request from the processor group is prohibited and the scan permission is sent to all the processors. When all the processors receive the scan permission, the common bus is switched to the scan control. When the processor recognizes that the scan request has been issued, the scan operation is performed by the scan instruction sent from the processor connected to the maintenance processor via the common bus, and after the scan ends, the processor drops the scan request, and the bus arbiter causes the bus arbiter to The scan permission is dropped and the common bus from the processor group needs to be used. Characterized in that it starts receiving again.

It should be noted that any one of the processor groups may serve as the bus arbiter.

[Action]

The processors other than the processors connected to the maintenance processor do not need a dedicated interface with the maintenance processor because the scan instructions from the maintenance processor are realized using the common bus. Therefore, an increase in the number of interface signals and an increase in dedicated interface control logic with the maintenance processor can be suppressed.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, the bus arbiter 2 and the processors 3, 4, 5 are commonly connected to a data bus 700, a start control bus 800, and an end control bus 900. The bus arbiter 2 may be one of the processors 3, 4, and 5. The maintenance processor 1 is connected to the processor 3 via a dedicated interface 101. Each processor 3,4,5 has a bus control unit 31,41,51, a data transfer unit 32,42,52, a data bus output selection circuit 33,43,53, a scan control unit 34,44,54, a scan-out data selection circuit
35, 45, 55, the processor 3 further includes a maintenance processor interface control unit 37 and a start control output selection circuit 3
8. Includes an end control output selection circuit 39. The clock 61 of the clock generator 6 is received by the bus arbiter 2 and the clock control units 26, 36, 46, 56 of the processors 3, 4, 5.

FIG. 2 shows, as an example, a time chart of data transfer from the processor 4 to the processor 5 in FIG.

The processor 4 sends an access request 411 from the bus controller 41 to the bus arbiter 2 for data transfer. The bus arbiter 2 returns an access permission 412 to the processor 4 when the common bus is not used. As a result, the processor 4 becomes the bus control unit.
41 sends data write instruction information to the processor 5 to the start control bus 800, and the write data is sent from the data transfer unit 42 via the data bus output selection circuit 43 to the data bus 70.
Send to 0. The bus arbiter 2 receives the information of the start control bus 800 from the processor 4 similarly to the processor 5, grasps the number of data transfer cycles of the processor 4, and receives an access request from another processor as soon as the data transfer is completed. The processor 5 transfers the data on the data bus 700 to the data transfer unit 52 according to the information on the start control bus 800.
Receive at. When the data reception is normally completed, the processor 5 sends an access request 511 from the bus control unit 51 to the bus arbiter 2, and when an access permission 512 is received from the bus arbiter 2, the bus control unit 51 sends the end control bus 900 to the processor 4. The information indicating the normal end of data writing is sent.
Also in this case, the bus arbiter 2 receives the information of the end control bus 900 like the processor 4, and when it is found that the bus can be released immediately, the bus arbiter 2 accepts the access request from another processor.

In this series of operations, the clock 61 generated from the clock generator 6 is supplied to the bus arbiter 2, each processor 3, 4,
From the maintenance processor interface control unit 37 in the processor 3 which is received by the clock control units 26, 36, 46, 56 in 5 and is connected to the maintenance processor 1 by the dedicated interface (hereinafter referred to as maintenance processor interface) 101. It is enabled when the clock activation signal 371 is being sent.

FIGS. 3 to 5 are time charts in which the data bus 700 used for the data transfer control described in FIG. 2, the start control bus 800, and the end control bus 900 are shared and the processor 5 is scan-controlled as an example. is there. FIG. 6 shows a scan target register of the processor 5 and a scan control unit 5.
4 is a detailed configuration diagram of a scan-out data selection circuit 55. FIG.

Maintenance processor 1 to maintenance processor interface 10
When there is a scan instruction of the maintenance processor 5 to the processor 3 via 1 (scan data is also sent if scan-in), the maintenance processor interface controller 37
Sends a scan request 372 to the bus arbiter 2. When the common buses 700, 800, 900 are open, the bus arbiter 2 sends a scan permission 373 to all the processors and further suppresses access request acceptance from all the processors. By this scan permission 373, the bus arbiter 2 and all the processors 3, 4, 5 recognize that the common buses 700, 800, 900 have been switched for scan control.

The scan control unit 34 of the processor 3 allows the scan permission 373.
Causes the start control output selection circuit 38 and the end control output selection circuit 39 to select the scan control signal 374 from the maintenance processor interface control section 37 by the selection signal 342. After that, the maintenance processor interface control unit 37 drops the clock activation signal 371 to suppress the clock supply to the bus arbiter 2 other than itself, the processors 3, 4, and 5, and the start control selection circuit 38 and the end control output selection circuit. The scan control signal 374 is sent to the start control bus 800 and the end control bus 900 via 39. That is, in the case of scan-in, as the scan signal to the processor 5, if the signal is scan-in, the selection signal of the processor 5, the scan-in instruction signal, and the scan trigger signal are sent to the start control bus 800. In the case of scan-out, as shown in FIG. 5, the selection signal of the processor 5 and the scan-out instruction signal are transmitted, but the scan trigger signal is not transmitted. The end control bus 900 has a processor 5
The scan target register address in is sent out.

The bus arbiter 2 and each of the processors 3, 4 and 5 receive the scan control information on the start control bus 800 and the end control bus 900 in the scan control units 34, 44 and 54 (there are similar ones to the bus arbiter 2). , Decipher whether it is a scan to its own processor.

If it is scan-in to the processor 5,
The scan control unit 34 of the processor 3 sends the scan-in data 375 from the maintenance processor interface control unit 37 to the data bus 700 via the data bus output selection circuit 33 in response to the selection signal 341 because of scan-in.

On the other hand, in the processor 5, in the scan control unit 54,
As shown in FIG. 6, the AND signal of the scan enable signal and the selection signal of the processor 5 is logically ANDed by the AND gate 54-a, the scan target address is further decoded by the decoder 54-b, and the logical AND is performed by the AND gate 54-c. By doing so, it is recognized that the scan is to the target register 58-a. The output of the AND gate 54-c selects the scan-in data on the data bus 700 in the input data selection circuit 58-b of the target register 58-a. Furthermore, by sending the output of the AND gate 54-c, the scan-in signal, and the logical product output of the scan trigger from the AND gate 54-d to the clock terminal of the target register 58-a via the OR gate 58-c, the scan-in signal is output. Set the data in the target register 58-a. The input CKi of the AND gate 54-d is the clock from the clock controller 56 in the processor 5 in FIG.
No clock is being sent because the clock activation signal 371 has fallen.

Next, in the case of scan out, in the scan controller 54, the processor 5 causes the AND gate 5 to operate as shown in FIG.
4-a output and scan out on start control bus 800
The AND gate 54-e calculates the logical product and sends it as the scan-out data selection instruction 541 to the data bus output selection circuit 53 in FIG. The output of the target register 58-a is the AND gate 54-c in the scan-out data selection circuit 55.
Is ANDed with the output of AND gate 55-a, and OR gate 55-a
It is selected by the data bus output selection circuit 53 via b and sent to the data bus 700. The scanout data on the data bus 700 is taken in by the maintenance processor interface 37 of the processor 3.

When the scan operation is completed, the maintenance processor interface controller 37 of the processor 3 sends the clock activation signal 371 as shown in FIG. 2 and further drops the scan request 372. As a result, the bus arbiter 2 drops the scan permission 373 and starts accepting an access request from each processor again. The maintenance processor interface control unit 7 which has dropped the scan request 372 reports the end of scanning to the maintenance processor 1 via the maintenance processor interface 101. If scan out, maintenance processor 1
The scan-out data is also read from the maintenance processor interface control unit 37.

Although the scan control to the processor 5 is described in the above description, the other processors 3 and 4 and the bus arbiter 2 can be realized in the same manner.

〔The invention's effect〕

As described above, according to the present invention, when performing maintenance or the like of a plurality of processors by the maintenance processor, when the plurality of processors are connected to a common bus, one of the processors is provided with an interface with the maintenance processor. It only needs to be connected, and it can be realized without newly providing an interface for scan control in another processor.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
3 is a time chart of data transfer from the processor 4 to the processor 5, FIG. 3 is a time chart when the common bus of FIG. 1 is switched to scan control, and FIG. 4 is a content of the start control bus at scan-in. Figure showing, fifth
FIG. 6 is a diagram showing the contents of the start control bus at the time of scan-out, and FIG. 6 is a diagram showing a scan target register and peripheral logic configuration example of the processor 5 in FIG. 1 ... Maintenance processor, 2 ... Bus arbiter, 3,4,5 ...
… Processor, 31,41,51 …… Bus controller, 32,42,52 ……
Data transfer unit, 33,43,53 ... Data bus output selection circuit,
34,44,54 …… Scan control unit, 35,45,55 …… Scan out data selection circuit, 26,36,46,56 …… Clock control unit, 37 …… Maintenance processor interface control unit, 38…
… Start control output selection circuit, 39 …… End control output selection circuit, 6 …… Clock generator, 101 …… Maintenance processor interface, 700 …… Data bus, 800 ……
Start control bus, 900 ... End control bus.

Claims (3)

[Claims] 1. A system in which a plurality of processors and a bus arbiter are connected to a common bus, and processors which receive a bus use right by the bus arbiter perform data transfer or the like using the common bus, are maintained in one of the plurality of processors. A processor is connected via a dedicated interface, and the processor connected to the maintenance processor follows instructions from the maintenance processor,
A processor scan control method, wherein scan-in / scan-out control of a processor group and a bus arbiter is performed using the common bus. 2. When a scan instruction is issued from the maintenance processor, a processor connected to the maintenance processor by a dedicated interface sends a scan request to the bus arbiter, and when the bus arbiter receives the scan request, the common When the bus becomes open, the acceptance of the common bus use request from the processor group is prohibited and the scan permission is sent to all the processors. When all the processors receive the scan permission, the common bus is switched for the scan control. The processor scan control system according to claim 1, wherein the scan operation is performed in response to a scan instruction sent from a processor connected to the maintenance processor via the common bus. 3. The processor scan control system according to claim 1, wherein any one of the plurality of processors also serves as the bus arbiter.