JPH0682784B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device for forming a channel region.

[Conventional technology]

In supplying the source potential and the substrate potential from the power supply wiring material of the conventional MOS type transistor, as shown in FIG. 5, a region 513 required to create a substrate potential supply region overlaps with the gate material 503. Setting, so that the transistor creation regions 501 and 513 overlap, that is, the source region 50.
A substrate potential supply region 502 is realized in 9 and a potential is supplied from the power supply wiring material 517 to the source region via the contacts 514 and 516, and to the substrate potential supply region via the contact 515, or FIG. The region 613 required in the diffusion process to create the substrate potential supply region is
A substrate potential supply region 602 is realized by being completely separated from the transistor creation region 601, and the power supply wiring material 617 makes contact 61
The potential is supplied to the source region via the contacts 4 and 616 and to the substrate potential supply region via the contact 615.

[Problems to be Solved by the Invention]

However, in the above-described conventional technique, in order to obtain stable transistor characteristics, it is necessary to prevent the gate electrode and the substrate potential supply region from overlapping in plan view. Therefore, the distance between the gate electrode and the substrate potential supply region is set to be large in consideration of the alignment margin of the manufacturing apparatus. Therefore, it is not necessary to realize logic in a semiconductor integrated circuit realized by a semiconductor element, but the irregular and redundant arrangement of the substrate potential supply region cannot be ignored for improving element characteristics. Therefore, it has been difficult to realize a semiconductor integrated circuit having a higher degree of integration.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a semiconductor device capable of reducing an unnecessary region in terms of logic realization and stably supplying a substrate potential.

[Means for Solving the Problems]

The semiconductor device of the present invention includes: a) In a MOS transistor, a non-transistor region in which a region forming a source and a drain is removed is present in at least a part of a continuous channel region, and the non-transistor region is separated from the drain region. To form a substrate potential supply region.

[Action]

In the semiconductor device having the above structure, by placing the substrate potential supply region in the non-transistor region,
Even if the gate electrode and the substrate potential supply region overlap in a plane, the stability of the transistor is not affected at all. Therefore, it is not necessary to separate the gate electrode and the substrate potential supply region from each other in consideration of the alignment margin of the manufacturing apparatus.
It is possible to reduce the area that is unnecessary for logic realization, and the characteristics of the semiconductor device are improved because the substrate potential is supplied closer to the gate material.

〔Example〕

 The semiconductor device of the present invention will be described in detail based on embodiments.

The semiconductor device of the present invention is basically as shown in FIG.
1 (b) is a sectional view taken along the dashed line a in FIG. 1 (a), and FIG. 1 (c) is a sectional view taken along the dashed line b in FIG. 1 (a).

In FIG. 1A, 1 and 2 are regions where an oxide film formed on the entire surface of a substrate to form a transistor and a basic potential supply region is removed, and 3 is a region where a gate material is formed. Is. Reference numeral 4 denotes a region required in the diffusion process for forming the source region and the drain region of the transistor, in consideration of the mask alignment margin. Therefore, in FIG. 1 (a), 1 and 3 are non-overlapping portions 5 are non-channel regions, overlapping portions 6 and 7 are channel regions, 9 and 11 are source regions, and 10 and 12 are drain regions. The above transistor exists without being connected to the substrate potential supply region 2. These transistors are connected by the drain connection region 8. 13
Is a region required when a margin for mask alignment is taken into consideration in the diffusion process for forming the substrate potential supply region, and this region is set so as not to overlap the drain connection region 8. 2 is a substrate potential supply region. The source regions 9 and 11 of the respective transistors are supplied with a potential from the power supply wiring material 17 via the contacts 14 and 16, and the substrate potential supply region 2 is supplied with a potential from the power supply wiring material 17 via the contact 15. To be done. The drain region 12 is connected to the drain electrode material 18 via the contact 19 and is drawn out of the element.

FIG. 2 is a circuit diagram explaining FIG. 1 (a) using the element symbol of the PMOS transistor. Incidentally, the resistor 20 of FIG.
8 is the resistance component of the drain connection region 8 of FIG.
Reference numeral 05 is a gate material in the non-channel region 5, and reference numeral 202 is a substrate potential supply region.

The above embodiment is merely one embodiment and is shown in FIG.
As shown in FIG. 3, the substrate potential supply region 2 is completely separated from the source regions 9 and 11, but as shown in FIG.
In addition, the same effect can be seen in the case where the source regions 309 and 311 are connected, or the case where a plurality of non-channel regions, drain connection regions, and substrate potential supply regions are provided as shown in FIG.

〔The invention's effect〕

As described above, according to the present invention, in a MOS transistor, a non-transistor region in which a region forming a source and a drain is removed is present in at least a part of a continuous channel region, and a drain region is formed in the non-transistor region. By forming the substrate potential supply region separately from
A substrate potential supply region can be formed in the vicinity of the gate material, which is not directly necessary for logic realization, but it is possible to suppress the area increase due to this region, which is important for device characteristics, and to supply a stable substrate potential. . That is, in the present invention, in at least a part of the continuous channel region, the non-transistor region in which the regions forming the source and the drain are removed is present, and the non-transistor region is separated from the drain region to form the substrate potential supply region. As a result, the substantial gate width is the sum of the lengths of the gate materials 3 existing on the channel regions 6 and 7. Therefore, even if the substrate potential supply region and the gate material overlap, the substantial gate width is
No influence. Therefore, since it is not necessary to consider the alignment margin of the manufacturing apparatus, miniaturization can be achieved and the transistor characteristics can be stabilized.

[Brief description of drawings]

FIG. 1 (a) is a configuration diagram showing an embodiment, FIG. 1 (b),
FIG. 1C is a sectional view of FIG. FIG. 2 is a circuit diagram when FIG. 1 (a) is a PMOS type transistor. 3 and 4 are views showing another embodiment. FIG. 5 and FIG. 6 are configuration diagrams of a conventional technique. 1, 301, 401, 501, 601 ... Transistor creation area 2, 302, 402, 502, 602 ... Substrate potential supply area 3, 503, 603 ... Gate material 4, 404 ... Diffusion for creating source and drain Regions required in the process 5,405 ... Non-channel regions 6, 7 ... Channel regions 8,408 ... Drain connection regions 9, 11, 309, 311, 509, 609 ... Source regions 10, 12, 510, 610 ... Drain region 13, 313, 413, 513, 613 ... Region required in diffusion process for forming substrate potential supply region 14-16, 19, 514-516, 614-616 ... Contact 17, 317, 417, 517, 617 ... power supply wiring material 18 ... drain electrode material 21-23, 25 ... oxide film 24 ... gate oxide film 26 ... semiconductor substrate 27 ... non-transistor region 202 ... substrate {Fig. 1 Corresponding to 2 in (a)} 209, 211 ... Source 210, 212 ... Drain 206, 207 ... Gate 208 .... Resistance component 205 ...... Figure 1 by in the connection region a gate material on the non-channel region 5 (a)

Claims (1)

[Claims] 1. A semiconductor device having an insulated gate field effect transistor, comprising: a first gate electrode and a second gate electrode which are formed in a continuous wiring and are separated from each other; and a semiconductor substrate adjacent to the first gate electrode. A first region consisting of a first source region and a first drain region, a second region consisting of a second source region and a second drain region provided on the semiconductor substrate next to the second gate electrode, the first region, the A non-transistor region surrounded by a second region and the wiring existing between the first gate electrode and the second gate electrode, and a substrate potential supply region provided on the semiconductor substrate as the non-transistor region A semiconductor device characterized by the above.