JPH0682997B2 - MOS differential amplifier circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS differential amplifier circuit, and more particularly to a MOS differential amplifier circuit having a wide common mode input voltage range.

[Conventional technology]

FIG. 2 is a circuit diagram showing a first example of a conventional example, which is a P-channel MOSF.
It is an ET input type.

The P-channel MOSFET input type differential amplifier circuit shown in FIG.
Power supply terminals 13 and 14, input terminals 10 and 11, output terminal 12, P-channel MOSFETs M20 and M21 forming a differential pair, N-channel MOSFETs M22 and M23 as active loads, P-channel MOSFETs as current sources
An N-channel MOSFET M24 that constitutes a differential amplifier stage from M26 and constitutes an output stage, and a P-channel MOSFET as its active load
M25, constant current source I3 that composes bias circuit, P-channel MOSF
Consists of ETM27. C2 is a frequency compensating capacitor.

When the in-phase input voltage approaches the power supply voltage of the positive power supply terminal 13, the P-channel MOSFET input differential amplifier circuit outputs a differential pair M20, M2.
1 and M26 as a current source cannot operate normally at a constant current value. Therefore, the common mode input voltage is
For the power supply voltage of M26, the drain of M26
It becomes lower than the sum of the saturation voltage V _DSsat between sources and the gate-source voltage V _GS of the differential pair M20, M21.

Similarly, in the N-channel MOSFET input type differential amplifier circuit (not shown) in which the polarity of the transistor of the P-channel MOSFET input type differential amplifier circuit is changed, the lower limit of the common mode input voltage is the negative side this time. Limited by the power supply voltage of the power supply terminal 14.

In order to improve the above-mentioned drawback that the common-mode input voltage range is limited, a circuit as shown in FIG. 3 is disclosed in Japanese Patent Application No. 59-22.
No. 8612.

The circuit configuration is as follows: a first differential pair composed of power supply terminals 23, 24, input terminals 20, 21, output terminal 22, N-channel MOSFETs M37, M38, P-channel MOSFETs M39, M40 as an active load, and a current source. First differential amplifier circuit composed of N-channel MOSFET M36, a second differential pair composed of P-channel MOSFETs M30 and M31, and a P-channel MOSF as a current source.
Drain of ETM45 and M30, and M37 of the first differential amplifier circuit
A first current mirror circuit composed of N-channel MOSFETs M32 and M33 connected to the drain of M31, and an N-channel M connected to the drain of M31 and the drain of M38 of the first differential amplifier circuit.
A differential amplifier stage including a second differential amplifier circuit including a second current mirror circuit including OSFETs M34 and M35 and a P-channel MO
A constant current source I4, N forming a bias circuit and an output stage consisting of an SFET M41 and an N-channel MOSFET M42 as an active load.
It is composed of a channel MOSFET M43 and a P-channel MOSFET M44. C3 is a frequency compensating capacitor.

In the circuit as shown in FIG. 3, when the in-phase input voltage approaches the power supply voltage of the positive power supply terminal 23, the second differential amplifier circuit side composed of the differential pair composed of M30 and M31 is The common-mode input voltage is limited, but the first differential amplifier circuit side composed of the differential pair composed of M37 and M38 is not subject to such limitation. Conversely, the in-phase input voltage is negative power supply terminal 24
When approaching the power supply voltage of, the second differential amplifier circuit side composed of the differential pair constituted by M30 and M31 is not restricted by the common mode input voltage.

Therefore, the common-mode input voltage range is almost full of the positive-side and negative-side power supply voltages, and the disadvantage that the common-mode input voltage in the circuit as shown in FIG. 2 is limited is improved.

[Problems to be Solved by the Invention]

The circuit as shown in FIG. 3 for improving the above-mentioned drawback that the common mode input voltage is limited has the following drawbacks.

The offset voltage in the MOS differential amplifier circuit is roughly divided into the elements that are required to be matched due to manufacturing reasons, and a mismatch that should not occur ideally occurs. Therefore, there are two types that occur even if all the elements are ideal.

Here, regarding the offset voltage, only the latter one will be considered and will be simply referred to as an offset voltage hereinafter.

In the circuit shown in FIG. 2, the cause of the offset voltage is that the gate-source voltages of M22 and M23 are generally the same, but the drain-source voltages are not always the same, so the drain currents of M22 and M23 are not the same. Is different. However, the gate-source voltage of M24 is
If they are equal to the source voltage, M22 and M23 have the same gate-source voltage and drain-source voltage, the drain currents of M22 and M23 are equal, and no offset voltage is generated.
Therefore, the transistor size By selecting, the gate and source voltages of M22, M23 and M24 can be made equal and the offset voltage can be eliminated.

Similarly, in the circuit shown in FIG. 3, in order to make the gate-source voltage of M41 equal to the gate-source voltage of M39 and M40, M39 (M40) has a drain current of M37 (M38) as well as M33 (M38). Note that the drain current of (M35) flows,
It is considered that the offset voltage can be eliminated by selecting the transistor size as in the following equation.

However, when the common-mode input voltage is near the power supply voltage of the positive power supply terminal 23, the second differential pair composed of M30 and M31 and M45 as a current source do not operate normally at a constant current value. The current flowing through (M40) is almost exclusively the drain current of M37 (M38), and the current flowing through M41 is constant, whereas the current flowing through M39 and M40 changes.
Even if the transistor size is selected as shown in equation (2), the common-mode input voltage is M39, M4 near the power supply voltage of the positive power supply terminal 23.
There is a drawback that the gate and source voltages of 0 and M41 are not equal and an offset voltage is generated.

The same applies when the in-phase input voltage is near the power supply voltage of the negative power supply terminal 24.

An object of the present invention is to provide a differential stage composed of a combination of first and second differential amplifier circuits having different polarities, and an MO of an active load of the differential stage.
By detecting the current flowing in the SFET and providing an output stage of the MOSFET through which a current proportional to the current value flows, the common mode input voltage range can be taken up to the full positive and negative side power supply voltage, and the common mode input An object is to provide a MOS differential amplifier circuit that does not generate an offset voltage even when the voltage is near the power supply voltage.

[Means for Solving the Problems]

The MOS differential amplifier circuit of the present invention has a first differential pair composed of two MOSFETs of the first conductivity type whose gates are respectively connected to the first and second input terminals, a common source and a first differential pair. A first constant current source provided between the two power supply terminals, and a current mirror type second conductivity provided between the drains of the MOSFETs forming the first differential pair and the first power supply terminal. Differential amplifier circuit consisting of two load MOSFETs of the second type, and two second differential amplifiers whose gates are respectively connected to the first and second input terminals.
A second differential pair composed of a conductivity type MOSFET, a second constant current source provided between the common source thereof and the first power supply terminal, and one of the first differential pair constituting the second differential pair. 1 MOSFET
Of the first conductivity type MOSFET connected to the drains of the MOSFETs forming the differential pair of the first differential amplifier circuit and having a common drain and the second MOSFET on the other hand. The first differential amplifier has a common drain and a drain of a second MOSFET forming the second differential pair and a first MOSFET forming the second differential pair. A differential amplification stage including a second differential amplification circuit including a second current mirror circuit including two first conductivity type MOSFETs connected to drains of MOSFETs forming a differential pair of the circuit; A second conductivity type MOSF that detects a current flowing in the load MOSFET of the first differential amplifier circuit and flows a current proportional to the current value.
And an output stage composed of ET.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention.

The MOS differential amplifier circuit shown in FIG. 1 includes a first differential pair composed of input terminals 1 and 2, output terminal 3, power supply terminals 4 and 5, N-channel MOSFETs M7 and M8, and a P as an active load. Channel MOSFET
A first differential amplifier circuit comprising M9, M10 and a current source I2, and P
The second differential pair formed by the channel MOSFETs M1 and M2, the drains of the current sources I1 and M1 and the first differential amplifier circuit
A first current mirror circuit composed of N-channel MOSFETs M3 and M4 connected to the drain of M9, M2, and an N-channel MOSFET M connected to the drain of M8 of the first differential amplifier circuit.
5, a differential amplifier stage composed of M6 to a second differential amplifier circuit composed of a second current mirror circuit, M9 as an active load in the first differential amplifier circuit, and a third current mirror circuit A fourth current mirror circuit composed of P-channel MOSFET M11 and N-channel MOSFETs M12 and M13, which uses the drain current of M11 as an input current, and is proportional to the current flowing through M9 by the third and fourth current mirror circuits. The output stage is composed of a P-channel MOSFET M14 which folds back a current and in which a current proportional to the current flowing through M9 flows through the fourth current mirror circuit. C1 is a capacitance for frequency compensation.

The MOS differential amplifier circuit shown in FIG. 1 differs from the conventional MOS differential amplifier circuit having a wide common-mode input voltage range shown in FIG. 3 by the combination of the first and second differential amplifier circuits having different polarities. Since the driving stage is configured, the common-mode input voltage range can be set to the full power supply voltage of the positive and negative power supply terminals 4 and 5.

Regarding the offset voltage, the current flowing through M14 is M
Because it is proportional to the current flowing through 9, M9, M10, M if the transistor size is selected so that
The gate-source voltages of 14 are equal and no offset voltage is generated.

Further, in the vicinity of the power supply voltage of the power supply terminal 4 on the positive side of the common mode input voltage, the first differential pair composed of M1 and M2 and the current source I1 do not operate normally at the constant current value, and M9 and M10 Even if the flowing current changes, the change is detected by the third and fourth current mirror circuits, and the current flowing in M14 is also changed.
Since a current proportional to the current flowing in M9 flows, if the transistor size is selected as shown in equation (3), the gate-source voltage of M9, M10, M14 can be set even when the common-mode input voltage is near the power supply voltage of power supply terminal 4 on the positive side. Does not generate an offset voltage equally.

Similarly, no offset voltage is generated even when the in-phase input voltage is near the power supply voltage of the power supply terminal 5 on the negative side.

〔The invention's effect〕

As described above, the present invention detects the current flowing through the differential stage composed of a combination of the first and second differential amplifier circuits having different polarities and the MOSFET of the active load of the differential stage, and outputs the detected current value. By supplying a proportional current to the MOSFET in the output stage, the common-mode input voltage range can be taken up to the full positive and negative power supply voltage, and offset voltage is not generated even when the common-mode input voltage is near the power supply voltage. There is.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a first conventional example, and FIG. 3 is a circuit diagram showing a second conventional example. 1,2,10,11,20,21 …… Input terminal, 3,12,22 …… Output terminal,
4,13,23 …… Positive power supply terminal, 5,14,24 …… Negative power supply terminal, M1, M2, M9 to M11, M14, M20, M21, M25 to M27, M30, M31, M39 to M4
1, M44, M45 ... P-channel MOSFET, M3 to M8, M12, M13, M22
~ M24, M32 ~ M38, M42, M43 ... N-channel MOSFET, I1 ~ I4
…… Constant current source, C1 to C3 …… Capacity.

Claims (1)

[Claims] 1. A first gate composed of two MOSFETs of a first conductivity type whose gates are respectively connected to first and second input terminals.
Differential pair, a common source of the first differential pair, and a first constant current source provided between the second power supply terminal and a drain of each of the MOSFETs forming the first differential pair. Two loads of the second conductivity type in the form of a power supply mirror provided between the first power supply terminals
A first differential amplifier circuit composed of a MOSFET, a second differential pair composed of two second conductivity type MOSFETs whose gates are connected to the first and second input terminals, respectively, and the second differential pair. A second constant current source provided between a common source and a first power supply terminal, and a drain of one first MOSFET forming the second differential pair, and the second differential pair are formed. On the other hand, the second MOSFET
A first current mirror circuit composed of two MOSFETs of the first conductivity type connected to the drains of the MOSFETs forming a differential pair of the first differential amplifier circuit having a common gate Of the MOSFET forming the differential pair of the first differential circuit in which the drain of the second MOSFET forming the differential pair and the first MOSFET forming the second differential pair have a common gate; A second differential amplifier circuit formed of a second current mirror circuit composed of two MOSFETs of the first conductivity type connected to the drain and a current flowing through the load MOSFET of the first differential amplifier circuit are detected. And a common output of the first and second differential amplifier circuits through which a current proportional to the current value flows and a source-grounded second conductivity type MOSFET connected to the gate. Differential amplifier circuit.