JPH0683000B2 - Amplifier - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier device, and more particularly to detecting the level of an input signal and the amplification factor of an amplifier circuit including a level adjusting circuit, and predicting an output signal of the amplifier circuit. By doing so, the present invention relates to an amplifying device configured to change the operating point and the power supply voltage of the amplifying element of the amplifying circuit.

(Prior Art) In recent years, in addition to conventional analog signal records and tapes, CDs (compact discs) capable of reproducing digital signals have become popular as audio sources (signal sources). This CD has many characteristics, but its dynamic range is over 90 dB.

Therefore, it is necessary for the amplifier circuit to also support a larger dynamic range than before, and the power supply voltage of the amplifier circuit must be increased so as not to clip even the maximum input signal, and the operating point of the amplifier element should also be set correspondingly. is there.

However, since the operating point and the power supply voltage of the amplifier circuit are set so that a correct signal can be obtained even when the input signal level is high, an excessive operating current will flow when the input signal level is low. .

Moreover, the ratio of the time when the maximum input signal is supplied to the amplifier circuit is small, and in most of the time, useless current flows in the amplifier element of the output stage, and in heat generation, power consumption efficiency and equipment durability, It was not preferable.

In order to solve these problems, an amplifier device configured to detect the level of an input signal supplied to an amplifier circuit and vary the operating point and power supply voltage of an amplifier element at the output stage of the amplifier circuit in accordance with the level. There was more than before.

FIG. 2 is a circuit diagram of the above-described conventional amplifying device. In FIG. 2, an analog signal such as music supplied to the input terminal 20 is amplified by the amplifying circuit 21 and then output to the output terminal 22. ing. The level of the signal supplied to the input terminal 20 is discriminated by the control circuit 23, and the switch 24 composed of a transistor is controlled in accordance with this level.

The input terminal 25 is supplied with a DC voltage Vl from a circuit (not shown), and this voltage Vl is forwarded to one end of a large-capacity capacitor C ₂ whose other end is grounded and a diode D ₃ to the amplifier circuit 21. It is supplied as drive power.

Similarly, the input terminal 26 is also supplied with a DC voltage Vh from a circuit (not shown), and this voltage Vh is supplied to the amplifier circuit 21 via one end of a large capacity capacitor C ₃ whose other end is grounded and the switch 24. ing. Here, the voltage Vh> Vl.

In the amplifying apparatus having the above configuration, when the signal supplied to the input terminal 20 is below a predetermined level, the control circuit 23 detects this and opens the switch 24 so that the voltage Vl lower than the input terminal 25 is It is supplied to the amplifier circuit 21.

Here, when the signal supplied to the input terminal 20 exceeds a predetermined level, the control circuit 23 detects this and switches the switch 24.
The voltage higher than the input terminal 26, Vh, is
Since it is supplied to the amplifier 21, the amplifier circuit 21 amplifies a signal with a high input level without clipping and outputs it.
The signal is taken out to 22.

Diode D ₃ is a capacitor when switch 24 is closed.
It is inserted so that the charging current will flow from C ₃ to capacitor C ₂ and voltage Vh will not drop.

Further, the capacity of the capacitor C ₃ needs to be large so that the voltage Vh does not decrease due to the electrostatic capacity of the amplifier circuit 21 when the switch 24 is closed.

(Problems to be Solved by the Invention) As described above, in the conventional amplification device, in order to determine the output signal of the amplification circuit, prediction was made by detecting only the input signal level. Even if the input signal level is constant, since the output signal level of the amplifier circuit fluctuates by the listener adjusting the level adjustment circuit, so-called volume, only the input signal level is detected,
Changing the operating point of the amplifier element of the amplifier circuit and the power supply voltage supplied to the amplifier circuit is not appropriate, and there is a problem that distortion occurs.

(Means for Solving the Problems) In order to solve the above problems, the present invention delays an input signal to be amplified by a delay circuit and then amplifies the input signal, and the input signal is delayed within the delay time of the delay circuit. The level of the input signal in an amplifier device that detects the level of the input signal and changes the operating point of the amplifier element of the amplifier circuit and the output voltage of the power supply circuit that supplies power to the amplifier circuit in accordance with the detected level. For detecting the level of the input signal of the level adjusting circuit for adjusting the level of the input signal of the amplifier circuit, and the level of the output signal of the amplifier circuit. A third peak detection circuit for detecting, a division circuit for dividing an output signal of the third peak detection circuit by an output signal of the second peak detection circuit, and an output signal of the division circuit A multiplication circuit for multiplying the output signal of the first peak detection circuit and a gate circuit for switching the output signal of the multiplication circuit and the output signal of the first peak detection circuit are provided, and the first or second
When the output signal of the peak detection circuit of is above a predetermined level,
The operating point and the power supply voltage of the amplifier circuit are varied based on the output signal of the multiplication circuit, and when the output signal of the first or second peak detection circuit is below a predetermined level, the first
The present invention provides an amplifying device characterized in that the operating point and the power supply voltage of the amplifying circuit are varied based on the output signal of the peak detecting circuit.

(Embodiment) FIG. 1 is a block system diagram showing an embodiment of an amplifier of the present invention. In the figure, 1 is an input terminal group to which a digital signal to be amplified is supplied. The signal supplied to this input terminal group 1 is a selector 2 and a DIR (Digital Int.
erface Receiver) 3, delay circuit 4, D / A converter 5,
The level adjusting circuit 6 and the amplifier circuit 7 are serially supplied to the output terminal 8.

The output signals of the DIR3, the D / A converter 5 and the amplifier circuit 7 are supplied to the control circuit 9, and the output signals of the control circuit 9 are supplied to the amplifier circuit 7 and the power supply circuit 10, respectively. The output voltage of the power supply circuit 10 is supplied to the amplifier circuit 7.

The control circuit 9 includes a D / A converter 11 and a peak detection circuit P ₁
To P _3, determination circuit 12, a driver 13, comparator circuit COM2, an amplifier circuit AMP, is constituted by a gate circuit GA, further discrimination circuit 12 division circuit DIV, multiplication circuit MUL, and is configured from the comparison circuit COM1.

The output signal of DIR3 is sent to the peak detection circuit P ₁ via the D / A converter 11, the output signal of the D / A converter 5 is sent to the peak detection circuit P ₂ , and the output signal of the amplifier circuit 7 is sent to the peak detection circuit P ₃ . Each is supplied.

The output signals of the peak detection circuits P ₂ and P ₃ are supplied to the division circuit DIV, and the output signal of the division circuit DIV is supplied to the multiplication circuit MUL together with the output signal of the peak detection circuit P ₁ . The output signals of the peak detection circuits P ₁ and P ₂ are respectively supplied to the amplification circuit AMP and the comparison circuit COM2, and the output signal of the amplification circuit AMP and the output signal of the multiplication circuit MUL are the two respective input terminals of the gate circuit GA. Is being supplied to.

The output signal of the comparison circuit COM2 is supplied to the control terminal of the gate circuit GA, and the output signal of the gate circuit GA is supplied to the driver 13 via the comparison circuit COM1.
Is output to the amplifier circuit 7 and the power supply circuit 10 as an output signal of the control circuit 9.

FIG. 3 is a waveform diagram for explaining the operation of FIG. 1, FIG. 4 is a partial circuit diagram of the power supply circuit 10, and FIG. 5 is a level diagram for explaining the operation of FIG.

Next, the operation of one embodiment of the amplification device of the present invention will be described.
A digital signal from, for example, a CD player or a digital tape recorder is supplied to the input terminal group 1, and a desired signal is selected by the selector 2 from these signals. The selected signal is error-corrected by DIR3 and processed into a serial digital signal, and delayed by the delay circuit 4 at time td.
After delaying only, it is converted into an analog signal by the D / A converter 5.

The signal a shown in FIG. 3 (A) is an analog signal corresponding to the input signal of the delay circuit 4, and the signal b shown in FIG. 3 (B) is
This is the output signal of the D / A converter 5. The analog signal b is adjusted to a desired level by the level adjusting circuit 6, amplified by the amplifying circuit 7, supplied to a speaker (not shown) or the like via the output terminal 8, and reproduced as sound.

On the other hand, signals from DIR3 supplied to the control circuit 9 is converted into an analog signal by a D / A converter 11, where the peak detection circuit P _1, the full-wave rectified value is output.

At this time, the D / A converter 11 only needs to obtain an analog signal of such a quality that the discriminating circuit 12 can discriminate the level. Therefore, if the upper half bits of the supplied digital signal are converted to the analog signal. good.

Further, the output signals of the D / A converter 5 and the amplifier circuit 7 are supplied to the peak detection circuits P ₂ and P ₃ , respectively, and the peak detection circuits P ₂ and P ₃ perform full-wave rectification on the supplied signals. Send out.

The voltage values sent by the peak detection circuits P _{1 to} P ₃ are
When V _{1 to} V ₃ are set, the division circuit DIV calculates V ₃ / V ₂ to obtain the total amplification factor of the level adjustment circuit 6 and the amplification circuit 7.
Av is obtained.

This amplification factor Av is changed by the listener who adjusts the level adjusting circuit 6, so-called volume, and is calculated as described above.

The multiplying circuit MUL calculates the output signal level V ₀ of the amplifying circuit 7 after the delay time td by multiplying the voltage value V ₁ sent by the peak detecting circuit P ₁ by the amplification factor Av, which is a prediction.

Here, it is assumed that the gate circuit GA passes the output signal of the multiplication circuit MUL by the control signal from the comparison circuit COM2. At this time, the output signal level V ₀ is compared with a preset reference value in the comparison circuit COM1.

However, since the output signal level V ₀ has a large value, in consideration of the operating voltage of the IC or the like that constitutes the discrimination circuit 12, in practice,
The peak detection circuit P ₃ sends the value multiplied by the coefficient 0.18, and conversely the value before amplification is small, so the peak detection circuits P ₁ and P ₂
The value multiplied by 3.2 is sent.

Therefore, when the comparison circuit COM1 determines that the output signal level V ₀ has reached the predetermined value, it sends a detection signal to the driver 13.
A logic H as shown in FIG. 3 (C) is obtained only for the sum of the time t0 when the level is equal to or higher than a predetermined value and the delay time td of the delay circuit 4.
Pulse signal c is generated. The pulse signal c causes the driver 13 to switch the power supply voltage supplied from the power supply circuit 10 to the amplifier circuit 7 and the operating point of the amplifier circuit 7.

However, when the input signal is not supplied to the input terminal group 1 or when the input signal is a music pianissimo, the output signal levels of the peak detection circuits P ₁ and P ₂ are zero or low.

Therefore, the operation of the multiplication circuit MUL and the division circuit DIV is likely to be unstable, and the output signal level of the amplification circuit 7 is low,
Since it is not necessary to predict this, the peak detection circuit P ₁
The output signal of is amplified by the amplifier circuit AMP and then supplied to the comparison circuit COM1.

Here, when the comparison circuit COM2 detects a predetermined value (here, 0.67 V) or less, the gate circuit GA is controlled so as to pass the output signal of the amplification circuit AMP.

The horizontal axis of FIG. 5 represents the input voltage of the level adjusting circuit 6, and the vertical axis represents the total amplification degree of the level adjusting circuit 6 and the amplifier circuit 7. In the figure, the straight line A indicates the line where the output voltage obtained at the output terminal 8 is 10.95V (20W / 6Ω), and the comparison circuit C
When OM1 exceeds this straight line A, the power supply voltage and operating point of the amplifier circuit 7 are switched.

The straight line B is also a line with an output voltage of 32.86 V (180 W / 6 Ω), and shows that the output voltage obtained at the output terminal 8 clips in a region beyond this. For example, the input voltage is 2V at maximum according to the standard of the D / A converter 5, and if the gain of the amplifier circuit 7 is set to 45dB, the level adjustment circuit 6 must attenuate by 20.7dB or more in order to prevent the output voltage from clipping. I have to.

Therefore, when the comparison circuit COM2 detects a predetermined value or less, the gate circuit GA controls so that the output signal of the amplifier circuit AMP passes through.

FIG. 4 shows a rectifier circuit 10 'showing a part of the power supply circuit 10. In FIG. 4, when the signal c is logic L, the switch S is l.
On the other hand, when the signal c is logic H, the switch S is connected to the h side.

Period of the switch S is connected to the l-side AC voltage vl is rectified by the diode D ₁ supplied through the input terminal 15 from the circuit (not shown), the amplifier circuit as a DC voltage Vl is smoothed by the capacitor C ₁ 7 is supplied.

Here, when the switch S is connected from the l side to the h side, the AC voltage vh (vl <vh) supplied through the input terminal 16 is rectified by the diode D _{2 and the} capacitor C ₁ is supplied as the DC voltage Vh. Is supplied to.

Therefore, the voltage at the terminal of the capacitor C ₁ changes from the voltage Vl to the voltage Vh.
In addition, as shown in FIG. 3 (D), the signal d which rises in time tc is obtained. This time tc is the delay time td
The impedance of the rectifier circuit system is set in advance so as to be within the range by considering the electrostatic capacitance of the capacitor C ₁ .

Further, at the same time as the switching of the power supply voltage, the operating point of the amplification element of the amplification circuit 7 is switched to the optimum value by the logic H signal from the driver 14 in correspondence with the power supply voltage.

As described above, since the input signal of the predetermined level or more is supplied to the amplifier circuit 7 with a delay of the delay time td, the power supply voltage of the amplifier circuit 7 increases at that time, and the operating point is controlled to change to the optimum value. Therefore, even if an abrupt pulse-like large-amplitude input signal is supplied to the amplifier circuit 7, amplification can be performed without causing signal loss or distortion.

Although the voltage of the power supply circuit 10 is switched in two stages in the above embodiment, it is possible to increase the number of discrimination stages of the discrimination circuit 12 and increase the number of voltage switching stages of the power supply circuit 10.

(Effect of the Invention) According to the present invention, the listener can adjust the volume (level adjustment circuit).
Even if you adjust, before performing amplification by delaying the input signal to be amplified, calculate and detect how much the level of the input signal becomes the output signal of the amplifier circuit,
Since the operating point of the amplification element of the amplification circuit and the power supply voltage are changed to optimum values, an output signal without signal loss or distortion can be obtained, and an amplification device with high power efficiency can be obtained, and further input There is a feature that the above operating point and the power supply voltage can be adjusted stably even when the signal is not supplied or when the input signal has a signal level of zero or low like a music pianissimo.

[Brief description of drawings]

FIG. 1 is a block system diagram showing an embodiment of an amplification device of the present invention, FIG. 2 is a circuit diagram of a conventional amplification device, and FIG.
FIG. 4 is a waveform diagram for explaining the operation of the figure, FIG. 4 is a partial circuit diagram of the power supply circuit 10, and FIG. 5 is a level diagram for explaining FIG. 1 …… Input terminal group, 2 …… Selector, 3 …… DIR (Digit
al Interface Receiver), 4 ... delay circuit, 5, 11 ... D
/ A converter, 6 ... Level adjustment circuit, 7, AMP ... Amplification circuit, 8 ... Output terminal, 9 ... Control circuit, 10 ... Power supply circuit, 12 ... Discrimination circuit, 13 ... Driver, COM1, COM2 ……
Comparison circuit, DIV ... Division circuit, GA ... Gate circuit, MUL ...
… Multiply circuit, P _{1 to} P ₃ … Peak detection circuit.

Claims (1)

[Claims] 1. An input signal to be amplified is delayed by a delay circuit and then amplified, and within the delay time of the delay circuit,
A first peak for detecting the level of the input signal in an amplifier device that detects the level of the input signal and changes the operating point and the power supply voltage of the amplifier element of the amplifier circuit in accordance with the detected level. A detection circuit, a second peak detection circuit that detects the level of the input signal of the level adjustment circuit that adjusts the level of the input signal of the amplification circuit, and a third peak detection circuit that detects the level of the output signal of the amplification circuit. A circuit, a division circuit for dividing the output signal of the third peak detection circuit by the output signal of the second peak detection circuit, an output signal of the division circuit and an output of the first peak detection circuit And a gate circuit for switching between the output signal of the multiplication circuit and the output signal of the first peak detection circuit, and the output signal of the second peak detection circuit is a predetermined level. When the output signal of the second peak detection circuit is equal to or lower than a predetermined level, the operating point and the power supply voltage of the amplification circuit are varied based on the output signal of the multiplication circuit. The operating point and the power supply voltage of the amplifying circuit are changed based on the output signal of the peak detecting circuit.